Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 4 | #include <amdblocks/acpimmio.h> |
Felix Held | dea4e0f | 2021-09-22 20:05:53 +0200 | [diff] [blame] | 5 | #include <amdblocks/gpio.h> |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 6 | #include <amdblocks/gpio_defs.h> |
| 7 | #include <amdblocks/i2c.h> |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame] | 8 | #include <console/console.h> |
| 9 | #include <delay.h> |
| 10 | #include <device/device.h> |
| 11 | #include <device/i2c.h> |
| 12 | #include <device/mmio.h> |
| 13 | #include <drivers/i2c/designware/dw_i2c.h> |
Felix Held | 96c4882 | 2021-08-02 19:48:40 +0200 | [diff] [blame] | 14 | #include <gpio.h> |
Angel Pons | c57cae8 | 2021-03-25 11:29:32 +0100 | [diff] [blame] | 15 | #include <types.h> |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 16 | |
| 17 | #define MAX_PIN_COUNT 4 |
| 18 | |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame] | 19 | uintptr_t dw_i2c_base_address(unsigned int bus) |
| 20 | { |
| 21 | size_t num_ctrlrs; |
| 22 | const struct soc_i2c_ctrlr_info *ctrlr = soc_get_i2c_ctrlr_info(&num_ctrlrs); |
| 23 | |
| 24 | if (bus >= num_ctrlrs) { |
Angel Pons | cf72a51 | 2021-03-25 11:15:32 +0100 | [diff] [blame] | 25 | printk(BIOS_ERR, "Bus ID %u is >= number of I2C controllers %zu\n", |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame] | 26 | bus, num_ctrlrs); |
| 27 | return 0; |
| 28 | } |
| 29 | |
| 30 | return ctrlr[bus].bar; |
| 31 | } |
| 32 | |
| 33 | const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) |
| 34 | { |
| 35 | size_t num_buses = 0; |
| 36 | const struct dw_i2c_bus_config *cfg = soc_get_i2c_bus_config(&num_buses); |
| 37 | |
| 38 | if (bus >= num_buses) { |
Angel Pons | cf72a51 | 2021-03-25 11:15:32 +0100 | [diff] [blame] | 39 | printk(BIOS_ERR, "Bus ID %u is >= number of I2C buses %zu\n", bus, num_buses); |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame] | 40 | return NULL; |
| 41 | } |
| 42 | |
| 43 | return &cfg[bus]; |
| 44 | } |
| 45 | |
| 46 | static const char *i2c_acpi_name(const struct device *dev) |
| 47 | { |
| 48 | size_t i; |
| 49 | size_t num_ctrlrs; |
| 50 | const struct soc_i2c_ctrlr_info *ctrlr = soc_get_i2c_ctrlr_info(&num_ctrlrs); |
| 51 | |
| 52 | if (!(uintptr_t)dev->path.mmio.addr) |
| 53 | die("NULL MMIO address at %s\n", __func__); |
| 54 | |
| 55 | for (i = 0; i < num_ctrlrs; i++) { |
| 56 | if ((uintptr_t)dev->path.mmio.addr == ctrlr[i].bar) |
| 57 | return ctrlr[i].acpi_name; |
| 58 | } |
| 59 | printk(BIOS_ERR, "%s: Could not find %lu\n", __func__, (uintptr_t)dev->path.mmio.addr); |
| 60 | return NULL; |
| 61 | } |
| 62 | |
| 63 | int dw_i2c_soc_dev_to_bus(const struct device *dev) |
| 64 | { |
| 65 | size_t i; |
| 66 | size_t num_ctrlrs; |
| 67 | const struct soc_i2c_ctrlr_info *ctrlr = soc_get_i2c_ctrlr_info(&num_ctrlrs); |
| 68 | |
| 69 | if (!(uintptr_t)dev->path.mmio.addr) |
| 70 | die("NULL MMIO address at %s\n", __func__); |
| 71 | |
| 72 | for (i = 0; i < num_ctrlrs; i++) { |
| 73 | if ((uintptr_t)dev->path.mmio.addr == ctrlr[i].bar) |
| 74 | return i; |
| 75 | } |
| 76 | printk(BIOS_ERR, "%s: Could not find %lu\n", __func__, (uintptr_t)dev->path.mmio.addr); |
| 77 | return -1; |
| 78 | } |
| 79 | |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame] | 80 | static void dw_i2c_soc_init(bool is_early_init) |
| 81 | { |
| 82 | unsigned int bus; |
| 83 | size_t num_buses = 0, num_ctrlrs = 0; |
| 84 | const struct dw_i2c_bus_config *cfg = soc_get_i2c_bus_config(&num_buses); |
| 85 | const struct soc_i2c_ctrlr_info *ctrlr = soc_get_i2c_ctrlr_info(&num_ctrlrs); |
| 86 | |
| 87 | /* Ensure that the number of controllers in devicetree and SoC match. */ |
| 88 | assert(num_buses == num_ctrlrs); |
| 89 | |
| 90 | for (bus = 0; bus < num_buses; bus++, cfg++, ctrlr++) { |
| 91 | /* |
| 92 | * Skip initialization when controller is in peripheral mode or base address |
| 93 | * is not configured or is not the expected stage to initialize. |
| 94 | */ |
| 95 | if (ctrlr->mode == I2C_PERIPHERAL_MODE || !ctrlr->bar || |
| 96 | cfg->early_init != is_early_init) |
| 97 | continue; |
| 98 | |
Felix Held | 3d94589 | 2022-01-31 15:52:36 +0100 | [diff] [blame] | 99 | if (dw_i2c_init(bus, cfg) != CB_SUCCESS) { |
Angel Pons | cf72a51 | 2021-03-25 11:15:32 +0100 | [diff] [blame] | 100 | printk(BIOS_ERR, "Failed to init i2c bus %u\n", bus); |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame] | 101 | continue; |
Felix Held | a16a09f | 2021-03-25 02:07:23 +0100 | [diff] [blame] | 102 | } |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame] | 103 | |
| 104 | soc_i2c_misc_init(bus, cfg); |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | void i2c_soc_early_init(void) |
| 109 | { |
| 110 | dw_i2c_soc_init(true); |
| 111 | } |
| 112 | |
| 113 | void i2c_soc_init(void) |
| 114 | { |
| 115 | dw_i2c_soc_init(false); |
| 116 | } |
| 117 | |
Felix Held | c2cee06 | 2021-10-12 23:35:11 +0200 | [diff] [blame] | 118 | static void i2c_read_resources(struct device *dev) |
| 119 | { |
| 120 | mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4); |
| 121 | } |
| 122 | |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame] | 123 | struct device_operations soc_amd_i2c_mmio_ops = { |
Felix Held | c2cee06 | 2021-10-12 23:35:11 +0200 | [diff] [blame] | 124 | .read_resources = i2c_read_resources, |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame] | 125 | .set_resources = noop_set_resources, |
| 126 | .scan_bus = scan_smbus, |
| 127 | .acpi_name = i2c_acpi_name, |
| 128 | .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, |
| 129 | }; |
| 130 | |
Felix Held | 96c4882 | 2021-08-02 19:48:40 +0200 | [diff] [blame] | 131 | static void drive_scl(const struct soc_i2c_peripheral_reset_info *reset_info, int val) |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 132 | { |
Angel Pons | c57cae8 | 2021-03-25 11:29:32 +0100 | [diff] [blame] | 133 | size_t j; |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 134 | |
| 135 | for (j = 0; j < reset_info->num_pins; j++) { |
| 136 | if (reset_info->i2c_scl_reset_mask & reset_info->i2c_scl[j].pin_mask) |
Felix Held | 96c4882 | 2021-08-02 19:48:40 +0200 | [diff] [blame] | 137 | gpio_set(reset_info->i2c_scl[j].pin.gpio, val); |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 138 | } |
| 139 | |
Felix Held | 96c4882 | 2021-08-02 19:48:40 +0200 | [diff] [blame] | 140 | gpio_get(0); /* Flush posted write */ |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 141 | /* |
| 142 | * TODO(b/183010197): 4usec gets 85KHz for 1 pin, 70KHz for 4 pins. Ensure this delay |
| 143 | * works fine for all SoCs and make this delay configurable if required. |
| 144 | */ |
| 145 | udelay(4); |
| 146 | } |
| 147 | |
| 148 | void sb_reset_i2c_peripherals(const struct soc_i2c_peripheral_reset_info *reset_info) |
| 149 | { |
Felix Held | f363ad4 | 2021-07-31 03:59:28 +0200 | [diff] [blame] | 150 | struct soc_amd_gpio_register_save save_table[MAX_PIN_COUNT]; |
Angel Pons | c57cae8 | 2021-03-25 11:29:32 +0100 | [diff] [blame] | 151 | size_t i; |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 152 | |
| 153 | if (!reset_info || !reset_info->i2c_scl || !reset_info->num_pins || |
| 154 | !reset_info->i2c_scl_reset_mask) |
| 155 | return; |
| 156 | |
| 157 | assert(reset_info->num_pins <= MAX_PIN_COUNT); |
| 158 | |
| 159 | /* Save and reprogram I2C SCL pins */ |
| 160 | for (i = 0; i < reset_info->num_pins; i++) { |
Felix Held | 35cee38 | 2021-08-03 02:55:34 +0200 | [diff] [blame] | 161 | /* To program I2C pins without destroying their programming, the registers |
| 162 | that will be changed need to be saved first */ |
| 163 | gpio_save_pin_registers(reset_info->i2c_scl[i].pin.gpio, &save_table[i]); |
Felix Held | 96c4882 | 2021-08-02 19:48:40 +0200 | [diff] [blame] | 164 | /* Program SCL GPIO as output driven high */ |
Felix Held | 7011fa1 | 2021-09-22 16:36:12 +0200 | [diff] [blame] | 165 | gpio_configure_pads(&reset_info->i2c_scl[i].pin, 1); |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | /* |
| 169 | * Toggle SCL back and forth 9 times under 100KHz. A single read is |
| 170 | * needed after the writes to force the posted write to complete. |
| 171 | */ |
| 172 | for (i = 0; i < 9; i++) { |
Felix Held | 96c4882 | 2021-08-02 19:48:40 +0200 | [diff] [blame] | 173 | drive_scl(reset_info, 1); |
| 174 | drive_scl(reset_info, 0); |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | /* Restore I2C pins. */ |
| 178 | for (i = 0; i < reset_info->num_pins; i++) |
Felix Held | 35cee38 | 2021-08-03 02:55:34 +0200 | [diff] [blame] | 179 | gpio_restore_pin_registers(reset_info->i2c_scl[i].pin.gpio, &save_table[i]); |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 180 | } |