Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <delay.h> |
| 5 | #include <amdblocks/acpimmio.h> |
| 6 | #include <amdblocks/gpio_banks.h> |
| 7 | #include <amdblocks/gpio_defs.h> |
| 8 | #include <amdblocks/i2c.h> |
| 9 | |
| 10 | #define MAX_PIN_COUNT 4 |
| 11 | |
| 12 | struct common_i2c_save { |
| 13 | uint32_t control_value; |
| 14 | uint8_t mux_value; |
| 15 | }; |
| 16 | |
| 17 | /* |
| 18 | * To program I2C pins without destroying their programming, the registers |
| 19 | * that will be changed need to be saved first. |
| 20 | */ |
| 21 | static void save_i2c_pin_registers(uint8_t gpio, struct common_i2c_save *save_table) |
| 22 | { |
| 23 | save_table->mux_value = iomux_read8(gpio); |
| 24 | save_table->control_value = gpio_read32(gpio); |
| 25 | } |
| 26 | |
| 27 | static void restore_i2c_pin_registers(uint8_t gpio, struct common_i2c_save *save_table) |
| 28 | { |
| 29 | /* Write and flush posted writes. */ |
| 30 | iomux_write8(gpio, save_table->mux_value); |
| 31 | iomux_read8(gpio); |
| 32 | gpio_write32(gpio, save_table->control_value); |
| 33 | gpio_read32(gpio); |
| 34 | } |
| 35 | |
| 36 | static void drive_scl(const struct soc_i2c_peripheral_reset_info *reset_info, uint32_t val) |
| 37 | { |
| 38 | uint8_t j; |
| 39 | |
| 40 | for (j = 0; j < reset_info->num_pins; j++) { |
| 41 | if (reset_info->i2c_scl_reset_mask & reset_info->i2c_scl[j].pin_mask) |
| 42 | gpio_write32(reset_info->i2c_scl[j].pin.gpio, val); |
| 43 | } |
| 44 | |
| 45 | gpio_read32(0); /* Flush posted write */ |
| 46 | /* |
| 47 | * TODO(b/183010197): 4usec gets 85KHz for 1 pin, 70KHz for 4 pins. Ensure this delay |
| 48 | * works fine for all SoCs and make this delay configurable if required. |
| 49 | */ |
| 50 | udelay(4); |
| 51 | } |
| 52 | |
| 53 | void sb_reset_i2c_peripherals(const struct soc_i2c_peripheral_reset_info *reset_info) |
| 54 | { |
| 55 | struct common_i2c_save save_table[MAX_PIN_COUNT]; |
| 56 | uint8_t i; |
| 57 | |
| 58 | if (!reset_info || !reset_info->i2c_scl || !reset_info->num_pins || |
| 59 | !reset_info->i2c_scl_reset_mask) |
| 60 | return; |
| 61 | |
| 62 | assert(reset_info->num_pins <= MAX_PIN_COUNT); |
| 63 | |
| 64 | /* Save and reprogram I2C SCL pins */ |
| 65 | for (i = 0; i < reset_info->num_pins; i++) { |
| 66 | save_i2c_pin_registers(reset_info->i2c_scl[i].pin.gpio, &save_table[i]); |
| 67 | program_gpios(&reset_info->i2c_scl[i].pin, 1); |
| 68 | } |
| 69 | |
| 70 | /* |
| 71 | * Toggle SCL back and forth 9 times under 100KHz. A single read is |
| 72 | * needed after the writes to force the posted write to complete. |
| 73 | */ |
| 74 | for (i = 0; i < 9; i++) { |
| 75 | drive_scl(reset_info, GPIO_OUTPUT_OUT_HIGH); |
| 76 | drive_scl(reset_info, GPIO_OUTPUT_OUT_LOW); |
| 77 | } |
| 78 | |
| 79 | /* Restore I2C pins. */ |
| 80 | for (i = 0; i < reset_info->num_pins; i++) |
| 81 | restore_i2c_pin_registers(reset_info->i2c_scl[i].pin.gpio, &save_table[i]); |
| 82 | } |