Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame^] | 3 | #include <acpi/acpi.h> |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 4 | #include <assert.h> |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 5 | #include <amdblocks/acpimmio.h> |
| 6 | #include <amdblocks/gpio_banks.h> |
| 7 | #include <amdblocks/gpio_defs.h> |
| 8 | #include <amdblocks/i2c.h> |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame^] | 9 | #include <console/console.h> |
| 10 | #include <delay.h> |
| 11 | #include <device/device.h> |
| 12 | #include <device/i2c.h> |
| 13 | #include <device/mmio.h> |
| 14 | #include <drivers/i2c/designware/dw_i2c.h> |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 15 | |
| 16 | #define MAX_PIN_COUNT 4 |
| 17 | |
Karthikeyan Ramasubramanian | 4f87ae1 | 2021-03-18 23:16:29 -0600 | [diff] [blame^] | 18 | uintptr_t dw_i2c_base_address(unsigned int bus) |
| 19 | { |
| 20 | size_t num_ctrlrs; |
| 21 | const struct soc_i2c_ctrlr_info *ctrlr = soc_get_i2c_ctrlr_info(&num_ctrlrs); |
| 22 | |
| 23 | if (bus >= num_ctrlrs) { |
| 24 | printk(BIOS_ERR, "Bus ID %d is >= number of I2C controllers %zu\n", |
| 25 | bus, num_ctrlrs); |
| 26 | return 0; |
| 27 | } |
| 28 | |
| 29 | return ctrlr[bus].bar; |
| 30 | } |
| 31 | |
| 32 | const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) |
| 33 | { |
| 34 | size_t num_buses = 0; |
| 35 | const struct dw_i2c_bus_config *cfg = soc_get_i2c_bus_config(&num_buses); |
| 36 | |
| 37 | if (bus >= num_buses) { |
| 38 | printk(BIOS_ERR, "Bus ID %d is >= number of I2C buses %zu\n", bus, num_buses); |
| 39 | return NULL; |
| 40 | } |
| 41 | |
| 42 | return &cfg[bus]; |
| 43 | } |
| 44 | |
| 45 | static const char *i2c_acpi_name(const struct device *dev) |
| 46 | { |
| 47 | size_t i; |
| 48 | size_t num_ctrlrs; |
| 49 | const struct soc_i2c_ctrlr_info *ctrlr = soc_get_i2c_ctrlr_info(&num_ctrlrs); |
| 50 | |
| 51 | if (!(uintptr_t)dev->path.mmio.addr) |
| 52 | die("NULL MMIO address at %s\n", __func__); |
| 53 | |
| 54 | for (i = 0; i < num_ctrlrs; i++) { |
| 55 | if ((uintptr_t)dev->path.mmio.addr == ctrlr[i].bar) |
| 56 | return ctrlr[i].acpi_name; |
| 57 | } |
| 58 | printk(BIOS_ERR, "%s: Could not find %lu\n", __func__, (uintptr_t)dev->path.mmio.addr); |
| 59 | return NULL; |
| 60 | } |
| 61 | |
| 62 | int dw_i2c_soc_dev_to_bus(const struct device *dev) |
| 63 | { |
| 64 | size_t i; |
| 65 | size_t num_ctrlrs; |
| 66 | const struct soc_i2c_ctrlr_info *ctrlr = soc_get_i2c_ctrlr_info(&num_ctrlrs); |
| 67 | |
| 68 | if (!(uintptr_t)dev->path.mmio.addr) |
| 69 | die("NULL MMIO address at %s\n", __func__); |
| 70 | |
| 71 | for (i = 0; i < num_ctrlrs; i++) { |
| 72 | if ((uintptr_t)dev->path.mmio.addr == ctrlr[i].bar) |
| 73 | return i; |
| 74 | } |
| 75 | printk(BIOS_ERR, "%s: Could not find %lu\n", __func__, (uintptr_t)dev->path.mmio.addr); |
| 76 | return -1; |
| 77 | } |
| 78 | |
| 79 | void __weak soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg) |
| 80 | { |
| 81 | /* Nothing by default. */ |
| 82 | } |
| 83 | |
| 84 | static void dw_i2c_soc_init(bool is_early_init) |
| 85 | { |
| 86 | unsigned int bus; |
| 87 | size_t num_buses = 0, num_ctrlrs = 0; |
| 88 | const struct dw_i2c_bus_config *cfg = soc_get_i2c_bus_config(&num_buses); |
| 89 | const struct soc_i2c_ctrlr_info *ctrlr = soc_get_i2c_ctrlr_info(&num_ctrlrs); |
| 90 | |
| 91 | /* Ensure that the number of controllers in devicetree and SoC match. */ |
| 92 | assert(num_buses == num_ctrlrs); |
| 93 | |
| 94 | for (bus = 0; bus < num_buses; bus++, cfg++, ctrlr++) { |
| 95 | /* |
| 96 | * Skip initialization when controller is in peripheral mode or base address |
| 97 | * is not configured or is not the expected stage to initialize. |
| 98 | */ |
| 99 | if (ctrlr->mode == I2C_PERIPHERAL_MODE || !ctrlr->bar || |
| 100 | cfg->early_init != is_early_init) |
| 101 | continue; |
| 102 | |
| 103 | if (dw_i2c_init(bus, cfg)) |
| 104 | printk(BIOS_ERR, "Failed to init i2c bus %d\n", bus); |
| 105 | continue; |
| 106 | |
| 107 | soc_i2c_misc_init(bus, cfg); |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | void i2c_soc_early_init(void) |
| 112 | { |
| 113 | dw_i2c_soc_init(true); |
| 114 | } |
| 115 | |
| 116 | void i2c_soc_init(void) |
| 117 | { |
| 118 | dw_i2c_soc_init(false); |
| 119 | } |
| 120 | |
| 121 | struct device_operations soc_amd_i2c_mmio_ops = { |
| 122 | /* TODO(kramasub): Move I2C resource info here. */ |
| 123 | .read_resources = noop_read_resources, |
| 124 | .set_resources = noop_set_resources, |
| 125 | .scan_bus = scan_smbus, |
| 126 | .acpi_name = i2c_acpi_name, |
| 127 | .acpi_fill_ssdt = dw_i2c_acpi_fill_ssdt, |
| 128 | }; |
| 129 | |
Karthikeyan Ramasubramanian | 0dbea48 | 2021-03-08 23:23:50 -0700 | [diff] [blame] | 130 | struct common_i2c_save { |
| 131 | uint32_t control_value; |
| 132 | uint8_t mux_value; |
| 133 | }; |
| 134 | |
| 135 | /* |
| 136 | * To program I2C pins without destroying their programming, the registers |
| 137 | * that will be changed need to be saved first. |
| 138 | */ |
| 139 | static void save_i2c_pin_registers(uint8_t gpio, struct common_i2c_save *save_table) |
| 140 | { |
| 141 | save_table->mux_value = iomux_read8(gpio); |
| 142 | save_table->control_value = gpio_read32(gpio); |
| 143 | } |
| 144 | |
| 145 | static void restore_i2c_pin_registers(uint8_t gpio, struct common_i2c_save *save_table) |
| 146 | { |
| 147 | /* Write and flush posted writes. */ |
| 148 | iomux_write8(gpio, save_table->mux_value); |
| 149 | iomux_read8(gpio); |
| 150 | gpio_write32(gpio, save_table->control_value); |
| 151 | gpio_read32(gpio); |
| 152 | } |
| 153 | |
| 154 | static void drive_scl(const struct soc_i2c_peripheral_reset_info *reset_info, uint32_t val) |
| 155 | { |
| 156 | uint8_t j; |
| 157 | |
| 158 | for (j = 0; j < reset_info->num_pins; j++) { |
| 159 | if (reset_info->i2c_scl_reset_mask & reset_info->i2c_scl[j].pin_mask) |
| 160 | gpio_write32(reset_info->i2c_scl[j].pin.gpio, val); |
| 161 | } |
| 162 | |
| 163 | gpio_read32(0); /* Flush posted write */ |
| 164 | /* |
| 165 | * TODO(b/183010197): 4usec gets 85KHz for 1 pin, 70KHz for 4 pins. Ensure this delay |
| 166 | * works fine for all SoCs and make this delay configurable if required. |
| 167 | */ |
| 168 | udelay(4); |
| 169 | } |
| 170 | |
| 171 | void sb_reset_i2c_peripherals(const struct soc_i2c_peripheral_reset_info *reset_info) |
| 172 | { |
| 173 | struct common_i2c_save save_table[MAX_PIN_COUNT]; |
| 174 | uint8_t i; |
| 175 | |
| 176 | if (!reset_info || !reset_info->i2c_scl || !reset_info->num_pins || |
| 177 | !reset_info->i2c_scl_reset_mask) |
| 178 | return; |
| 179 | |
| 180 | assert(reset_info->num_pins <= MAX_PIN_COUNT); |
| 181 | |
| 182 | /* Save and reprogram I2C SCL pins */ |
| 183 | for (i = 0; i < reset_info->num_pins; i++) { |
| 184 | save_i2c_pin_registers(reset_info->i2c_scl[i].pin.gpio, &save_table[i]); |
| 185 | program_gpios(&reset_info->i2c_scl[i].pin, 1); |
| 186 | } |
| 187 | |
| 188 | /* |
| 189 | * Toggle SCL back and forth 9 times under 100KHz. A single read is |
| 190 | * needed after the writes to force the posted write to complete. |
| 191 | */ |
| 192 | for (i = 0; i < 9; i++) { |
| 193 | drive_scl(reset_info, GPIO_OUTPUT_OUT_HIGH); |
| 194 | drive_scl(reset_info, GPIO_OUTPUT_OUT_LOW); |
| 195 | } |
| 196 | |
| 197 | /* Restore I2C pins. */ |
| 198 | for (i = 0; i < reset_info->num_pins; i++) |
| 199 | restore_i2c_pin_registers(reset_info->i2c_scl[i].pin.gpio, &save_table[i]); |
| 200 | } |