Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 2 | |
Elyes HAOUAS | aa8e7e7 | 2016-06-19 12:38:47 +0200 | [diff] [blame] | 3 | /* |
| 4 | * JEDEC Standard No. 21-C |
| 5 | * Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules 2014 |
| 6 | * http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf |
| 7 | */ |
| 8 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 9 | #ifndef DEVICE_DRAM_DDR3L_H |
| 10 | #define DEVICE_DRAM_DDR3L_H |
| 11 | |
| 12 | /** |
| 13 | * @file ddr3.h |
| 14 | * |
| 15 | * \brief Utilities for decoding DDR3 SPDs |
| 16 | */ |
| 17 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 18 | #include <spd.h> |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 19 | #include <device/dram/common.h> |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 20 | #include <types.h> |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 21 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 22 | /** |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 23 | * Convenience definitions for SPD offsets |
| 24 | * |
| 25 | * @{ |
| 26 | */ |
| 27 | #define SPD_DIMM_MOD_ID1 117 |
| 28 | #define SPD_DIMM_MOD_ID2 118 |
| 29 | #define SPD_DIMM_SERIAL_NUM 122 |
| 30 | #define SPD_DIMM_SERIAL_LEN 4 |
| 31 | #define SPD_DIMM_PART_NUM 128 |
| 32 | #define SPD_DIMM_PART_LEN 18 |
| 33 | /** @} */ |
| 34 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 35 | /* |
| 36 | * Module type (byte 3, bits 3:0) of SPD |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 37 | * This definition is specific to DDR3. DDR2 SPDs have a different structure. |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 38 | */ |
Angel Pons | 1857138 | 2021-03-28 13:49:39 +0200 | [diff] [blame] | 39 | enum spd_dimm_type_ddr3 { |
| 40 | SPD_DDR3_DIMM_TYPE_UNDEFINED = 0x00, |
| 41 | SPD_DDR3_DIMM_TYPE_RDIMM = 0x01, |
| 42 | SPD_DDR3_DIMM_TYPE_UDIMM = 0x02, |
| 43 | SPD_DDR3_DIMM_TYPE_SO_DIMM = 0x03, |
| 44 | SPD_DDR3_DIMM_TYPE_MICRO_DIMM = 0x04, |
| 45 | SPD_DDR3_DIMM_TYPE_MINI_RDIMM = 0x05, |
| 46 | SPD_DDR3_DIMM_TYPE_MINI_UDIMM = 0x06, |
| 47 | SPD_DDR3_DIMM_TYPE_MINI_CDIMM = 0x07, |
| 48 | SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM = 0x08, |
| 49 | SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM = 0x09, |
| 50 | SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM = 0x0a, |
| 51 | SPD_DDR3_DIMM_TYPE_LRDIMM = 0x0b, |
| 52 | SPD_DDR3_DIMM_TYPE_16B_SO_DIMM = 0x0c, |
| 53 | SPD_DDR3_DIMM_TYPE_32B_SO_DIMM = 0x0d, |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 54 | /* Masks to bits 3:0 to give the dimm type */ |
Angel Pons | 1857138 | 2021-03-28 13:49:39 +0200 | [diff] [blame] | 55 | SPD_DDR3_DIMM_TYPE_MASK = 0x0f, |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 56 | }; |
| 57 | |
| 58 | /** |
| 59 | * \brief DIMM flags |
| 60 | * |
| 61 | * Characteristic flags for the DIMM, as presented by the SPD |
| 62 | */ |
Angel Pons | afb3d7e | 2021-03-28 13:43:13 +0200 | [diff] [blame] | 63 | union dimm_flags_ddr3_st { |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 64 | /* The whole point of the union/struct construct is to allow us to clear |
| 65 | * all the bits with one line: flags.raw = 0. |
| 66 | * We do not care how these bits are ordered */ |
| 67 | struct { |
| 68 | /* Indicates if rank 1 of DIMM uses a mirrored pin mapping. See: |
| 69 | * Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 70 | unsigned int pins_mirrored:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 71 | /* Module can work at 1.50V - All DIMMS must be 1.5V operable */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 72 | unsigned int operable_1_50V:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 73 | /* Module can work at 1.35V */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 74 | unsigned int operable_1_35V:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 75 | /* Module can work at 1.20V */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 76 | unsigned int operable_1_25V:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 77 | /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 78 | unsigned int is_ecc:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 79 | /* DLL-Off Mode Support */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 80 | unsigned int dll_off_mode:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 81 | /* Indicates a drive strength of RZQ/6 (40 Ohm) is supported */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 82 | unsigned int rzq6_supported:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 83 | /* Indicates a drive strength of RZQ/7 (35 Ohm) is supported */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 84 | unsigned int rzq7_supported:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 85 | /* Partial Array Self Refresh */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 86 | unsigned int pasr:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 87 | /* On-die Thermal Sensor Readout */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 88 | unsigned int odts:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 89 | /* Auto Self Refresh */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 90 | unsigned int asr:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 91 | /* Extended temperature range supported */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 92 | unsigned int ext_temp_range:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 93 | /* Operating at extended temperature requires 2X refresh rate */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 94 | unsigned int ext_temp_refresh:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 95 | /* Thermal sensor incorporated */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 96 | unsigned int therm_sensor:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 97 | }; |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 98 | unsigned int raw; |
Angel Pons | afb3d7e | 2021-03-28 13:43:13 +0200 | [diff] [blame] | 99 | }; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 100 | |
| 101 | /** |
| 102 | * \brief DIMM characteristics |
| 103 | * |
| 104 | * The characteristics of each DIMM, as presented by the SPD |
| 105 | */ |
Angel Pons | afb3d7e | 2021-03-28 13:43:13 +0200 | [diff] [blame] | 106 | struct dimm_attr_ddr3_st { |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 107 | enum spd_memory_type dram_type; |
Angel Pons | 1857138 | 2021-03-28 13:49:39 +0200 | [diff] [blame] | 108 | enum spd_dimm_type_ddr3 dimm_type; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 109 | u16 cas_supported; |
| 110 | /* Flags extracted from SPD */ |
Angel Pons | afb3d7e | 2021-03-28 13:43:13 +0200 | [diff] [blame] | 111 | union dimm_flags_ddr3_st flags; |
Vladimir Serbinenko | 7686a56 | 2014-05-18 11:05:56 +0200 | [diff] [blame] | 112 | /* SDRAM width */ |
| 113 | u8 width; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 114 | /* Number of ranks */ |
| 115 | u8 ranks; |
| 116 | /* Number or row address bits */ |
| 117 | u8 row_bits; |
| 118 | /* Number or column address bits */ |
| 119 | u8 col_bits; |
| 120 | /* Size of module in MiB */ |
| 121 | u32 size_mb; |
| 122 | /* Latencies are in units of 1/256 ns */ |
| 123 | u32 tCK; |
| 124 | u32 tAA; |
| 125 | u32 tWR; |
| 126 | u32 tRCD; |
| 127 | u32 tRRD; |
| 128 | u32 tRP; |
| 129 | u32 tRAS; |
| 130 | u32 tRC; |
| 131 | u32 tRFC; |
| 132 | u32 tWTR; |
| 133 | u32 tRTP; |
| 134 | u32 tFAW; |
Dan Elkouby | 0c02420 | 2018-04-13 18:45:02 +0300 | [diff] [blame] | 135 | u32 tCWL; |
| 136 | u16 tCMD; |
Vladimir Serbinenko | 7686a56 | 2014-05-18 11:05:56 +0200 | [diff] [blame] | 137 | |
| 138 | u8 reference_card; |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 139 | /* XMP: Module voltage in mV */ |
| 140 | u16 voltage; |
| 141 | /* XMP: max DIMMs per channel supported (1-4) */ |
| 142 | u8 dimms_per_channel; |
Patrick Rudolph | 0769159 | 2016-02-29 18:21:00 +0100 | [diff] [blame] | 143 | /* Manufacturer ID */ |
| 144 | u16 manufacturer_id; |
| 145 | /* ASCII part number - NULL terminated */ |
| 146 | u8 part_number[17]; |
Patrick Rudolph | 15e6469 | 2018-08-17 15:24:56 +0200 | [diff] [blame] | 147 | /* Serial number */ |
| 148 | u8 serial[SPD_DIMM_SERIAL_LEN]; |
Angel Pons | afb3d7e | 2021-03-28 13:43:13 +0200 | [diff] [blame] | 149 | }; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 150 | |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 151 | enum ddr3_xmp_profile { |
| 152 | DDR3_XMP_PROFILE_1 = 0, |
| 153 | DDR3_XMP_PROFILE_2 = 1, |
| 154 | }; |
| 155 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 156 | typedef u8 spd_raw_data[256]; |
| 157 | |
Alexandru Gagniuc | 4c37e58 | 2013-12-17 13:08:01 -0500 | [diff] [blame] | 158 | u16 spd_ddr3_calc_crc(u8 *spd, int len); |
Kyösti Mälkki | 7dc4b84 | 2016-11-18 18:41:17 +0200 | [diff] [blame] | 159 | u16 spd_ddr3_calc_unique_crc(u8 *spd, int len); |
Angel Pons | afb3d7e | 2021-03-28 13:43:13 +0200 | [diff] [blame] | 160 | int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data); |
Angel Pons | 1857138 | 2021-03-28 13:49:39 +0200 | [diff] [blame] | 161 | int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type); |
Angel Pons | afb3d7e | 2021-03-28 13:43:13 +0200 | [diff] [blame] | 162 | void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm); |
| 163 | int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, |
Lee Leahy | 708fc27 | 2017-03-07 12:18:53 -0800 | [diff] [blame] | 164 | spd_raw_data spd, |
| 165 | enum ddr3_xmp_profile profile); |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 166 | enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, |
| 167 | const u16 selected_freq, |
Angel Pons | afb3d7e | 2021-03-28 13:43:13 +0200 | [diff] [blame] | 168 | const struct dimm_attr_ddr3_st *info); |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 169 | |
Martin Roth | fd277d8 | 2016-01-11 12:47:30 -0700 | [diff] [blame] | 170 | #endif /* DEVICE_DRAM_DDR3L_H */ |