Patrick Georgi | 02363b5 | 2020-05-05 20:48:50 +0200 | [diff] [blame] | 1 | /* This file is part of the coreboot project. */ |
Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame^] | 2 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 3 | |
Elyes HAOUAS | aa8e7e7 | 2016-06-19 12:38:47 +0200 | [diff] [blame] | 4 | /* |
| 5 | * JEDEC Standard No. 21-C |
| 6 | * Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules 2014 |
| 7 | * http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf |
| 8 | */ |
| 9 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 10 | #ifndef DEVICE_DRAM_DDR3L_H |
| 11 | #define DEVICE_DRAM_DDR3L_H |
| 12 | |
| 13 | /** |
| 14 | * @file ddr3.h |
| 15 | * |
| 16 | * \brief Utilities for decoding DDR3 SPDs |
| 17 | */ |
| 18 | |
| 19 | #include <stdint.h> |
| 20 | #include <spd.h> |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 21 | #include <device/dram/common.h> |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 22 | #include <types.h> |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 23 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 24 | |
| 25 | /** |
Matt DeVillier | 5aaa8ce | 2016-09-02 13:29:17 -0500 | [diff] [blame] | 26 | * Convenience definitions for SPD offsets |
| 27 | * |
| 28 | * @{ |
| 29 | */ |
| 30 | #define SPD_DIMM_MOD_ID1 117 |
| 31 | #define SPD_DIMM_MOD_ID2 118 |
| 32 | #define SPD_DIMM_SERIAL_NUM 122 |
| 33 | #define SPD_DIMM_SERIAL_LEN 4 |
| 34 | #define SPD_DIMM_PART_NUM 128 |
| 35 | #define SPD_DIMM_PART_LEN 18 |
| 36 | /** @} */ |
| 37 | |
| 38 | /** |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 39 | * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP |
| 40 | * |
| 41 | * Use this macro instead of printk(); for verbose RAM initialization messages. |
| 42 | * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically |
| 43 | * disabled. |
| 44 | * @{ |
| 45 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 46 | #if CONFIG(DEBUG_RAM_SETUP) |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 47 | #define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) |
| 48 | #else |
| 49 | #define printram(x, ...) |
| 50 | #endif |
| 51 | /** @} */ |
| 52 | |
| 53 | /* |
| 54 | * Module type (byte 3, bits 3:0) of SPD |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 55 | * This definition is specific to DDR3. DDR2 SPDs have a different structure. |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 56 | */ |
| 57 | enum spd_dimm_type { |
| 58 | SPD_DIMM_TYPE_UNDEFINED = 0x00, |
| 59 | SPD_DIMM_TYPE_RDIMM = 0x01, |
| 60 | SPD_DIMM_TYPE_UDIMM = 0x02, |
| 61 | SPD_DIMM_TYPE_SO_DIMM = 0x03, |
| 62 | SPD_DIMM_TYPE_MICRO_DIMM = 0x04, |
| 63 | SPD_DIMM_TYPE_MINI_RDIMM = 0x05, |
| 64 | SPD_DIMM_TYPE_MINI_UDIMM = 0x06, |
| 65 | SPD_DIMM_TYPE_MINI_CDIMM = 0x07, |
| 66 | SPD_DIMM_TYPE_72B_SO_UDIMM = 0x08, |
| 67 | SPD_DIMM_TYPE_72B_SO_RDIMM = 0x09, |
| 68 | SPD_DIMM_TYPE_72B_SO_CDIMM = 0x0a, |
| 69 | SPD_DIMM_TYPE_LRDIMM = 0x0b, |
Elyes HAOUAS | aa8e7e7 | 2016-06-19 12:38:47 +0200 | [diff] [blame] | 70 | SPD_DIMM_TYPE_16B_SO_DIMM = 0x0c, |
| 71 | SPD_DIMM_TYPE_32B_SO_DIMM = 0x0d, |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 72 | /* Masks to bits 3:0 to give the dimm type */ |
| 73 | SPD_DIMM_TYPE_MASK = 0x0f, |
| 74 | }; |
| 75 | |
| 76 | /** |
| 77 | * \brief DIMM flags |
| 78 | * |
| 79 | * Characteristic flags for the DIMM, as presented by the SPD |
| 80 | */ |
| 81 | typedef union dimm_flags_st { |
| 82 | /* The whole point of the union/struct construct is to allow us to clear |
| 83 | * all the bits with one line: flags.raw = 0. |
| 84 | * We do not care how these bits are ordered */ |
| 85 | struct { |
| 86 | /* Indicates if rank 1 of DIMM uses a mirrored pin mapping. See: |
| 87 | * Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 88 | unsigned int pins_mirrored:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 89 | /* Module can work at 1.50V - All DIMMS must be 1.5V operable */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 90 | unsigned int operable_1_50V:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 91 | /* Module can work at 1.35V */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 92 | unsigned int operable_1_35V:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 93 | /* Module can work at 1.20V */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 94 | unsigned int operable_1_25V:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 95 | /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 96 | unsigned int is_ecc:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 97 | /* DLL-Off Mode Support */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 98 | unsigned int dll_off_mode:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 99 | /* Indicates a drive strength of RZQ/6 (40 Ohm) is supported */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 100 | unsigned int rzq6_supported:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 101 | /* Indicates a drive strength of RZQ/7 (35 Ohm) is supported */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 102 | unsigned int rzq7_supported:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 103 | /* Partial Array Self Refresh */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 104 | unsigned int pasr:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 105 | /* On-die Thermal Sensor Readout */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 106 | unsigned int odts:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 107 | /* Auto Self Refresh */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 108 | unsigned int asr:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 109 | /* Extended temperature range supported */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 110 | unsigned int ext_temp_range:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 111 | /* Operating at extended temperature requires 2X refresh rate */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 112 | unsigned int ext_temp_refresh:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 113 | /* Thermal sensor incorporated */ |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 114 | unsigned int therm_sensor:1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 115 | }; |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 116 | unsigned int raw; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 117 | } dimm_flags_t; |
| 118 | |
| 119 | /** |
| 120 | * \brief DIMM characteristics |
| 121 | * |
| 122 | * The characteristics of each DIMM, as presented by the SPD |
| 123 | */ |
| 124 | typedef struct dimm_attr_st { |
| 125 | enum spd_memory_type dram_type; |
Vladimir Serbinenko | 0e675f7 | 2014-12-07 13:56:48 +0100 | [diff] [blame] | 126 | enum spd_dimm_type dimm_type; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 127 | u16 cas_supported; |
| 128 | /* Flags extracted from SPD */ |
| 129 | dimm_flags_t flags; |
Vladimir Serbinenko | 7686a56 | 2014-05-18 11:05:56 +0200 | [diff] [blame] | 130 | /* SDRAM width */ |
| 131 | u8 width; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 132 | /* Number of ranks */ |
| 133 | u8 ranks; |
| 134 | /* Number or row address bits */ |
| 135 | u8 row_bits; |
| 136 | /* Number or column address bits */ |
| 137 | u8 col_bits; |
| 138 | /* Size of module in MiB */ |
| 139 | u32 size_mb; |
| 140 | /* Latencies are in units of 1/256 ns */ |
| 141 | u32 tCK; |
| 142 | u32 tAA; |
| 143 | u32 tWR; |
| 144 | u32 tRCD; |
| 145 | u32 tRRD; |
| 146 | u32 tRP; |
| 147 | u32 tRAS; |
| 148 | u32 tRC; |
| 149 | u32 tRFC; |
| 150 | u32 tWTR; |
| 151 | u32 tRTP; |
| 152 | u32 tFAW; |
Dan Elkouby | 0c02420 | 2018-04-13 18:45:02 +0300 | [diff] [blame] | 153 | u32 tCWL; |
| 154 | u16 tCMD; |
Vladimir Serbinenko | 7686a56 | 2014-05-18 11:05:56 +0200 | [diff] [blame] | 155 | |
| 156 | u8 reference_card; |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 157 | /* XMP: Module voltage in mV */ |
| 158 | u16 voltage; |
| 159 | /* XMP: max DIMMs per channel supported (1-4) */ |
| 160 | u8 dimms_per_channel; |
Patrick Rudolph | 0769159 | 2016-02-29 18:21:00 +0100 | [diff] [blame] | 161 | /* Manufacturer ID */ |
| 162 | u16 manufacturer_id; |
| 163 | /* ASCII part number - NULL terminated */ |
| 164 | u8 part_number[17]; |
Patrick Rudolph | 15e6469 | 2018-08-17 15:24:56 +0200 | [diff] [blame] | 165 | /* Serial number */ |
| 166 | u8 serial[SPD_DIMM_SERIAL_LEN]; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 167 | } dimm_attr; |
| 168 | |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 169 | enum ddr3_xmp_profile { |
| 170 | DDR3_XMP_PROFILE_1 = 0, |
| 171 | DDR3_XMP_PROFILE_2 = 1, |
| 172 | }; |
| 173 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 174 | typedef u8 spd_raw_data[256]; |
| 175 | |
Alexandru Gagniuc | 4c37e58 | 2013-12-17 13:08:01 -0500 | [diff] [blame] | 176 | u16 spd_ddr3_calc_crc(u8 *spd, int len); |
Kyösti Mälkki | 7dc4b84 | 2016-11-18 18:41:17 +0200 | [diff] [blame] | 177 | u16 spd_ddr3_calc_unique_crc(u8 *spd, int len); |
Lee Leahy | 6d71a43 | 2017-03-07 15:24:16 -0800 | [diff] [blame] | 178 | int spd_decode_ddr3(dimm_attr *dimm, spd_raw_data spd_data); |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 179 | int spd_dimm_is_registered_ddr3(enum spd_dimm_type type); |
Lee Leahy | 6d71a43 | 2017-03-07 15:24:16 -0800 | [diff] [blame] | 180 | void dram_print_spd_ddr3(const dimm_attr *dimm); |
| 181 | int spd_xmp_decode_ddr3(dimm_attr *dimm, |
Lee Leahy | 708fc27 | 2017-03-07 12:18:53 -0800 | [diff] [blame] | 182 | spd_raw_data spd, |
| 183 | enum ddr3_xmp_profile profile); |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 184 | enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, |
| 185 | const u16 selected_freq, |
| 186 | const dimm_attr *info); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 187 | /** |
| 188 | * \brief Read double word from specified address |
| 189 | * |
| 190 | * Should be useful when doing an MRS to the DIMM |
| 191 | */ |
Stefan Reinauer | 1e2500e | 2015-06-19 14:59:06 -0700 | [diff] [blame] | 192 | static inline u32 volatile_read(volatile uintptr_t addr) |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 193 | { |
| 194 | volatile u32 result; |
| 195 | result = *(volatile u32 *)addr; |
| 196 | return result; |
| 197 | } |
| 198 | |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 199 | /** |
| 200 | * \brief Representation of an MRS command |
| 201 | * |
| 202 | * This represents an MRS command as seen by the DIMM. This is not a memory |
| 203 | * address that can be read to generate an MRS command. The mapping of CPU |
| 204 | * to memory pins is hardware-dependent. |
| 205 | * \n |
| 206 | * The idea is to generalize the MRS code, and only need a hardware-specific |
| 207 | * function to map the MRS bits to CPU address bits. An MRS command can be |
| 208 | * sent like: |
| 209 | * @code{.c} |
| 210 | * u32 addr; |
| 211 | * mrs_cmd_t mrs; |
| 212 | * chipset_enable_mrs_command_mode(); |
| 213 | * mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl) |
| 214 | * if (rank_has_mirrorred_pins) |
| 215 | * mrs = ddr3_mrs_mirror_pins(mrs); |
| 216 | * addr = chipset_specific_get_mrs_addr(mrs); |
| 217 | * volatile_read(addr); |
| 218 | * @endcode |
| 219 | * |
| 220 | * The MRS representation has the following structure: |
| 221 | * - cmd[15:0] = Address pins MA[15:0] |
| 222 | * - cmd[18:16] = Bank address BA[2:0] |
| 223 | */ |
| 224 | typedef u32 mrs_cmd_t; |
| 225 | |
| 226 | enum ddr3_mr0_precharge { |
| 227 | DDR3_MR0_PRECHARGE_SLOW = 0, |
| 228 | DDR3_MR0_PRECHARGE_FAST = 1, |
| 229 | }; |
| 230 | enum ddr3_mr0_mode { |
| 231 | DDR3_MR0_MODE_NORMAL = 0, |
| 232 | DDR3_MR0_MODE_TEST = 1, |
| 233 | }; |
| 234 | enum ddr3_mr0_dll_reset { |
| 235 | DDR3_MR0_DLL_RESET_NO = 0, |
| 236 | DDR3_MR0_DLL_RESET_YES = 1, |
| 237 | }; |
| 238 | enum ddr3_mr0_burst_type { |
| 239 | DDR3_MR0_BURST_TYPE_SEQUENTIAL = 0, |
| 240 | DDR3_MR0_BURST_TYPE_INTERLEAVED = 1, |
| 241 | }; |
| 242 | enum ddr3_mr0_burst_length { |
| 243 | DDR3_MR0_BURST_LENGTH_8 = 0, |
| 244 | DDR3_MR0_BURST_LENGTH_CHOP = 1, |
| 245 | DDR3_MR0_BURST_LENGTH_4 = 2, |
| 246 | }; |
| 247 | mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, |
| 248 | u8 write_recovery, |
| 249 | enum ddr3_mr0_dll_reset dll_reset, |
| 250 | enum ddr3_mr0_mode mode, |
| 251 | u8 cas, |
| 252 | enum ddr3_mr0_burst_type interleaved_burst, |
| 253 | enum ddr3_mr0_burst_length burst_length); |
| 254 | |
| 255 | enum ddr3_mr1_qoff { |
| 256 | DDR3_MR1_QOFF_ENABLE = 0, |
| 257 | DDR3_MR1_QOFF_DISABLE = 1, |
| 258 | }; |
| 259 | enum ddr3_mr1_tqds { |
| 260 | DDR3_MR1_TQDS_DISABLE = 0, |
| 261 | DDR3_MR1_TQDS_ENABLE = 1, |
| 262 | }; |
| 263 | enum ddr3_mr1_write_leveling { |
| 264 | DDR3_MR1_WRLVL_DISABLE = 0, |
| 265 | DDR3_MR1_WRLVL_ENABLE = 1, |
| 266 | }; |
| 267 | enum ddr3_mr1_rtt_nom { |
| 268 | DDR3_MR1_RTT_NOM_OFF = 0, |
| 269 | DDR3_MR1_RTT_NOM_RZQ4 = 1, |
| 270 | DDR3_MR1_RTT_NOM_RZQ2 = 2, |
| 271 | DDR3_MR1_RTT_NOM_RZQ6 = 3, |
| 272 | DDR3_MR1_RTT_NOM_RZQ12 = 4, |
| 273 | DDR3_MR1_RTT_NOM_RZQ8 = 5, |
| 274 | }; |
| 275 | enum ddr3_mr1_additive_latency { |
| 276 | DDR3_MR1_AL_DISABLE = 0, |
| 277 | DDR3_MR1_AL_CL_MINUS_1 = 1, |
| 278 | DDR3_MR1_AL_CL_MINUS_2 = 2, |
| 279 | }; |
| 280 | enum ddr3_mr1_ods { |
| 281 | DDR3_MR1_ODS_RZQ6 = 0, |
| 282 | DDR3_MR1_ODS_RZQ7 = 1, |
| 283 | }; |
| 284 | enum ddr3_mr1_dll { |
| 285 | DDR3_MR1_DLL_ENABLE = 0, |
| 286 | DDR3_MR1_DLL_DISABLE = 1, |
| 287 | }; |
| 288 | |
| 289 | mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, |
| 290 | enum ddr3_mr1_tqds tqds, |
| 291 | enum ddr3_mr1_rtt_nom rtt_nom, |
| 292 | enum ddr3_mr1_write_leveling write_leveling, |
| 293 | enum ddr3_mr1_ods output_drive_strenght, |
| 294 | enum ddr3_mr1_additive_latency additive_latency, |
| 295 | enum ddr3_mr1_dll dll_disable); |
| 296 | |
| 297 | enum ddr3_mr2_rttwr { |
| 298 | DDR3_MR2_RTTWR_OFF = 0, |
| 299 | DDR3_MR2_RTTWR_RZQ4 = 1, |
| 300 | DDR3_MR2_RTTWR_RZQ2 = 2, |
| 301 | }; |
| 302 | enum ddr3_mr2_srt_range { |
| 303 | DDR3_MR2_SRT_NORMAL = 0, |
| 304 | DDR3_MR2_SRT_EXTENDED = 1, |
| 305 | }; |
| 306 | enum ddr3_mr2_asr { |
| 307 | DDR3_MR2_ASR_MANUAL = 0, |
| 308 | DDR3_MR2_ASR_AUTO = 1, |
| 309 | }; |
| 310 | |
| 311 | mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, |
| 312 | enum ddr3_mr2_srt_range extended_temp, |
| 313 | enum ddr3_mr2_asr self_refresh, u8 cas_cwl); |
| 314 | |
| 315 | mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr); |
| 316 | mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd); |
| 317 | |
Martin Roth | fd277d8 | 2016-01-11 12:47:30 -0700 | [diff] [blame] | 318 | #endif /* DEVICE_DRAM_DDR3L_H */ |