Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | a608969 | 2016-01-05 16:34:58 -0800 | [diff] [blame] | 5 | * Copyright (C) 2015-2016 Intel Corporation. |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stddef.h> |
Aaron Durbin | 932e09d | 2016-07-13 23:09:52 -0500 | [diff] [blame] | 18 | #include <arch/acpi.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 19 | #include <arch/io.h> |
| 20 | #include <arch/cbfs.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 21 | #include <arch/early_variables.h> |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 22 | #include <assert.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 23 | #include <console/console.h> |
| 24 | #include <cbmem.h> |
robbie zhang | 13a2e94 | 2016-02-10 11:40:11 -0800 | [diff] [blame] | 25 | #include <cpu/intel/microcode.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 26 | #include <cpu/x86/mtrr.h> |
| 27 | #include <ec/google/chromeec/ec.h> |
| 28 | #include <ec/google/chromeec/ec_commands.h> |
| 29 | #include <elog.h> |
Lee Leahy | b092c9e | 2016-01-01 18:09:50 -0800 | [diff] [blame] | 30 | #include <fsp/romstage.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 31 | #include <mrc_cache.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 32 | #include <reset.h> |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 33 | #include <program_loading.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 34 | #include <romstage_handoff.h> |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 35 | #include <smbios.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 36 | #include <stage_cache.h> |
Aaron Durbin | afe8aee | 2016-11-29 21:37:42 -0600 | [diff] [blame] | 37 | #include <string.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 38 | #include <timestamp.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 39 | #include <vendorcode/google/chromeos/chromeos.h> |
| 40 | |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 41 | asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 42 | { |
| 43 | void *top_of_stack; |
| 44 | struct pei_data pei_data; |
| 45 | struct romstage_params params = { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 46 | .pei_data = &pei_data, |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 47 | .chipset_context = fih, |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 48 | }; |
| 49 | |
| 50 | post_code(0x30); |
| 51 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 52 | timestamp_add_now(TS_START_ROMSTAGE); |
| 53 | |
Elyes HAOUAS | 7753731 | 2016-07-30 15:37:26 +0200 | [diff] [blame] | 54 | /* Load microcode before RAM init */ |
robbie zhang | 13a2e94 | 2016-02-10 11:40:11 -0800 | [diff] [blame] | 55 | if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS)) |
| 56 | intel_update_microcode_from_cbfs(); |
| 57 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 58 | memset(&pei_data, 0, sizeof(pei_data)); |
| 59 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 60 | /* Display parameters */ |
Lee Leahy | c253a92 | 2017-03-13 17:36:39 -0700 | [diff] [blame] | 61 | if (!IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT)) |
| 62 | printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", |
| 63 | CONFIG_MMCONF_BASE_ADDRESS); |
Aaron Durbin | 929b602 | 2015-12-09 16:00:18 -0600 | [diff] [blame] | 64 | printk(BIOS_INFO, "Using FSP 1.1\n"); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 65 | |
| 66 | /* Display FSP banner */ |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 67 | print_fsp_info(fih); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 68 | |
Aaron Durbin | 929b602 | 2015-12-09 16:00:18 -0600 | [diff] [blame] | 69 | /* Stash FSP version. */ |
| 70 | params.fsp_version = fsp_version(fih); |
| 71 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 72 | /* Get power state */ |
| 73 | params.power_state = fill_power_state(); |
| 74 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 75 | /* Call into mainboard. */ |
| 76 | mainboard_romstage_entry(¶ms); |
| 77 | soc_after_ram_init(¶ms); |
| 78 | post_code(0x38); |
| 79 | |
| 80 | top_of_stack = setup_stack_and_mtrrs(); |
| 81 | |
Lee Leahy | 3e5bc1f | 2015-06-24 11:17:54 -0700 | [diff] [blame] | 82 | printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); |
| 83 | timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 84 | return top_of_stack; |
| 85 | } |
| 86 | |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 87 | void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) |
| 88 | { |
| 89 | return romstage_main(fih); |
| 90 | } |
| 91 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 92 | /* Entry from the mainboard. */ |
| 93 | void romstage_common(struct romstage_params *params) |
| 94 | { |
Subrata Banik | 0beac81 | 2017-07-12 15:13:53 +0530 | [diff] [blame] | 95 | bool s3wake; |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 96 | struct region_device rdev; |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 97 | struct pei_data *pei_data; |
| 98 | |
| 99 | post_code(0x32); |
| 100 | |
| 101 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 102 | |
| 103 | pei_data = params->pei_data; |
| 104 | pei_data->boot_mode = params->power_state->prev_sleep_state; |
Subrata Banik | 0beac81 | 2017-07-12 15:13:53 +0530 | [diff] [blame] | 105 | s3wake = params->power_state->prev_sleep_state == ACPI_S3; |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 106 | |
Subrata Banik | 0beac81 | 2017-07-12 15:13:53 +0530 | [diff] [blame] | 107 | if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 108 | boot_count_increment(); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 109 | |
| 110 | /* Perform remaining SOC initialization */ |
| 111 | soc_pre_ram_init(params); |
| 112 | post_code(0x33); |
| 113 | |
| 114 | /* Check recovery and MRC cache */ |
| 115 | params->pei_data->saved_data_size = 0; |
| 116 | params->pei_data->saved_data = NULL; |
| 117 | if (!params->pei_data->disable_saved_data) { |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 118 | if (vboot_recovery_mode_enabled()) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 119 | /* Recovery mode does not use MRC cache */ |
| 120 | printk(BIOS_DEBUG, |
| 121 | "Recovery mode: not using MRC cache.\n"); |
Lee Leahy | a608969 | 2016-01-05 16:34:58 -0800 | [diff] [blame] | 122 | } else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 123 | && (!mrc_cache_get_current(MRC_TRAINING_DATA, |
| 124 | params->fsp_version, |
| 125 | &rdev))) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 126 | /* MRC cache found */ |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 127 | params->pei_data->saved_data_size = |
| 128 | region_device_sz(&rdev); |
| 129 | params->pei_data->saved_data = rdev_mmap_full(&rdev); |
Elyes HAOUAS | 1895838 | 2018-08-07 12:23:16 +0200 | [diff] [blame] | 130 | /* Assume boot device is memory mapped. */ |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 131 | assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); |
Aaron Durbin | 932e09d | 2016-07-13 23:09:52 -0500 | [diff] [blame] | 132 | } else if (params->pei_data->boot_mode == ACPI_S3) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 133 | /* Waking from S3 and no cache. */ |
| 134 | printk(BIOS_DEBUG, |
| 135 | "No MRC cache found in S3 resume path.\n"); |
| 136 | post_code(POST_RESUME_FAILURE); |
| 137 | hard_reset(); |
| 138 | } else { |
| 139 | printk(BIOS_DEBUG, "No MRC cache found.\n"); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 140 | } |
| 141 | } |
| 142 | |
| 143 | /* Initialize RAM */ |
| 144 | raminit(params); |
| 145 | timestamp_add_now(TS_AFTER_INITRAM); |
| 146 | |
| 147 | /* Save MRC output */ |
Lee Leahy | a608969 | 2016-01-05 16:34:58 -0800 | [diff] [blame] | 148 | if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { |
| 149 | printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", |
| 150 | pei_data->data_to_save, pei_data->data_to_save_size); |
Aaron Durbin | 932e09d | 2016-07-13 23:09:52 -0500 | [diff] [blame] | 151 | if ((params->pei_data->boot_mode != ACPI_S3) |
Lee Leahy | a608969 | 2016-01-05 16:34:58 -0800 | [diff] [blame] | 152 | && (params->pei_data->data_to_save_size != 0) |
| 153 | && (params->pei_data->data_to_save != NULL)) |
Lee Leahy | 216712a | 2017-03-17 11:23:32 -0700 | [diff] [blame] | 154 | mrc_cache_stash_data(MRC_TRAINING_DATA, |
| 155 | params->fsp_version, |
| 156 | params->pei_data->data_to_save, |
| 157 | params->pei_data->data_to_save_size); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | /* Save DIMM information */ |
Subrata Banik | 0beac81 | 2017-07-12 15:13:53 +0530 | [diff] [blame] | 161 | if (!s3wake) |
| 162 | mainboard_save_dimm_info(params); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 163 | |
| 164 | /* Create romstage handof information */ |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 165 | if (romstage_handoff_init( |
| 166 | params->power_state->prev_sleep_state == ACPI_S3) < 0) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 167 | hard_reset(); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 168 | } |
| 169 | |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 170 | void after_cache_as_ram_stage(void) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 171 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 172 | /* Load the ramstage. */ |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 173 | run_ramstage(); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 174 | die("ERROR - Failed to load ramstage!"); |
| 175 | } |
| 176 | |
| 177 | /* Initialize the power state */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 178 | __weak struct chipset_power_state *fill_power_state(void) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 179 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 180 | return NULL; |
| 181 | } |
| 182 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 183 | /* Board initialization before and after RAM is enabled */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 184 | __weak void mainboard_romstage_entry( |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 185 | struct romstage_params *params) |
| 186 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 187 | post_code(0x31); |
| 188 | |
| 189 | /* Initliaze memory */ |
| 190 | romstage_common(params); |
| 191 | } |
| 192 | |
| 193 | /* Save the DIMM information for SMBIOS table 17 */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 194 | __weak void mainboard_save_dimm_info( |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 195 | struct romstage_params *params) |
| 196 | { |
| 197 | int channel; |
| 198 | CHANNEL_INFO *channel_info; |
| 199 | int dimm; |
| 200 | DIMM_INFO *dimm_info; |
| 201 | int dimm_max; |
| 202 | void *hob_list_ptr; |
| 203 | EFI_HOB_GUID_TYPE *hob_ptr; |
| 204 | int index; |
| 205 | struct memory_info *mem_info; |
| 206 | FSP_SMBIOS_MEMORY_INFO *memory_info_hob; |
| 207 | const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID; |
| 208 | |
| 209 | /* Locate the memory info HOB, presence validated by raminit */ |
| 210 | hob_list_ptr = fsp_get_hob_list(); |
| 211 | hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr); |
| 212 | memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1); |
| 213 | |
| 214 | /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ |
| 215 | if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) { |
| 216 | printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n"); |
| 217 | printk(BIOS_DEBUG, " 0x%02x: Revision\n", |
| 218 | memory_info_hob->Revision); |
| 219 | printk(BIOS_DEBUG, " 0x%02x: MemoryType\n", |
| 220 | memory_info_hob->MemoryType); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 221 | printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n", |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 222 | memory_info_hob->MemoryFrequencyInMHz); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 223 | printk(BIOS_DEBUG, " %d: DataWidth in bits\n", |
| 224 | memory_info_hob->DataWidth); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 225 | printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n", |
| 226 | memory_info_hob->ErrorCorrectionType); |
| 227 | printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n", |
| 228 | memory_info_hob->ChannelCount); |
| 229 | for (channel = 0; channel < memory_info_hob->ChannelCount; |
| 230 | channel++) { |
| 231 | channel_info = &memory_info_hob->ChannelInfo[channel]; |
| 232 | printk(BIOS_DEBUG, " Channel %d\n", channel); |
| 233 | printk(BIOS_DEBUG, " 0x%02x: ChannelId\n", |
| 234 | channel_info->ChannelId); |
| 235 | printk(BIOS_DEBUG, " 0x%02x: DimmCount\n", |
| 236 | channel_info->DimmCount); |
| 237 | for (dimm = 0; dimm < channel_info->DimmCount; |
| 238 | dimm++) { |
| 239 | dimm_info = &channel_info->DimmInfo[dimm]; |
| 240 | printk(BIOS_DEBUG, " DIMM %d\n", dimm); |
| 241 | printk(BIOS_DEBUG, " 0x%02x: DimmId\n", |
| 242 | dimm_info->DimmId); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 243 | printk(BIOS_DEBUG, " %d: SizeInMb\n", |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 244 | dimm_info->SizeInMb); |
| 245 | } |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | /* |
| 250 | * Allocate CBMEM area for DIMM information used to populate SMBIOS |
| 251 | * table 17 |
| 252 | */ |
| 253 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); |
| 254 | printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); |
| 255 | if (mem_info == NULL) |
| 256 | return; |
| 257 | memset(mem_info, 0, sizeof(*mem_info)); |
| 258 | |
| 259 | /* Describe the first N DIMMs in the system */ |
| 260 | index = 0; |
| 261 | dimm_max = ARRAY_SIZE(mem_info->dimm); |
| 262 | for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) { |
| 263 | if (index >= dimm_max) |
| 264 | break; |
| 265 | channel_info = &memory_info_hob->ChannelInfo[channel]; |
| 266 | for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { |
| 267 | if (index >= dimm_max) |
| 268 | break; |
| 269 | dimm_info = &channel_info->DimmInfo[dimm]; |
| 270 | |
| 271 | /* Populate the DIMM information */ |
| 272 | if (dimm_info->SizeInMb) { |
| 273 | mem_info->dimm[index].dimm_size = |
| 274 | dimm_info->SizeInMb; |
| 275 | mem_info->dimm[index].ddr_type = |
| 276 | memory_info_hob->MemoryType; |
| 277 | mem_info->dimm[index].ddr_frequency = |
| 278 | memory_info_hob->MemoryFrequencyInMHz; |
| 279 | mem_info->dimm[index].channel_num = |
| 280 | channel_info->ChannelId; |
| 281 | mem_info->dimm[index].dimm_num = |
| 282 | dimm_info->DimmId; |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 283 | switch (memory_info_hob->DataWidth) { |
| 284 | default: |
| 285 | case 8: |
| 286 | mem_info->dimm[index].bus_width = |
| 287 | MEMORY_BUS_WIDTH_8; |
| 288 | break; |
| 289 | |
| 290 | case 16: |
| 291 | mem_info->dimm[index].bus_width = |
| 292 | MEMORY_BUS_WIDTH_16; |
| 293 | break; |
| 294 | |
| 295 | case 32: |
| 296 | mem_info->dimm[index].bus_width = |
| 297 | MEMORY_BUS_WIDTH_32; |
| 298 | break; |
| 299 | |
| 300 | case 64: |
| 301 | mem_info->dimm[index].bus_width = |
| 302 | MEMORY_BUS_WIDTH_64; |
| 303 | break; |
| 304 | |
| 305 | case 128: |
| 306 | mem_info->dimm[index].bus_width = |
| 307 | MEMORY_BUS_WIDTH_128; |
| 308 | break; |
| 309 | } |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 310 | |
| 311 | /* Add any mainboard specific information */ |
| 312 | mainboard_add_dimm_info(params, mem_info, |
| 313 | channel, dimm, index); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 314 | index++; |
| 315 | } |
| 316 | } |
| 317 | } |
| 318 | mem_info->dimm_cnt = index; |
| 319 | printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); |
| 320 | } |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 321 | |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 322 | /* Add any mainboard specific information */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 323 | __weak void mainboard_add_dimm_info( |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 324 | struct romstage_params *params, |
| 325 | struct memory_info *mem_info, |
| 326 | int channel, int dimm, int index) |
| 327 | { |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 328 | } |
| 329 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 330 | /* Get the memory configuration data */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 331 | __weak int mrc_cache_get_current(int type, uint32_t version, |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 332 | struct region_device *rdev) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 333 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 334 | return -1; |
| 335 | } |
| 336 | |
| 337 | /* Save the memory configuration data */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 338 | __weak int mrc_cache_stash_data(int type, uint32_t version, |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 339 | const void *data, size_t size) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 340 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 341 | return -1; |
| 342 | } |
| 343 | |
| 344 | /* Transition RAM from off or self-refresh to active */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 345 | __weak void raminit(struct romstage_params *params) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 346 | { |
Furquan Shaikh | 585210a | 2018-10-16 11:54:37 -0700 | [diff] [blame] | 347 | post_code(POST_MEM_PREINIT_PREP_START); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 348 | die("ERROR - No RAM initialization specified!\n"); |
| 349 | } |
| 350 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 351 | /* Display the memory configuration */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 352 | __weak void report_memory_config(void) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 353 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 354 | } |
| 355 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 356 | /* Choose top of stack and setup MTRRs */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 357 | __weak void *setup_stack_and_mtrrs(void) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 358 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 359 | die("ERROR - Must specify top of stack!\n"); |
| 360 | return NULL; |
| 361 | } |
| 362 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 363 | /* SOC initialization after RAM is enabled */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 364 | __weak void soc_after_ram_init(struct romstage_params *params) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 365 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 366 | } |
| 367 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 368 | /* SOC initialization before RAM is enabled */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 369 | __weak void soc_pre_ram_init(struct romstage_params *params) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 370 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 371 | } |