Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | config SOC_INTEL_BAYTRAIL |
| 2 | bool |
| 3 | help |
| 4 | Bay Trail M/D part support. |
| 5 | |
| 6 | if SOC_INTEL_BAYTRAIL |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 10 | select ARCH_BOOTBLOCK_X86_32 |
Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 11 | select ARCH_VERSTAGE_X86_32 |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 12 | select ARCH_ROMSTAGE_X86_32 |
| 13 | select ARCH_RAMSTAGE_X86_32 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 14 | select CACHE_MRC_SETTINGS |
Aaron Durbin | 59d1d87 | 2014-01-14 17:34:10 -0600 | [diff] [blame] | 15 | select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED |
Kyösti Mälkki | 4851bf2 | 2014-12-27 12:57:06 +0200 | [diff] [blame] | 16 | select SUPPORT_CPU_UCODE_IN_CBFS |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 17 | select HAVE_SMI_HANDLER |
Aaron Durbin | 6ecdb68 | 2013-10-10 20:54:57 -0500 | [diff] [blame] | 18 | select HAVE_HARD_RESET |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 19 | select MMCONF_SUPPORT |
| 20 | select MMCONF_SUPPORT_DEFAULT |
Aaron Durbin | f5ff854 | 2016-05-05 10:38:03 -0500 | [diff] [blame^] | 21 | select NO_FIXED_XIP_ROM_SIZE |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 22 | select RELOCATABLE_MODULES |
Kyösti Mälkki | d05d0db | 2014-10-16 14:54:03 +0300 | [diff] [blame] | 23 | select RELOCATABLE_RAMSTAGE |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 24 | select PARALLEL_MP |
Duncan Laurie | c6313db | 2014-01-16 11:18:36 -0800 | [diff] [blame] | 25 | select PCIEXP_ASPM |
| 26 | select PCIEXP_COMMON_CLOCK |
Isaac Christensen | d2044cc | 2014-10-01 13:37:36 -0600 | [diff] [blame] | 27 | select REG_SCRIPT |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 28 | select SMM_TSEG |
| 29 | select SMP |
| 30 | select SPI_FLASH |
| 31 | select SSE2 |
| 32 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 33 | select TSC_CONSTANT_RATE |
Aaron Durbin | ce7ecf9 | 2013-10-24 08:42:10 -0500 | [diff] [blame] | 34 | select TSC_MONOTONIC_TIMER |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 35 | select TSC_SYNC_MFENCE |
| 36 | select UDELAY_TSC |
Stefan Reinauer | 9616f3c | 2015-04-29 10:45:22 -0700 | [diff] [blame] | 37 | select SOC_INTEL_COMMON |
Martin Roth | c407cb9 | 2015-06-23 19:59:30 -0600 | [diff] [blame] | 38 | select HAVE_INTEL_FIRMWARE |
Martin Roth | 3a54318 | 2015-09-28 15:27:24 -0600 | [diff] [blame] | 39 | select HAVE_SPI_CONSOLE_SUPPORT |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 40 | |
| 41 | config BOOTBLOCK_CPU_INIT |
| 42 | string |
| 43 | default "soc/intel/baytrail/bootblock/bootblock.c" |
| 44 | |
| 45 | config MMCONF_BASE_ADDRESS |
| 46 | hex |
| 47 | default 0xe0000000 |
| 48 | |
| 49 | config MAX_CPUS |
| 50 | int |
| 51 | default 4 |
| 52 | |
| 53 | config CPU_ADDR_BITS |
| 54 | int |
| 55 | default 36 |
| 56 | |
| 57 | config SMM_TSEG_SIZE |
| 58 | hex |
| 59 | default 0x800000 |
| 60 | |
| 61 | config SMM_RESERVED_SIZE |
| 62 | hex |
| 63 | default 0x100000 |
| 64 | |
| 65 | config HAVE_MRC |
| 66 | bool "Add a Memory Reference Code binary" |
| 67 | default y |
| 68 | help |
| 69 | Select this option to add a blob containing |
| 70 | memory reference code. |
| 71 | Note: Without this binary coreboot will not work |
| 72 | |
| 73 | if HAVE_MRC |
| 74 | |
| 75 | config MRC_FILE |
| 76 | string "Intel memory refeference code path and filename" |
Patrick Georgi | 26e24cc | 2015-05-05 22:27:25 +0200 | [diff] [blame] | 77 | default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin" |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 78 | help |
| 79 | The path and filename of the file to use as System Agent |
| 80 | binary. Note that this points to the sandybridge binary file |
| 81 | which is will not work, but it serves its purpose to do builds. |
| 82 | |
| 83 | config MRC_BIN_ADDRESS |
| 84 | hex |
| 85 | default 0xfffa0000 |
| 86 | |
Shawn Nematbakhsh | 13d9341 | 2013-11-26 15:37:43 -0800 | [diff] [blame] | 87 | config MRC_RMT |
| 88 | bool "Enable MRC RMT training + debug prints" |
| 89 | default n |
| 90 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 91 | endif # HAVE_MRC |
| 92 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 93 | # Cache As RAM region layout: |
| 94 | # |
| 95 | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE |
| 96 | # | MRC usage | |
| 97 | # | | |
| 98 | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE |
| 99 | # | Stack |\ |
| 100 | # | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| 101 | # | v |/ |
| 102 | # +-------------+ |
| 103 | # | ^ | |
| 104 | # | | | |
| 105 | # | CAR Globals | |
| 106 | # +-------------+ DCACHE_RAM_BASE |
| 107 | # |
| 108 | # Note that the MRC binary is linked to assume the region marked as "MRC usage" |
| 109 | # starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then |
| 110 | # a new MRC binary needs to be produced with the updated start and size |
| 111 | # information. |
| 112 | |
| 113 | config DCACHE_RAM_BASE |
| 114 | hex |
Aaron Durbin | 89f5292 | 2014-03-19 11:48:33 -0500 | [diff] [blame] | 115 | default 0xfe000000 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 116 | |
| 117 | config DCACHE_RAM_SIZE |
| 118 | hex |
Aaron Durbin | 08a4613 | 2013-10-07 16:24:44 -0500 | [diff] [blame] | 119 | default 0x8000 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 120 | help |
| 121 | The size of the cache-as-ram region required during bootblock |
| 122 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 123 | must add up to a power of 2. |
| 124 | |
| 125 | config DCACHE_RAM_MRC_VAR_SIZE |
| 126 | hex |
Aaron Durbin | 08a4613 | 2013-10-07 16:24:44 -0500 | [diff] [blame] | 127 | default 0x8000 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 128 | help |
| 129 | The amount of cache-as-ram region required by the reference code. |
| 130 | |
| 131 | config DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| 132 | hex |
| 133 | default 0x800 |
| 134 | help |
| 135 | The amount of anticipated stack usage from the data cache |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 136 | during pre-RAM ROM stage execution. |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 137 | |
| 138 | config RESET_ON_INVALID_RAMSTAGE_CACHE |
| 139 | bool "Reset the system on S3 wake when ramstage cache invalid." |
| 140 | default n |
| 141 | depends on RELOCATABLE_RAMSTAGE |
| 142 | help |
| 143 | The baytrail romstage code caches the loaded ramstage program |
| 144 | in SMM space. On S3 wake the romstage will copy over a fresh |
| 145 | ramstage that was cached in the SMM space. This option determines |
| 146 | the action to take when the ramstage cache is invalid. If selected |
| 147 | the system will reset otherwise the ramstage will be reloaded from |
| 148 | cbfs. |
| 149 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 150 | config ENABLE_BUILTIN_COM1 |
| 151 | bool "Enable builtin COM1 Serial Port" |
| 152 | default n |
| 153 | help |
| 154 | The PMC has a legacy COM1 serial port. Choose this option to |
| 155 | configure the pads and enable it. This serial port can be used for |
| 156 | the debug console. |
| 157 | |
Vladimir Serbinenko | f1d6e7e | 2014-08-09 07:16:10 +0200 | [diff] [blame] | 158 | config HAVE_REFCODE_BLOB |
| 159 | depends on ARCH_X86 |
| 160 | bool "An external reference code blob should be put into cbfs." |
| 161 | default n |
| 162 | help |
| 163 | The reference code blob will be placed into cbfs. |
| 164 | |
| 165 | if HAVE_REFCODE_BLOB |
| 166 | |
| 167 | config REFCODE_BLOB_FILE |
| 168 | string "Path and filename to reference code blob." |
| 169 | default "refcode.elf" |
| 170 | help |
| 171 | The path and filename to the file to be added to cbfs. |
| 172 | |
| 173 | endif # HAVE_REFCODE_BLOB |
| 174 | |
Aaron Durbin | 3953e39 | 2015-09-03 00:41:29 -0500 | [diff] [blame] | 175 | config CHIPSET_BOOTBLOCK_INCLUDE |
| 176 | string |
| 177 | default "soc/intel/baytrail/bootblock/timestamp.inc" |
| 178 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 179 | endif |