Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | |
| 2 | config SOC_INTEL_BAYTRAIL |
| 3 | bool |
| 4 | help |
| 5 | Bay Trail M/D part support. |
| 6 | |
| 7 | if SOC_INTEL_BAYTRAIL |
| 8 | |
| 9 | config CPU_SPECIFIC_OPTIONS |
| 10 | def_bool y |
Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame^] | 11 | select ARCH_BOOTBLOCK_X86_32 |
| 12 | select ARCH_ROMSTAGE_X86_32 |
| 13 | select ARCH_RAMSTAGE_X86_32 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 14 | select CACHE_MRC_SETTINGS |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 15 | select CAR_MIGRATION |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 16 | select COLLECT_TIMESTAMPS |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 17 | select CPU_MICROCODE_IN_CBFS |
| 18 | select DYNAMIC_CBMEM |
Aaron Durbin | ce7ecf9 | 2013-10-24 08:42:10 -0500 | [diff] [blame] | 19 | select HAVE_MONOTONIC_TIMER |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 20 | select HAVE_SMI_HANDLER |
Aaron Durbin | 6ecdb68 | 2013-10-10 20:54:57 -0500 | [diff] [blame] | 21 | select HAVE_HARD_RESET |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 22 | select MMCONF_SUPPORT |
| 23 | select MMCONF_SUPPORT_DEFAULT |
| 24 | select RELOCATABLE_MODULES |
Aaron Durbin | 302cbd6 | 2013-10-21 12:36:17 -0500 | [diff] [blame] | 25 | select PARALLEL_MP |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 26 | select SMM_MODULES |
| 27 | select SMM_TSEG |
| 28 | select SMP |
| 29 | select SPI_FLASH |
| 30 | select SSE2 |
| 31 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 32 | select TSC_CONSTANT_RATE |
Aaron Durbin | ce7ecf9 | 2013-10-24 08:42:10 -0500 | [diff] [blame] | 33 | select TSC_MONOTONIC_TIMER |
Vadim Bendebury | c04e171 | 2013-09-27 16:21:04 -0700 | [diff] [blame] | 34 | select TSC_SYNC_MFENCE |
| 35 | select UDELAY_TSC |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 36 | |
| 37 | config BOOTBLOCK_CPU_INIT |
| 38 | string |
| 39 | default "soc/intel/baytrail/bootblock/bootblock.c" |
| 40 | |
| 41 | config MMCONF_BASE_ADDRESS |
| 42 | hex |
| 43 | default 0xe0000000 |
| 44 | |
| 45 | config MAX_CPUS |
| 46 | int |
| 47 | default 4 |
| 48 | |
| 49 | config CPU_ADDR_BITS |
| 50 | int |
| 51 | default 36 |
| 52 | |
| 53 | config SMM_TSEG_SIZE |
| 54 | hex |
| 55 | default 0x800000 |
| 56 | |
| 57 | config SMM_RESERVED_SIZE |
| 58 | hex |
| 59 | default 0x100000 |
| 60 | |
| 61 | config HAVE_MRC |
| 62 | bool "Add a Memory Reference Code binary" |
| 63 | default y |
| 64 | help |
| 65 | Select this option to add a blob containing |
| 66 | memory reference code. |
| 67 | Note: Without this binary coreboot will not work |
| 68 | |
| 69 | if HAVE_MRC |
| 70 | |
| 71 | config MRC_FILE |
| 72 | string "Intel memory refeference code path and filename" |
| 73 | default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin" |
| 74 | help |
| 75 | The path and filename of the file to use as System Agent |
| 76 | binary. Note that this points to the sandybridge binary file |
| 77 | which is will not work, but it serves its purpose to do builds. |
| 78 | |
| 79 | config MRC_BIN_ADDRESS |
| 80 | hex |
| 81 | default 0xfffa0000 |
| 82 | |
| 83 | config CACHE_MRC_SETTINGS |
| 84 | bool "Save cached MRC settings" |
| 85 | default n |
| 86 | |
| 87 | if CACHE_MRC_SETTINGS |
| 88 | |
| 89 | config MRC_SETTINGS_CACHE_BASE |
| 90 | hex |
| 91 | default 0xffb00000 |
| 92 | |
| 93 | config MRC_SETTINGS_CACHE_SIZE |
| 94 | hex |
| 95 | default 0x10000 |
| 96 | |
| 97 | endif # CACHE_MRC_SETTINGS |
| 98 | |
| 99 | endif # HAVE_MRC |
| 100 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 101 | # Cache As RAM region layout: |
| 102 | # |
| 103 | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE |
| 104 | # | MRC usage | |
| 105 | # | | |
| 106 | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE |
| 107 | # | Stack |\ |
| 108 | # | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| 109 | # | v |/ |
| 110 | # +-------------+ |
| 111 | # | ^ | |
| 112 | # | | | |
| 113 | # | CAR Globals | |
| 114 | # +-------------+ DCACHE_RAM_BASE |
| 115 | # |
| 116 | # Note that the MRC binary is linked to assume the region marked as "MRC usage" |
| 117 | # starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then |
| 118 | # a new MRC binary needs to be produced with the updated start and size |
| 119 | # information. |
| 120 | |
| 121 | config DCACHE_RAM_BASE |
| 122 | hex |
Aaron Durbin | 08a4613 | 2013-10-07 16:24:44 -0500 | [diff] [blame] | 123 | default 0xff800000 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 124 | |
| 125 | config DCACHE_RAM_SIZE |
| 126 | hex |
Aaron Durbin | 08a4613 | 2013-10-07 16:24:44 -0500 | [diff] [blame] | 127 | default 0x8000 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 128 | help |
| 129 | The size of the cache-as-ram region required during bootblock |
| 130 | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| 131 | must add up to a power of 2. |
| 132 | |
| 133 | config DCACHE_RAM_MRC_VAR_SIZE |
| 134 | hex |
Aaron Durbin | 08a4613 | 2013-10-07 16:24:44 -0500 | [diff] [blame] | 135 | default 0x8000 |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 136 | help |
| 137 | The amount of cache-as-ram region required by the reference code. |
| 138 | |
| 139 | config DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| 140 | hex |
| 141 | default 0x800 |
| 142 | help |
| 143 | The amount of anticipated stack usage from the data cache |
| 144 | during pre-ram rom stage execution. |
| 145 | |
| 146 | config RESET_ON_INVALID_RAMSTAGE_CACHE |
| 147 | bool "Reset the system on S3 wake when ramstage cache invalid." |
| 148 | default n |
| 149 | depends on RELOCATABLE_RAMSTAGE |
| 150 | help |
| 151 | The baytrail romstage code caches the loaded ramstage program |
| 152 | in SMM space. On S3 wake the romstage will copy over a fresh |
| 153 | ramstage that was cached in the SMM space. This option determines |
| 154 | the action to take when the ramstage cache is invalid. If selected |
| 155 | the system will reset otherwise the ramstage will be reloaded from |
| 156 | cbfs. |
| 157 | |
| 158 | config CBFS_SIZE |
| 159 | hex "Size of CBFS filesystem in ROM" |
| 160 | default 0x100000 |
| 161 | help |
| 162 | On Bay Trail systems the firmware image has to store a lot more |
| 163 | than just coreboot, including: |
| 164 | - a firmware descriptor |
| 165 | - Intel Management Engine firmware |
| 166 | - MRC cache information |
| 167 | This option allows to limit the size of the CBFS portion in the |
| 168 | firmware image. |
| 169 | |
| 170 | config ENABLE_BUILTIN_COM1 |
| 171 | bool "Enable builtin COM1 Serial Port" |
| 172 | default n |
| 173 | help |
| 174 | The PMC has a legacy COM1 serial port. Choose this option to |
| 175 | configure the pads and enable it. This serial port can be used for |
| 176 | the debug console. |
| 177 | |
| 178 | config HAVE_ME_BIN |
| 179 | bool "Add Intel Management Engine firmware" |
| 180 | default y |
| 181 | help |
| 182 | The Intel processor in the selected system requires a special firmware |
| 183 | for an integrated controller called Management Engine (ME). The ME |
| 184 | firmware might be provided in coreboot's 3rdparty repository. If |
| 185 | not and if you don't have the firmware elsewhere, you can still |
| 186 | build coreboot without it. In this case however, you'll have to make |
| 187 | sure that you don't overwrite your ME firmware on your flash ROM. |
| 188 | |
| 189 | config ME_BIN_PATH |
| 190 | string "Path to management engine firmware" |
| 191 | depends on HAVE_ME_BIN |
| 192 | default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" |
| 193 | |
| 194 | config HAVE_IFD_BIN |
| 195 | bool |
| 196 | default y |
| 197 | |
| 198 | config BUILD_WITH_FAKE_IFD |
| 199 | bool "Build with a fake IFD" |
| 200 | default y if !HAVE_IFD_BIN |
| 201 | help |
| 202 | If you don't have an Intel Firmware Descriptor (ifd.bin) for your |
| 203 | board, you can select this option and coreboot will build without it. |
| 204 | Though, the resulting coreboot.rom will not contain all parts required |
| 205 | to get coreboot running on your board. You can however write only the |
| 206 | BIOS section to your board's flash ROM and keep the other sections |
| 207 | untouched. Unfortunately the current version of flashrom doesn't |
| 208 | support this yet. But there is a patch pending [1]. |
| 209 | |
| 210 | WARNING: Never write a complete coreboot.rom to your flash ROM if it |
| 211 | was built with a fake IFD. It just won't work. |
| 212 | |
| 213 | [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html |
| 214 | |
| 215 | config IFD_BIOS_SECTION |
| 216 | depends on BUILD_WITH_FAKE_IFD |
| 217 | string |
| 218 | default "" |
| 219 | |
| 220 | config IFD_ME_SECTION |
| 221 | depends on BUILD_WITH_FAKE_IFD |
| 222 | string |
| 223 | default "" |
| 224 | |
| 225 | config IFD_PLATFORM_SECTION |
| 226 | depends on BUILD_WITH_FAKE_IFD |
| 227 | string |
| 228 | default "" |
| 229 | |
| 230 | config IFD_BIN_PATH |
| 231 | string "Path to intel firmware descriptor" |
| 232 | depends on !BUILD_WITH_FAKE_IFD |
| 233 | default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" |
| 234 | |
| 235 | endif |