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Huayang Duanc90a9e62020-06-22 19:52:45 +08001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <assert.h>
4#include <bootmode.h>
5#include <cbfs.h>
6#include <console/console.h>
7#include <ip_checksum.h>
Yu-Ping Wu71c5ca72021-01-13 10:29:18 +08008#include <mrc_cache.h>
9#include <soc/dramc_param.h>
Huayang Duanc90a9e62020-06-22 19:52:45 +080010#include <soc/emi.h>
Yu-Ping Wu71c5ca72021-01-13 10:29:18 +080011#include <soc/mmu_operations.h>
Huayang Duanc90a9e62020-06-22 19:52:45 +080012#include <symbols.h>
Huayang Duan68e597d2020-06-22 19:59:40 +080013#include <timer.h>
Huayang Duanc90a9e62020-06-22 19:52:45 +080014
Yu-Ping Wu71c5ca72021-01-13 10:29:18 +080015/* This must be defined in chromeos.fmd in same name and size. */
16#define CALIBRATION_REGION "RW_MRC_CACHE"
17#define CALIBRATION_REGION_SIZE 0x2000
18
19_Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE,
20 "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION);
21
Xi Chene8c681c2021-03-03 17:58:07 +080022const char *get_dram_geometry_str(u32 ddr_geometry);
23const char *get_dram_type_str(u32 ddr_type);
24
Huayang Duanc90a9e62020-06-22 19:52:45 +080025static int mt_mem_test(const struct dramc_data *dparam)
26{
27 if (CONFIG(MEMORY_TEST)) {
28 u8 *addr = _dram;
29 const struct ddr_base_info *ddr_info = &dparam->ddr_info;
30
31 for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) {
Xi Chen3827f562020-10-20 17:55:14 +080032 int result = complex_mem_test(addr, 0x2000);
Huayang Duanc90a9e62020-06-22 19:52:45 +080033
Xi Chen3827f562020-10-20 17:55:14 +080034 if (result != 0) {
35 printk(BIOS_ERR,
36 "[MEM] complex R/W mem test failed: %d\n", result);
Huayang Duanc90a9e62020-06-22 19:52:45 +080037 return -1;
Huayang Duanc90a9e62020-06-22 19:52:45 +080038 }
Xi Chene8c681c2021-03-03 17:58:07 +080039 printk(BIOS_DEBUG, "[MEM] rank %u complex R/W mem test passed\n", rank);
Huayang Duanc90a9e62020-06-22 19:52:45 +080040
41 addr += ddr_info->rank_size[rank];
42 }
43 }
44
45 return 0;
46}
47
Xi Chene8c681c2021-03-03 17:58:07 +080048const char *get_dram_geometry_str(u32 ddr_geometry)
49{
50 const char *s;
51
52 switch (ddr_geometry) {
53 case DDR_TYPE_2CH_2RK_4GB_2_2:
54 s = "2CH_2RK_4GB_2_2";
55 break;
56 case DDR_TYPE_2CH_2RK_6GB_3_3:
57 s = "2CH_2RK_6GB_3_3";
58 break;
59 case DDR_TYPE_2CH_2RK_8GB_4_4:
60 s = "2CH_2RK_8GB_4_4";
61 break;
62 case DDR_TYPE_2CH_2RK_8GB_4_4_BYTE:
63 s = "2CH_2RK_8GB_4_4_BYTE";
64 break;
65 case DDR_TYPE_2CH_1RK_4GB_4_0:
66 s = "2CH_1RK_4GB_4_0";
67 break;
68 case DDR_TYPE_2CH_2RK_6GB_2_4:
69 s = "2CH_2RK_6GB_2_4";
70 break;
71 default:
72 s = "";
73 break;
74 }
75
76 return s;
77}
78
79const char *get_dram_type_str(u32 ddr_type)
80{
81 const char *s;
82
83 switch (ddr_type) {
84 case DDR_TYPE_DISCRETE:
85 s = "DSC";
86 break;
87 case DDR_TYPE_EMCP:
88 s = "EMCP";
89 break;
90 default:
91 s = "";
92 break;
93 }
94
95 return s;
96}
97
98static int dram_run_fast_calibration(struct dramc_param *dparam)
Huayang Duanc90a9e62020-06-22 19:52:45 +080099{
Xi Chene8c681c2021-03-03 17:58:07 +0800100 const u16 config = CONFIG(MEDIATEK_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS;
Huayang Duanc90a9e62020-06-22 19:52:45 +0800101 if (dparam->dramc_datas.ddr_info.config_dvfs != config) {
102 printk(BIOS_WARNING,
Huayang Duan68e597d2020-06-22 19:59:40 +0800103 "DRAM-K: Incompatible config for calibration data from flash "
Huayang Duanc90a9e62020-06-22 19:52:45 +0800104 "(expected: %#x, saved: %#x)\n",
105 config, dparam->dramc_datas.ddr_info.config_dvfs);
106 return -1;
107 }
108
Huayang Duan68e597d2020-06-22 19:59:40 +0800109 printk(BIOS_INFO, "DRAM-K: DRAM calibration data valid pass\n");
Xi Chene8c681c2021-03-03 17:58:07 +0800110 init_dram_by_params(dparam);
Huayang Duanc90a9e62020-06-22 19:52:45 +0800111 if (mt_mem_test(&dparam->dramc_datas) == 0)
112 return 0;
113
114 return DRAMC_ERR_FAST_CALIBRATION;
115}
116
Huayang Duan68e597d2020-06-22 19:59:40 +0800117static int dram_run_full_calibration(struct dramc_param *dparam)
118{
119 /* Load and run the provided blob for full-calibration if available */
120 struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram");
121
122 initialize_dramc_param(dparam);
Yu-Ping Wu71c5ca72021-01-13 10:29:18 +0800123 dump_param_header(dparam);
Huayang Duan68e597d2020-06-22 19:59:40 +0800124
Huayang Duan68e597d2020-06-22 19:59:40 +0800125 if (cbfs_prog_stage_load(&dram)) {
126 printk(BIOS_ERR, "DRAM-K: CBFS load program failed\n");
127 return -2;
128 }
129
130 dparam->do_putc = do_putchar;
131
132 prog_set_entry(&dram, prog_entry(&dram), dparam);
133 prog_run(&dram);
134 if (dparam->header.status != DRAMC_SUCCESS) {
135 printk(BIOS_ERR, "DRAM-K: Full calibration failed: status = %d\n",
Xi Chene8c681c2021-03-03 17:58:07 +0800136 dparam->header.status);
Huayang Duan68e597d2020-06-22 19:59:40 +0800137 return -3;
138 }
139
140 if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) {
141 printk(BIOS_ERR,
142 "DRAM-K: Full calibration executed without saving parameters. "
143 "Please ensure the blob is built properly.\n");
144 return -4;
145 }
146
147 return 0;
148}
149
Huayang Duanc90a9e62020-06-22 19:52:45 +0800150static void mem_init_set_default_config(struct dramc_param *dparam,
Xi Chene8c681c2021-03-03 17:58:07 +0800151 const struct sdram_info *dram_info)
Huayang Duanc90a9e62020-06-22 19:52:45 +0800152{
Xi Chene8c681c2021-03-03 17:58:07 +0800153 u32 type, geometry;
Huayang Duanc90a9e62020-06-22 19:52:45 +0800154 memset(dparam, 0, sizeof(*dparam));
155
Xi Chene8c681c2021-03-03 17:58:07 +0800156 type = dram_info->ddr_type;
157 geometry = dram_info->ddr_geometry;
Huayang Duanc90a9e62020-06-22 19:52:45 +0800158
Yu-Ping Wuc074f612021-04-12 11:03:57 +0800159 dparam->dramc_datas.ddr_info.sdram.ddr_type = type;
Xi Chene8c681c2021-03-03 17:58:07 +0800160
161 if (CONFIG(MEDIATEK_DRAM_DVFS))
Huayang Duanc90a9e62020-06-22 19:52:45 +0800162 dparam->dramc_datas.ddr_info.config_dvfs = DRAMC_ENABLE_DVFS;
Huayang Duanc90a9e62020-06-22 19:52:45 +0800163
Yu-Ping Wuc074f612021-04-12 11:03:57 +0800164 dparam->dramc_datas.ddr_info.sdram.ddr_geometry = geometry;
Xi Chene8c681c2021-03-03 17:58:07 +0800165
166 printk(BIOS_INFO, "DRAM-K: ddr_type: %s, config_dvfs: %d, ddr_geometry: %s\n",
167 get_dram_type_str(type),
168 dparam->dramc_datas.ddr_info.config_dvfs,
169 get_dram_geometry_str(geometry));
Huayang Duanc90a9e62020-06-22 19:52:45 +0800170}
171
Yu-Ping Wu71c5ca72021-01-13 10:29:18 +0800172static void mt_mem_init_run(struct dramc_param *dparam,
Xi Chene8c681c2021-03-03 17:58:07 +0800173 const struct sdram_info *dram_info)
Huayang Duanc90a9e62020-06-22 19:52:45 +0800174{
Xi Chenf4bb77b2022-01-21 17:18:45 +0800175 const ssize_t mrc_cache_size = sizeof(*dparam);
Yu-Ping Wu71c5ca72021-01-13 10:29:18 +0800176 ssize_t data_size;
Huayang Duan68e597d2020-06-22 19:59:40 +0800177 struct stopwatch sw;
178 int ret;
Huayang Duanc90a9e62020-06-22 19:52:45 +0800179
180 /* Load calibration params from flash and run fast calibration */
Yu-Ping Wu71c5ca72021-01-13 10:29:18 +0800181 data_size = mrc_cache_load_current(MRC_TRAINING_DATA,
182 DRAMC_PARAM_HEADER_VERSION,
Xi Chenf4bb77b2022-01-21 17:18:45 +0800183 dparam, mrc_cache_size);
Yu-Ping Wu71c5ca72021-01-13 10:29:18 +0800184 if (data_size == mrc_cache_size) {
Huayang Duanc90a9e62020-06-22 19:52:45 +0800185 printk(BIOS_INFO, "DRAM-K: Running fast calibration\n");
Huayang Duan68e597d2020-06-22 19:59:40 +0800186 stopwatch_init(&sw);
187
188 ret = dram_run_fast_calibration(dparam);
189 if (ret != 0) {
190 printk(BIOS_ERR, "DRAM-K: Failed to run fast calibration "
191 "in %ld msecs, error: %d\n",
192 stopwatch_duration_msecs(&sw), ret);
Huayang Duanc90a9e62020-06-22 19:52:45 +0800193
194 /* Erase flash data after fast calibration failed */
Xi Chenf4bb77b2022-01-21 17:18:45 +0800195 memset(dparam, 0xa5, mrc_cache_size);
Yu-Ping Wuba494442021-04-15 10:06:27 +0800196 mrc_cache_stash_data(MRC_TRAINING_DATA,
197 DRAMC_PARAM_HEADER_VERSION,
Xi Chenf4bb77b2022-01-21 17:18:45 +0800198 dparam, mrc_cache_size);
Huayang Duanc90a9e62020-06-22 19:52:45 +0800199 } else {
Huayang Duan68e597d2020-06-22 19:59:40 +0800200 printk(BIOS_INFO, "DRAM-K: Fast calibration passed in %ld msecs\n",
201 stopwatch_duration_msecs(&sw));
Huayang Duanc90a9e62020-06-22 19:52:45 +0800202 return;
203 }
204 } else {
Yu-Ping Wu71c5ca72021-01-13 10:29:18 +0800205 printk(BIOS_WARNING, "DRAM-K: Invalid data in flash (size: %#zx, expected: %#zx)\n",
206 data_size, mrc_cache_size);
Huayang Duan68e597d2020-06-22 19:59:40 +0800207 }
208
209 /* Run full calibration */
210 printk(BIOS_INFO, "DRAM-K: Running full calibration\n");
Xi Chene8c681c2021-03-03 17:58:07 +0800211 mem_init_set_default_config(dparam, dram_info);
Huayang Duan68e597d2020-06-22 19:59:40 +0800212
213 stopwatch_init(&sw);
214 int err = dram_run_full_calibration(dparam);
215 if (err == 0) {
216 printk(BIOS_INFO, "DRAM-K: Full calibration passed in %ld msecs\n",
217 stopwatch_duration_msecs(&sw));
Yu-Ping Wuba494442021-04-15 10:06:27 +0800218 mrc_cache_stash_data(MRC_TRAINING_DATA,
219 DRAMC_PARAM_HEADER_VERSION,
Xi Chenf4bb77b2022-01-21 17:18:45 +0800220 dparam, mrc_cache_size);
Huayang Duan68e597d2020-06-22 19:59:40 +0800221 } else {
222 printk(BIOS_ERR, "DRAM-K: Full calibration failed in %ld msecs\n",
223 stopwatch_duration_msecs(&sw));
Huayang Duanc90a9e62020-06-22 19:52:45 +0800224 }
225}
226
Yu-Ping Wu71c5ca72021-01-13 10:29:18 +0800227void mt_mem_init(struct dramc_param *dparam)
Huayang Duanc90a9e62020-06-22 19:52:45 +0800228{
229 const struct sdram_info *sdram_param = get_sdram_config();
230
Yu-Ping Wu71c5ca72021-01-13 10:29:18 +0800231 mt_mem_init_run(dparam, sdram_param);
232}
233
234void mtk_dram_init(void)
235{
236 /* dramc_param is too large to fit in stack. */
237 static struct dramc_param dramc_parameter;
238 mt_mem_init(&dramc_parameter);
239 mtk_mmu_after_dram();
Huayang Duanc90a9e62020-06-22 19:52:45 +0800240}