Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <bootmode.h> |
| 5 | #include <cbfs.h> |
| 6 | #include <console/console.h> |
| 7 | #include <ip_checksum.h> |
Yu-Ping Wu | 71c5ca7 | 2021-01-13 10:29:18 +0800 | [diff] [blame] | 8 | #include <mrc_cache.h> |
| 9 | #include <soc/dramc_param.h> |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 10 | #include <soc/emi.h> |
Yu-Ping Wu | 71c5ca7 | 2021-01-13 10:29:18 +0800 | [diff] [blame] | 11 | #include <soc/mmu_operations.h> |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 12 | #include <symbols.h> |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 13 | #include <timer.h> |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 14 | |
Yu-Ping Wu | 71c5ca7 | 2021-01-13 10:29:18 +0800 | [diff] [blame] | 15 | /* This must be defined in chromeos.fmd in same name and size. */ |
| 16 | #define CALIBRATION_REGION "RW_MRC_CACHE" |
| 17 | #define CALIBRATION_REGION_SIZE 0x2000 |
| 18 | |
| 19 | _Static_assert(sizeof(struct dramc_param) <= CALIBRATION_REGION_SIZE, |
| 20 | "sizeof(struct dramc_param) exceeds " CALIBRATION_REGION); |
| 21 | |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 22 | const char *get_dram_geometry_str(u32 ddr_geometry); |
| 23 | const char *get_dram_type_str(u32 ddr_type); |
| 24 | |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 25 | static int mt_mem_test(const struct dramc_data *dparam) |
| 26 | { |
| 27 | if (CONFIG(MEMORY_TEST)) { |
| 28 | u8 *addr = _dram; |
| 29 | const struct ddr_base_info *ddr_info = &dparam->ddr_info; |
| 30 | |
| 31 | for (u8 rank = RANK_0; rank < ddr_info->support_ranks; rank++) { |
Xi Chen | 3827f56 | 2020-10-20 17:55:14 +0800 | [diff] [blame] | 32 | int result = complex_mem_test(addr, 0x2000); |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 33 | |
Xi Chen | 3827f56 | 2020-10-20 17:55:14 +0800 | [diff] [blame] | 34 | if (result != 0) { |
| 35 | printk(BIOS_ERR, |
| 36 | "[MEM] complex R/W mem test failed: %d\n", result); |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 37 | return -1; |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 38 | } |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 39 | printk(BIOS_DEBUG, "[MEM] rank %u complex R/W mem test passed\n", rank); |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 40 | |
| 41 | addr += ddr_info->rank_size[rank]; |
| 42 | } |
| 43 | } |
| 44 | |
| 45 | return 0; |
| 46 | } |
| 47 | |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 48 | const char *get_dram_geometry_str(u32 ddr_geometry) |
| 49 | { |
| 50 | const char *s; |
| 51 | |
| 52 | switch (ddr_geometry) { |
| 53 | case DDR_TYPE_2CH_2RK_4GB_2_2: |
| 54 | s = "2CH_2RK_4GB_2_2"; |
| 55 | break; |
| 56 | case DDR_TYPE_2CH_2RK_6GB_3_3: |
| 57 | s = "2CH_2RK_6GB_3_3"; |
| 58 | break; |
| 59 | case DDR_TYPE_2CH_2RK_8GB_4_4: |
| 60 | s = "2CH_2RK_8GB_4_4"; |
| 61 | break; |
| 62 | case DDR_TYPE_2CH_2RK_8GB_4_4_BYTE: |
| 63 | s = "2CH_2RK_8GB_4_4_BYTE"; |
| 64 | break; |
| 65 | case DDR_TYPE_2CH_1RK_4GB_4_0: |
| 66 | s = "2CH_1RK_4GB_4_0"; |
| 67 | break; |
| 68 | case DDR_TYPE_2CH_2RK_6GB_2_4: |
| 69 | s = "2CH_2RK_6GB_2_4"; |
| 70 | break; |
| 71 | default: |
| 72 | s = ""; |
| 73 | break; |
| 74 | } |
| 75 | |
| 76 | return s; |
| 77 | } |
| 78 | |
| 79 | const char *get_dram_type_str(u32 ddr_type) |
| 80 | { |
| 81 | const char *s; |
| 82 | |
| 83 | switch (ddr_type) { |
| 84 | case DDR_TYPE_DISCRETE: |
| 85 | s = "DSC"; |
| 86 | break; |
| 87 | case DDR_TYPE_EMCP: |
| 88 | s = "EMCP"; |
| 89 | break; |
| 90 | default: |
| 91 | s = ""; |
| 92 | break; |
| 93 | } |
| 94 | |
| 95 | return s; |
| 96 | } |
| 97 | |
| 98 | static int dram_run_fast_calibration(struct dramc_param *dparam) |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 99 | { |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 100 | const u16 config = CONFIG(MEDIATEK_DRAM_DVFS) ? DRAMC_ENABLE_DVFS : DRAMC_DISABLE_DVFS; |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 101 | if (dparam->dramc_datas.ddr_info.config_dvfs != config) { |
| 102 | printk(BIOS_WARNING, |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 103 | "DRAM-K: Incompatible config for calibration data from flash " |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 104 | "(expected: %#x, saved: %#x)\n", |
| 105 | config, dparam->dramc_datas.ddr_info.config_dvfs); |
| 106 | return -1; |
| 107 | } |
| 108 | |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 109 | printk(BIOS_INFO, "DRAM-K: DRAM calibration data valid pass\n"); |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 110 | init_dram_by_params(dparam); |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 111 | if (mt_mem_test(&dparam->dramc_datas) == 0) |
| 112 | return 0; |
| 113 | |
| 114 | return DRAMC_ERR_FAST_CALIBRATION; |
| 115 | } |
| 116 | |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 117 | static int dram_run_full_calibration(struct dramc_param *dparam) |
| 118 | { |
| 119 | /* Load and run the provided blob for full-calibration if available */ |
| 120 | struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); |
| 121 | |
| 122 | initialize_dramc_param(dparam); |
Yu-Ping Wu | 71c5ca7 | 2021-01-13 10:29:18 +0800 | [diff] [blame] | 123 | dump_param_header(dparam); |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 124 | |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 125 | if (cbfs_prog_stage_load(&dram)) { |
| 126 | printk(BIOS_ERR, "DRAM-K: CBFS load program failed\n"); |
| 127 | return -2; |
| 128 | } |
| 129 | |
| 130 | dparam->do_putc = do_putchar; |
| 131 | |
| 132 | prog_set_entry(&dram, prog_entry(&dram), dparam); |
| 133 | prog_run(&dram); |
| 134 | if (dparam->header.status != DRAMC_SUCCESS) { |
| 135 | printk(BIOS_ERR, "DRAM-K: Full calibration failed: status = %d\n", |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 136 | dparam->header.status); |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 137 | return -3; |
| 138 | } |
| 139 | |
| 140 | if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { |
| 141 | printk(BIOS_ERR, |
| 142 | "DRAM-K: Full calibration executed without saving parameters. " |
| 143 | "Please ensure the blob is built properly.\n"); |
| 144 | return -4; |
| 145 | } |
| 146 | |
| 147 | return 0; |
| 148 | } |
| 149 | |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 150 | static void mem_init_set_default_config(struct dramc_param *dparam, |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 151 | const struct sdram_info *dram_info) |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 152 | { |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 153 | u32 type, geometry; |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 154 | memset(dparam, 0, sizeof(*dparam)); |
| 155 | |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 156 | type = dram_info->ddr_type; |
| 157 | geometry = dram_info->ddr_geometry; |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 158 | |
Yu-Ping Wu | c074f61 | 2021-04-12 11:03:57 +0800 | [diff] [blame] | 159 | dparam->dramc_datas.ddr_info.sdram.ddr_type = type; |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 160 | |
| 161 | if (CONFIG(MEDIATEK_DRAM_DVFS)) |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 162 | dparam->dramc_datas.ddr_info.config_dvfs = DRAMC_ENABLE_DVFS; |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 163 | |
Yu-Ping Wu | c074f61 | 2021-04-12 11:03:57 +0800 | [diff] [blame] | 164 | dparam->dramc_datas.ddr_info.sdram.ddr_geometry = geometry; |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 165 | |
| 166 | printk(BIOS_INFO, "DRAM-K: ddr_type: %s, config_dvfs: %d, ddr_geometry: %s\n", |
| 167 | get_dram_type_str(type), |
| 168 | dparam->dramc_datas.ddr_info.config_dvfs, |
| 169 | get_dram_geometry_str(geometry)); |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 170 | } |
| 171 | |
Yu-Ping Wu | 71c5ca7 | 2021-01-13 10:29:18 +0800 | [diff] [blame] | 172 | static void mt_mem_init_run(struct dramc_param *dparam, |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 173 | const struct sdram_info *dram_info) |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 174 | { |
Yu-Ping Wu | 71c5ca7 | 2021-01-13 10:29:18 +0800 | [diff] [blame] | 175 | const ssize_t mrc_cache_size = sizeof(dparam->dramc_datas); |
| 176 | ssize_t data_size; |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 177 | struct stopwatch sw; |
| 178 | int ret; |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 179 | |
| 180 | /* Load calibration params from flash and run fast calibration */ |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 181 | mem_init_set_default_config(dparam, dram_info); |
Yu-Ping Wu | 71c5ca7 | 2021-01-13 10:29:18 +0800 | [diff] [blame] | 182 | data_size = mrc_cache_load_current(MRC_TRAINING_DATA, |
| 183 | DRAMC_PARAM_HEADER_VERSION, |
| 184 | &dparam->dramc_datas, |
| 185 | mrc_cache_size); |
| 186 | if (data_size == mrc_cache_size) { |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 187 | printk(BIOS_INFO, "DRAM-K: Running fast calibration\n"); |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 188 | stopwatch_init(&sw); |
| 189 | |
| 190 | ret = dram_run_fast_calibration(dparam); |
| 191 | if (ret != 0) { |
| 192 | printk(BIOS_ERR, "DRAM-K: Failed to run fast calibration " |
| 193 | "in %ld msecs, error: %d\n", |
| 194 | stopwatch_duration_msecs(&sw), ret); |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 195 | |
| 196 | /* Erase flash data after fast calibration failed */ |
Yu-Ping Wu | 71c5ca7 | 2021-01-13 10:29:18 +0800 | [diff] [blame] | 197 | memset(&dparam->dramc_datas, 0xa5, mrc_cache_size); |
Yu-Ping Wu | ba49444 | 2021-04-15 10:06:27 +0800 | [diff] [blame^] | 198 | mrc_cache_stash_data(MRC_TRAINING_DATA, |
| 199 | DRAMC_PARAM_HEADER_VERSION, |
| 200 | &dparam->dramc_datas, |
| 201 | mrc_cache_size); |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 202 | } else { |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 203 | printk(BIOS_INFO, "DRAM-K: Fast calibration passed in %ld msecs\n", |
| 204 | stopwatch_duration_msecs(&sw)); |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 205 | return; |
| 206 | } |
| 207 | } else { |
Yu-Ping Wu | 71c5ca7 | 2021-01-13 10:29:18 +0800 | [diff] [blame] | 208 | printk(BIOS_WARNING, "DRAM-K: Invalid data in flash (size: %#zx, expected: %#zx)\n", |
| 209 | data_size, mrc_cache_size); |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 210 | } |
| 211 | |
| 212 | /* Run full calibration */ |
| 213 | printk(BIOS_INFO, "DRAM-K: Running full calibration\n"); |
Xi Chen | e8c681c | 2021-03-03 17:58:07 +0800 | [diff] [blame] | 214 | mem_init_set_default_config(dparam, dram_info); |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 215 | |
| 216 | stopwatch_init(&sw); |
| 217 | int err = dram_run_full_calibration(dparam); |
| 218 | if (err == 0) { |
| 219 | printk(BIOS_INFO, "DRAM-K: Full calibration passed in %ld msecs\n", |
| 220 | stopwatch_duration_msecs(&sw)); |
Yu-Ping Wu | ba49444 | 2021-04-15 10:06:27 +0800 | [diff] [blame^] | 221 | mrc_cache_stash_data(MRC_TRAINING_DATA, |
| 222 | DRAMC_PARAM_HEADER_VERSION, |
| 223 | &dparam->dramc_datas, mrc_cache_size); |
Huayang Duan | 68e597d | 2020-06-22 19:59:40 +0800 | [diff] [blame] | 224 | } else { |
| 225 | printk(BIOS_ERR, "DRAM-K: Full calibration failed in %ld msecs\n", |
| 226 | stopwatch_duration_msecs(&sw)); |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 227 | } |
| 228 | } |
| 229 | |
Yu-Ping Wu | 71c5ca7 | 2021-01-13 10:29:18 +0800 | [diff] [blame] | 230 | void mt_mem_init(struct dramc_param *dparam) |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 231 | { |
| 232 | const struct sdram_info *sdram_param = get_sdram_config(); |
| 233 | |
Yu-Ping Wu | 71c5ca7 | 2021-01-13 10:29:18 +0800 | [diff] [blame] | 234 | mt_mem_init_run(dparam, sdram_param); |
| 235 | } |
| 236 | |
| 237 | void mtk_dram_init(void) |
| 238 | { |
| 239 | /* dramc_param is too large to fit in stack. */ |
| 240 | static struct dramc_param dramc_parameter; |
| 241 | mt_mem_init(&dramc_parameter); |
| 242 | mtk_mmu_after_dram(); |
Huayang Duan | c90a9e6 | 2020-06-22 19:52:45 +0800 | [diff] [blame] | 243 | } |