Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 2 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 3 | #include <arch/bootblock.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 5 | #include "haswell.h" |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 6 | |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 7 | void bootblock_early_northbridge_init(void) |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 8 | { |
| 9 | uint32_t reg; |
| 10 | |
| 11 | /* |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 12 | * The "io" variant of the config access is explicitly used to setup the PCIEXBAR |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame^] | 13 | * because CONFIG(MMCONF_SUPPORT) is set to true. That way, all subsequent |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 14 | * non-explicit config accesses use MCFG. This code also assumes that |
| 15 | * bootblock_northbridge_init() is the first thing called in the non-asm |
| 16 | * boot block code. The final assumption is that no assembly code is using |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame^] | 17 | * the CONFIG(MMCONF_SUPPORT) option to do PCI config acceses. |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 18 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 19 | * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 20 | */ |
| 21 | reg = 0; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 22 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg); |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 23 | reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 24 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 25 | } |