Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Kyösti Mälkki | de64078 | 2019-12-03 07:30:26 +0200 | [diff] [blame] | 14 | #include <arch/bootblock.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 15 | #include <device/pci_ops.h> |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 16 | #include "haswell.h" |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 17 | |
Arthur Heymans | 8e646e7 | 2018-06-05 11:19:22 +0200 | [diff] [blame] | 18 | void bootblock_early_northbridge_init(void) |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 19 | { |
| 20 | uint32_t reg; |
| 21 | |
| 22 | /* |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame^] | 23 | * The "io" variant of the config access is explicitly used to setup the PCIEXBAR |
| 24 | * because CONFIG_MMCONF_SUPPORT is set to true. That way, all subsequent |
| 25 | * non-explicit config accesses use MCFG. This code also assumes that |
| 26 | * bootblock_northbridge_init() is the first thing called in the non-asm |
| 27 | * boot block code. The final assumption is that no assembly code is using |
| 28 | * the CONFIG_MMCONF_SUPPORT option to do PCI config acceses. |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 29 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame^] | 30 | * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 31 | */ |
| 32 | reg = 0; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame^] | 33 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg); |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 34 | reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame^] | 35 | pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); |
Aaron Durbin | 6d04f0f | 2012-10-31 22:57:16 -0500 | [diff] [blame] | 36 | } |