Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 4 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 6 | #include <bootmode.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 7 | #include <console/console.h> |
| 8 | #include <delay.h> |
| 9 | #include <device/device.h> |
| 10 | #include <device/pci.h> |
| 11 | #include <device/pci_ids.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 12 | #include <string.h> |
| 13 | #include <reg_script.h> |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 14 | #include <cbmem.h> |
Matt DeVillier | 53e2446 | 2016-08-05 02:20:15 -0500 | [diff] [blame] | 15 | #include <drivers/intel/gma/i915.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 16 | #include <drivers/intel/gma/i915_reg.h> |
Nico Huber | a06689c | 2019-10-08 20:56:41 +0200 | [diff] [blame] | 17 | #include <drivers/intel/gma/libgfxinit.h> |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 18 | #include <drivers/intel/gma/opregion.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 19 | #include <soc/cpu.h> |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 20 | #include <soc/nvs.h> |
Duncan Laurie | 1e6b591 | 2015-01-30 16:33:43 -0800 | [diff] [blame] | 21 | #include <soc/pm.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 22 | #include <soc/ramstage.h> |
| 23 | #include <soc/systemagent.h> |
| 24 | #include <soc/intel/broadwell/chip.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 25 | #include <security/vboot/vbnv.h> |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 26 | #include <soc/igd.h> |
Elyes HAOUAS | 27d02d8 | 2019-05-15 21:11:39 +0200 | [diff] [blame] | 27 | #include <types.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 28 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 29 | #define GT_RETRY 1000 |
| 30 | enum { |
| 31 | GT_CDCLK_DEFAULT = 0, |
| 32 | GT_CDCLK_337, |
| 33 | GT_CDCLK_450, |
| 34 | GT_CDCLK_540, |
| 35 | GT_CDCLK_675, |
| 36 | }; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 37 | |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 38 | static u32 reg_em4; |
| 39 | static u32 reg_em5; |
| 40 | |
| 41 | u32 igd_get_reg_em4(void) { return reg_em4; } |
| 42 | u32 igd_get_reg_em5(void) { return reg_em5; } |
| 43 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 44 | struct reg_script haswell_early_init_script[] = { |
| 45 | /* Enable Force Wake */ |
| 46 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), |
| 47 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 48 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 49 | |
| 50 | /* Enable Counters */ |
| 51 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016), |
| 52 | |
| 53 | /* GFXPAUSE settings */ |
| 54 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00070020), |
| 55 | |
| 56 | /* ECO Settings */ |
| 57 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0xa180, 0xff3fffff, 0x15000000), |
| 58 | |
| 59 | /* Enable DOP Clock Gating */ |
| 60 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000003fd), |
| 61 | |
| 62 | /* Enable Unit Level Clock Gating */ |
| 63 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000080), |
| 64 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000), |
| 65 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000), |
| 66 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001), |
| 67 | |
| 68 | /* |
| 69 | * RC6 Settings |
| 70 | */ |
| 71 | |
| 72 | /* Wake Rate Limits */ |
| 73 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa090, 0x00000000), |
| 74 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa098, 0x03e80000), |
| 75 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa09c, 0x00280000), |
| 76 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0a8, 0x0001e848), |
| 77 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0ac, 0x00000019), |
| 78 | |
| 79 | /* Render/Video/Blitter Idle Max Count */ |
| 80 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a), |
| 81 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a), |
| 82 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a), |
| 83 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a), |
| 84 | |
| 85 | /* RC Sleep / RCx Thresholds */ |
| 86 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b0, 0x00000000), |
| 87 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b4, 0x000003e8), |
| 88 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa0b8, 0x0000c350), |
| 89 | |
| 90 | /* RP Settings */ |
| 91 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa010, 0x000f4240), |
| 92 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa014, 0x12060000), |
| 93 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa02c, 0x0000e808), |
| 94 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa030, 0x0003bd08), |
| 95 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa068, 0x000101d0), |
| 96 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa06c, 0x00055730), |
| 97 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a), |
| 98 | |
| 99 | /* RP Control */ |
| 100 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92), |
| 101 | |
| 102 | /* HW RC6 Control */ |
| 103 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x88040000), |
| 104 | |
| 105 | /* Video Frequency Request */ |
| 106 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000), |
| 107 | |
| 108 | /* Set RC6 VIDs */ |
| 109 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 110 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), |
| 111 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), |
| 112 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 113 | |
| 114 | /* Enable PM Interrupts */ |
| 115 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), |
| 116 | |
| 117 | /* Enable RC6 in idle */ |
| 118 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000), |
| 119 | |
| 120 | REG_SCRIPT_END |
| 121 | }; |
| 122 | |
| 123 | static const struct reg_script haswell_late_init_script[] = { |
| 124 | /* Lock settings */ |
| 125 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)), |
| 126 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a004, (1 << 4)), |
| 127 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a080, (1 << 2)), |
| 128 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)), |
| 129 | |
| 130 | /* Disable Force Wake */ |
| 131 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 132 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 133 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00000001), |
| 134 | |
| 135 | /* Enable power well for DP and Audio */ |
| 136 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), |
| 137 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, |
| 138 | (1 << 30), (1 << 30), GT_RETRY), |
| 139 | |
| 140 | REG_SCRIPT_END |
| 141 | }; |
| 142 | |
| 143 | static const struct reg_script broadwell_early_init_script[] = { |
| 144 | /* Enable Force Wake */ |
| 145 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 146 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 147 | |
| 148 | /* Enable push bus metric control and shift */ |
| 149 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000004), |
| 150 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa250, 0x000000ff), |
| 151 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa25c, 0x00000010), |
| 152 | |
Duncan Laurie | 84b9cf4 | 2014-07-31 10:46:57 -0700 | [diff] [blame] | 153 | /* GFXPAUSE settings (set based on stepping) */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 154 | |
| 155 | /* ECO Settings */ |
| 156 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x45200000), |
| 157 | |
| 158 | /* Enable DOP Clock Gating */ |
| 159 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000000fd), |
| 160 | |
| 161 | /* Enable Unit Level Clock Gating */ |
| 162 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000000), |
| 163 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0x40401000), |
| 164 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0x00000000), |
| 165 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0x02000001), |
| 166 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1a054, 0x0000000a), |
| 167 | |
| 168 | /* Video Frequency Request */ |
| 169 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000), |
| 170 | |
Duncan Laurie | 84b9cf4 | 2014-07-31 10:46:57 -0700 | [diff] [blame] | 171 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138158, 0x00000009), |
| 172 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x13815c, 0x0000000d), |
| 173 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 174 | /* |
| 175 | * RC6 Settings |
| 176 | */ |
| 177 | |
| 178 | /* Wake Rate Limits */ |
| 179 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0a090, 0, 0), |
| 180 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a098, 0x03e80000), |
| 181 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a09c, 0x00280000), |
| 182 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0a8, 0x0001e848), |
| 183 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0ac, 0x00000019), |
| 184 | |
| 185 | /* Render/Video/Blitter Idle Max Count */ |
| 186 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x02054, 0x0000000a), |
| 187 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000a), |
| 188 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000a), |
| 189 | |
| 190 | /* RC Sleep / RCx Thresholds */ |
| 191 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b0, 0x00000000), |
| 192 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a0b8, 0x00000271), |
| 193 | |
| 194 | /* RP Settings */ |
| 195 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a010, 0x000f4240), |
| 196 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a014, 0x12060000), |
| 197 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a02c, 0x0000e808), |
| 198 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a030, 0x0003bd08), |
| 199 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a068, 0x000101d0), |
| 200 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a06c, 0x00055730), |
| 201 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a070, 0x0000000a), |
| 202 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a168, 0x00000006), |
| 203 | |
| 204 | /* RP Control */ |
| 205 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000b92), |
| 206 | |
| 207 | /* HW RC6 Control */ |
| 208 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x90040000), |
| 209 | |
| 210 | /* Set RC6 VIDs */ |
| 211 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 212 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138128, 0), |
| 213 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138124, 0x80000004), |
| 214 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x138124, (1 << 31), 0, GT_RETRY), |
| 215 | |
| 216 | /* Enable PM Interrupts */ |
| 217 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), |
| 218 | |
| 219 | /* Enable RC6 in idle */ |
| 220 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa094, 0x00040000), |
| 221 | |
| 222 | REG_SCRIPT_END |
| 223 | }; |
| 224 | |
| 225 | static const struct reg_script broadwell_late_init_script[] = { |
| 226 | /* Lock settings */ |
| 227 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a248, (1 << 31)), |
| 228 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a000, (1 << 18)), |
| 229 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x0a180, (1 << 31)), |
| 230 | |
| 231 | /* Disable Force Wake */ |
| 232 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010000), |
Edward O'Callaghan | 986e85c | 2014-10-29 12:15:34 +1100 | [diff] [blame] | 233 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 0, GT_RETRY), |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 234 | |
| 235 | /* Enable power well for DP and Audio */ |
| 236 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x45400, (1 << 31)), |
| 237 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x45400, |
| 238 | (1 << 30), (1 << 30), GT_RETRY), |
| 239 | |
| 240 | REG_SCRIPT_END |
| 241 | }; |
| 242 | |
| 243 | u32 map_oprom_vendev(u32 vendev) |
| 244 | { |
| 245 | return SA_IGD_OPROM_VENDEV; |
| 246 | } |
| 247 | |
| 248 | static struct resource *gtt_res = NULL; |
| 249 | |
Matt DeVillier | 53e2446 | 2016-08-05 02:20:15 -0500 | [diff] [blame] | 250 | u32 gtt_read(u32 reg) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 251 | { |
| 252 | u32 val; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 253 | val = read32(res2mmio(gtt_res, reg, 0)); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 254 | return val; |
| 255 | |
| 256 | } |
| 257 | |
Matt DeVillier | 53e2446 | 2016-08-05 02:20:15 -0500 | [diff] [blame] | 258 | void gtt_write(u32 reg, u32 data) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 259 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 260 | write32(res2mmio(gtt_res, reg, 0), data); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) |
| 264 | { |
| 265 | u32 val = gtt_read(reg); |
| 266 | val &= andmask; |
| 267 | val |= ormask; |
| 268 | gtt_write(reg, val); |
| 269 | } |
| 270 | |
Matt DeVillier | 53e2446 | 2016-08-05 02:20:15 -0500 | [diff] [blame] | 271 | int gtt_poll(u32 reg, u32 mask, u32 value) |
| 272 | { unsigned int try = GT_RETRY; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 273 | u32 data; |
| 274 | |
| 275 | while (try--) { |
| 276 | data = gtt_read(reg); |
| 277 | if ((data & mask) == value) |
| 278 | return 1; |
| 279 | udelay(10); |
| 280 | } |
| 281 | |
| 282 | printk(BIOS_ERR, "GT init timeout\n"); |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | static void igd_setup_panel(struct device *dev) |
| 287 | { |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 288 | config_t *conf = config_of(dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 289 | u32 reg32; |
| 290 | |
| 291 | /* Setup Digital Port Hotplug */ |
| 292 | reg32 = gtt_read(PCH_PORT_HOTPLUG); |
| 293 | if (!reg32) { |
| 294 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 295 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 296 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 297 | gtt_write(PCH_PORT_HOTPLUG, reg32); |
| 298 | } |
| 299 | |
| 300 | /* Setup Panel Power On Delays */ |
| 301 | reg32 = gtt_read(PCH_PP_ON_DELAYS); |
| 302 | if (!reg32) { |
| 303 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 304 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 305 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 306 | gtt_write(PCH_PP_ON_DELAYS, reg32); |
| 307 | } |
| 308 | |
| 309 | /* Setup Panel Power Off Delays */ |
| 310 | reg32 = gtt_read(PCH_PP_OFF_DELAYS); |
| 311 | if (!reg32) { |
| 312 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 313 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 314 | gtt_write(PCH_PP_OFF_DELAYS, reg32); |
| 315 | } |
| 316 | |
| 317 | /* Setup Panel Power Cycle Delay */ |
| 318 | if (conf->gpu_panel_power_cycle_delay) { |
| 319 | reg32 = gtt_read(PCH_PP_DIVISOR); |
| 320 | reg32 &= ~0xff; |
| 321 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 322 | gtt_write(PCH_PP_DIVISOR, reg32); |
| 323 | } |
| 324 | |
Nico Huber | 3b57a7c | 2019-10-08 20:24:05 +0200 | [diff] [blame] | 325 | /* So far all devices seem to use the PCH PWM function. |
| 326 | The CPU PWM registers are all zero after reset. */ |
| 327 | if (conf->gpu_pch_backlight_pwm_hz) { |
| 328 | /* For Lynx Point-LP: |
| 329 | Reference clock is 24MHz. We can choose either a 16 |
| 330 | or a 128 step increment. Use 16 if we would have less |
| 331 | than 100 steps otherwise. */ |
| 332 | const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; |
| 333 | unsigned int pwm_increment, pwm_period; |
| 334 | u32 south_chicken2; |
| 335 | |
| 336 | south_chicken2 = gtt_read(SOUTH_CHICKEN2); |
| 337 | if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { |
| 338 | pwm_increment = 16; |
Nico Huber | e47132b | 2020-03-23 01:33:23 +0100 | [diff] [blame] | 339 | south_chicken2 |= 1 << 5; |
Nico Huber | 3b57a7c | 2019-10-08 20:24:05 +0200 | [diff] [blame] | 340 | } else { |
| 341 | pwm_increment = 128; |
Nico Huber | e47132b | 2020-03-23 01:33:23 +0100 | [diff] [blame] | 342 | south_chicken2 &= ~(1 << 5); |
Nico Huber | 3b57a7c | 2019-10-08 20:24:05 +0200 | [diff] [blame] | 343 | } |
| 344 | gtt_write(SOUTH_CHICKEN2, south_chicken2); |
| 345 | |
| 346 | pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; |
| 347 | /* Start with a 50% duty cycle. */ |
| 348 | gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); |
| 349 | |
| 350 | gtt_write(BLC_PWM_PCH_CTL1, |
| 351 | (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | |
| 352 | BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 353 | } |
| 354 | } |
| 355 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 356 | static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc, |
| 357 | struct device *const dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 358 | { |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 359 | const config_t *const conf = config_of(dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 360 | int cdclk = conf->cdclk; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 361 | |
| 362 | /* Check for ULX GT1 or GT2 */ |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 363 | const int devid = pci_read_config16(dev, PCI_DEVICE_ID); |
| 364 | const int gpu_is_ulx = devid == IGD_HASWELL_ULX_GT1 || |
| 365 | devid == IGD_HASWELL_ULX_GT2; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 366 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 367 | /* Check for fixed fused clock */ |
| 368 | if (gtt_read(0x42014) & 1 << 24) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 369 | cdclk = GT_CDCLK_450; |
| 370 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 371 | /* |
| 372 | * ULX defaults to 337MHz with possible override for 450MHz |
| 373 | * ULT is fixed at 450MHz |
| 374 | * others default to 540MHz with possible override for 450MHz |
| 375 | */ |
| 376 | if (gpu_is_ulx && cdclk <= GT_CDCLK_337) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 377 | cdclk = GT_CDCLK_337; |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 378 | else if (gpu_is_ulx || cpu_is_ult() || |
| 379 | cdclk == GT_CDCLK_337 || cdclk == GT_CDCLK_450) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 380 | cdclk = GT_CDCLK_450; |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 381 | else |
| 382 | cdclk = GT_CDCLK_540; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 383 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 384 | *cdsel = cdclk != GT_CDCLK_450; |
| 385 | *inform_pc = gpu_is_ulx; |
| 386 | return cdclk; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 387 | } |
| 388 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 389 | static int igd_get_cdclk_broadwell(u32 *const cdsel, int *const inform_pc, |
| 390 | struct device *const dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 391 | { |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 392 | static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 }; |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 393 | const config_t *const conf = config_of(dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 394 | int cdclk = conf->cdclk; |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 395 | |
| 396 | /* Check for ULX */ |
| 397 | const int devid = pci_read_config16(dev, PCI_DEVICE_ID); |
| 398 | const int gpu_is_ulx = devid == IGD_BROADWELL_Y_GT2; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 399 | |
| 400 | /* Inform power controller of upcoming frequency change */ |
| 401 | gtt_write(0x138128, 0); |
| 402 | gtt_write(0x13812c, 0); |
| 403 | gtt_write(0x138124, 0x80000018); |
| 404 | |
| 405 | /* Poll GT driver mailbox for run/busy clear */ |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 406 | if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { |
| 407 | *inform_pc = 1; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 408 | } else { |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 409 | cdclk = GT_CDCLK_450; |
| 410 | *inform_pc = 0; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 411 | } |
| 412 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 413 | /* Check for fixed fused clock */ |
| 414 | if (gtt_read(0x42014) & 1 << 24) |
| 415 | cdclk = GT_CDCLK_450; |
| 416 | |
| 417 | /* |
| 418 | * ULX defaults to 450MHz with possible override up to 540MHz |
| 419 | * ULT defaults to 540MHz with possible override up to 675MHz |
| 420 | * others default to 675MHz with possible override for lower freqs |
| 421 | */ |
| 422 | if (cdclk == GT_CDCLK_337) |
| 423 | cdclk = GT_CDCLK_337; |
| 424 | else if (cdclk == GT_CDCLK_450 || |
| 425 | (gpu_is_ulx && cdclk == GT_CDCLK_DEFAULT)) |
| 426 | cdclk = GT_CDCLK_450; |
| 427 | else if (cdclk == GT_CDCLK_540 || gpu_is_ulx || |
| 428 | (cpu_is_ult() && cdclk == GT_CDCLK_DEFAULT)) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 429 | cdclk = GT_CDCLK_540; |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 430 | else |
| 431 | cdclk = GT_CDCLK_675; |
| 432 | |
| 433 | *cdsel = cdsel_by_cdclk[cdclk]; |
| 434 | return cdclk; |
| 435 | } |
| 436 | |
| 437 | static void igd_cdclk_init(struct device *dev, const int is_broadwell) |
| 438 | { |
| 439 | u32 dpdiv, cdsel, cdval; |
| 440 | int cdclk, inform_pc; |
| 441 | |
| 442 | if (is_broadwell) |
| 443 | cdclk = igd_get_cdclk_broadwell(&cdsel, &inform_pc, dev); |
| 444 | else |
| 445 | cdclk = igd_get_cdclk_haswell(&cdsel, &inform_pc, dev); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 446 | |
| 447 | /* Set variables based on CD Clock setting */ |
| 448 | switch (cdclk) { |
| 449 | case GT_CDCLK_337: |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 450 | cdval = 337; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 451 | dpdiv = 169; |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 452 | reg_em4 = 16; |
| 453 | reg_em5 = 225; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 454 | break; |
| 455 | case GT_CDCLK_450: |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 456 | cdval = 449; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 457 | dpdiv = 225; |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 458 | reg_em4 = 4; |
| 459 | reg_em5 = 75; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 460 | break; |
| 461 | case GT_CDCLK_540: |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 462 | cdval = 539; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 463 | dpdiv = 270; |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 464 | reg_em4 = 4; |
| 465 | reg_em5 = 90; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 466 | break; |
| 467 | case GT_CDCLK_675: |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 468 | cdval = 674; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 469 | dpdiv = 338; |
Matt DeVillier | f8960a6 | 2016-11-16 23:37:43 -0600 | [diff] [blame] | 470 | reg_em4 = 8; |
| 471 | reg_em5 = 225; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 472 | default: |
| 473 | return; |
| 474 | } |
| 475 | |
| 476 | /* Set LPCLL_CTL CD Clock Frequency Select */ |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 477 | gtt_rmw(0x130040, 0xf3ffffff, cdsel << 26); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 478 | |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 479 | if (inform_pc) { |
| 480 | /* Inform power controller of selected frequency */ |
| 481 | gtt_write(0x138128, cdsel); |
| 482 | gtt_write(0x13812c, 0); |
| 483 | gtt_write(0x138124, 0x80000017); |
| 484 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 485 | |
| 486 | /* Program CD Clock Frequency */ |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 487 | gtt_rmw(0x46200, 0xfffffc00, cdval); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 488 | |
| 489 | /* Set CPU DP AUX 2X bit clock dividers */ |
| 490 | gtt_rmw(0x64010, 0xfffff800, dpdiv); |
| 491 | gtt_rmw(0x64810, 0xfffff800, dpdiv); |
| 492 | } |
| 493 | |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 494 | uintptr_t gma_get_gnvs_aslb(const void *gnvs) |
| 495 | { |
| 496 | const global_nvs_t *gnvs_ptr = gnvs; |
| 497 | return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); |
| 498 | } |
| 499 | |
| 500 | void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) |
| 501 | { |
| 502 | global_nvs_t *gnvs_ptr = gnvs; |
| 503 | if (gnvs_ptr) |
| 504 | gnvs_ptr->aslb = aslb; |
| 505 | } |
| 506 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 507 | static void igd_init(struct device *dev) |
| 508 | { |
| 509 | int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); |
| 510 | u32 rp1_gfx_freq; |
| 511 | |
| 512 | /* IGD needs to be Bus Master */ |
| 513 | u32 reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 514 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 515 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 516 | |
| 517 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 518 | if (!gtt_res || !gtt_res->base) |
| 519 | return; |
| 520 | |
| 521 | /* Wait for any configured pre-graphics delay */ |
Kyösti Mälkki | 1ec23c9 | 2015-05-29 06:18:18 +0300 | [diff] [blame] | 522 | if (!acpi_is_wakeup_s3()) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 523 | #if CONFIG(CHROMEOS) |
Joel Kitching | 807803a | 2019-05-10 12:58:53 +0800 | [diff] [blame] | 524 | if (display_init_required()) |
Duncan Laurie | 1e6b591 | 2015-01-30 16:33:43 -0800 | [diff] [blame] | 525 | mdelay(CONFIG_PRE_GRAPHICS_DELAY); |
Duncan Laurie | b8a7b71 | 2014-11-10 13:00:27 -0800 | [diff] [blame] | 526 | #else |
Duncan Laurie | 1e6b591 | 2015-01-30 16:33:43 -0800 | [diff] [blame] | 527 | mdelay(CONFIG_PRE_GRAPHICS_DELAY); |
Duncan Laurie | b8a7b71 | 2014-11-10 13:00:27 -0800 | [diff] [blame] | 528 | #endif |
Duncan Laurie | 1e6b591 | 2015-01-30 16:33:43 -0800 | [diff] [blame] | 529 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 530 | |
| 531 | /* Early init steps */ |
| 532 | if (is_broadwell) { |
| 533 | reg_script_run_on_dev(dev, broadwell_early_init_script); |
Duncan Laurie | 84b9cf4 | 2014-07-31 10:46:57 -0700 | [diff] [blame] | 534 | |
| 535 | /* Set GFXPAUSE based on stepping */ |
| 536 | if (cpu_stepping() <= (CPUID_BROADWELL_E0 & 0xf) && |
| 537 | systemagent_revision() <= 9) { |
| 538 | gtt_write(0xa000, 0x300ff); |
| 539 | } else { |
| 540 | gtt_write(0xa000, 0x30020); |
| 541 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 542 | } else { |
| 543 | reg_script_run_on_dev(dev, haswell_early_init_script); |
| 544 | } |
| 545 | |
| 546 | /* Set RP1 graphics frequency */ |
| 547 | rp1_gfx_freq = (MCHBAR32(0x5998) >> 8) & 0xff; |
| 548 | gtt_write(0xa008, rp1_gfx_freq << 24); |
| 549 | |
| 550 | /* Post VBIOS panel setup */ |
| 551 | igd_setup_panel(dev); |
| 552 | |
| 553 | /* Initialize PCI device, load/execute BIOS Option ROM */ |
| 554 | pci_dev_init(dev); |
| 555 | |
| 556 | /* Late init steps */ |
Nico Huber | e392f41 | 2016-12-07 19:29:08 +0100 | [diff] [blame] | 557 | igd_cdclk_init(dev, is_broadwell); |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 558 | if (is_broadwell) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 559 | reg_script_run_on_dev(dev, broadwell_late_init_script); |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 560 | else |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 561 | reg_script_run_on_dev(dev, haswell_late_init_script); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 562 | |
Duncan Laurie | 49efaf2 | 2014-10-09 16:13:24 -0700 | [diff] [blame] | 563 | if (gfx_get_init_done()) { |
| 564 | /* |
| 565 | * Work around VBIOS issue that is not clearing first 64 |
| 566 | * bytes of the framebuffer during VBE mode set. |
| 567 | */ |
| 568 | struct resource *fb = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 569 | memset((void *)((u32)fb->base), 0, 64); |
| 570 | } |
| 571 | |
Kyösti Mälkki | 1ec23c9 | 2015-05-29 06:18:18 +0300 | [diff] [blame] | 572 | if (!gfx_get_init_done() && !acpi_is_wakeup_s3()) { |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 573 | /* |
| 574 | * Enable DDI-A if the Option ROM did not execute: |
| 575 | * |
| 576 | * bit 0: Display detected (RO) |
| 577 | * bit 4: DDI A supports 4 lanes and DDI E is not used |
| 578 | * bit 7: DDI buffer is idle |
| 579 | */ |
| 580 | gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | |
| 581 | DDI_INIT_DISPLAY_DETECTED); |
| 582 | } |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 583 | |
Nico Huber | a06689c | 2019-10-08 20:56:41 +0200 | [diff] [blame] | 584 | if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { |
| 585 | int lightup_ok; |
| 586 | gma_gfxinit(&lightup_ok); |
| 587 | gfx_set_init_done(lightup_ok); |
| 588 | } |
| 589 | |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 590 | intel_gma_restore_opregion(); |
| 591 | } |
| 592 | |
| 593 | static unsigned long |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 594 | gma_write_acpi_tables(const struct device *const dev, unsigned long current, |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 595 | struct acpi_rsdp *const rsdp) |
| 596 | { |
| 597 | igd_opregion_t *opregion = (igd_opregion_t *)current; |
| 598 | global_nvs_t *gnvs; |
| 599 | |
| 600 | if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) |
| 601 | return current; |
| 602 | |
| 603 | current += sizeof(igd_opregion_t); |
| 604 | |
| 605 | /* GNVS has been already set up */ |
| 606 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 607 | if (gnvs) { |
| 608 | /* IGD OpRegion Base Address */ |
| 609 | gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); |
| 610 | } else { |
| 611 | printk(BIOS_ERR, "Error: GNVS table not found.\n"); |
| 612 | } |
| 613 | |
| 614 | current = acpi_align_current(current); |
| 615 | return current; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 616 | } |
| 617 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 618 | static void gma_generate_ssdt(const struct device *dev) |
Matt DeVillier | 53e2446 | 2016-08-05 02:20:15 -0500 | [diff] [blame] | 619 | { |
| 620 | const struct soc_intel_broadwell_config *chip = dev->chip_info; |
| 621 | |
| 622 | drivers_intel_gma_displays_ssdt_generate(&chip->gfx); |
| 623 | } |
| 624 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 625 | static struct device_operations igd_ops = { |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 626 | .read_resources = &pci_dev_read_resources, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 627 | .set_resources = &pci_dev_set_resources, |
| 628 | .enable_resources = &pci_dev_enable_resources, |
| 629 | .init = &igd_init, |
| 630 | .ops_pci = &broadwell_pci_ops, |
Matt DeVillier | 773488f | 2017-10-18 12:27:25 -0500 | [diff] [blame] | 631 | .write_acpi_tables = gma_write_acpi_tables, |
Matt DeVillier | 53e2446 | 2016-08-05 02:20:15 -0500 | [diff] [blame] | 632 | .acpi_fill_ssdt = gma_generate_ssdt, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 633 | }; |
| 634 | |
| 635 | static const unsigned short pci_device_ids[] = { |
| 636 | IGD_HASWELL_ULT_GT1, |
| 637 | IGD_HASWELL_ULT_GT2, |
| 638 | IGD_HASWELL_ULT_GT3, |
| 639 | IGD_BROADWELL_U_GT1, |
| 640 | IGD_BROADWELL_U_GT2, |
| 641 | IGD_BROADWELL_U_GT3_15W, |
| 642 | IGD_BROADWELL_U_GT3_28W, |
| 643 | IGD_BROADWELL_Y_GT2, |
| 644 | IGD_BROADWELL_H_GT2, |
| 645 | IGD_BROADWELL_H_GT3, |
| 646 | 0, |
| 647 | }; |
| 648 | |
| 649 | static const struct pci_driver igd_driver __pci_driver = { |
| 650 | .ops = &igd_ops, |
| 651 | .vendor = PCI_VENDOR_ID_INTEL, |
| 652 | .devices = pci_device_ids, |
| 653 | }; |