intel/broadwell: Implement proper backlight PWM config

Port the backlight-PWM handling from Skylake instead of the previously
used Haswell version. We use a 200Hz PWM signal for all boards. Which
is higher than the previous devicetree value, 183Hz, but that was over-
ridden by the VBIOS anyway. 200Hz is still very low, considering LED
backlights, but accurate values are unknown at this time.

Lynx Point, the PCH for Haswell and Broadwell, is a transition point
for the backlight-PWM config. On platforms with a PCH, we have:

  o Before Lynx Point:
    The CPU has no PWM pin and sends the PWM duty-cycle setting
    to the PCH. The PCH can choose to ignore that and use its own
    We use the CPU setting on these platforms.
  o Lynx Point + Haswell:
    The CPU has an additional PWM pin but can be set up to send
    its setting to the PCH as before. The PCH can still choose
    to ignore that.
    We use the CPU setting with Haswell.
  o Lynx Point + Broadwell:
    The CPU can't send its setting to the PCH anymore. BLM_PCH_
    OVERRIDE_ENABLE must always be set(!) if the PCH PWM pin is
    used (it virtually always is).
    We have to use the PCH setting in this case.
  o After Lynx Point:
    Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is
    implied and the bit not implemented anymore.

Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924
Signed-off-by: Nico Huber <>
Tested-by: build bot (Jenkins) <>
Reviewed-by: Arthur Heymans <>
10 files changed
tree: 5ed735666c0e98046b28fa74b878386bda47beba
  1. .checkpatch.conf
  2. .clang-format
  3. .editorconfig
  4. .gitignore
  5. .gitmodules
  6. .gitreview
  7. 3rdparty/
  10. Documentation/
  12. Makefile
  15. configs/
  16. gnat.adc
  17. payloads/
  18. src/
  20. util/

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.


After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)


  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

You can contact us directly on the coreboot mailing list:

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.