Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /* |
| 18 | * Helper functions for dealing with power management registers |
| 19 | * and the differences between PCH variants. |
| 20 | */ |
| 21 | |
Furquan Shaikh | 3efeeb2 | 2017-10-14 19:24:43 -0700 | [diff] [blame] | 22 | #include <arch/acpi.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 23 | #include <arch/io.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/pci.h> |
| 26 | #include <device/pci_def.h> |
| 27 | #include <console/console.h> |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 28 | #include <intelblocks/pmclib.h> |
Aaron Durbin | 38613d0 | 2016-07-14 00:56:58 -0500 | [diff] [blame] | 29 | #include <halt.h> |
Ravi Sarawadi | 1483d1f | 2017-09-28 17:06:01 -0700 | [diff] [blame] | 30 | #include <intelblocks/lpc_lib.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 31 | #include <intelblocks/tco.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 32 | #include <stdlib.h> |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 33 | #include <soc/gpe.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 34 | #include <soc/gpio.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 35 | #include <soc/iomap.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 36 | #include <soc/pci_devs.h> |
| 37 | #include <soc/pm.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 38 | #include <soc/pmc.h> |
| 39 | #include <soc/smbus.h> |
Duncan Laurie | 2f3736e | 2016-11-03 10:33:43 -0700 | [diff] [blame] | 40 | #include <timer.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 41 | #include <security/vboot/vbnv.h> |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 42 | #include "chip.h" |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 43 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 44 | /* |
| 45 | * SMI |
| 46 | */ |
| 47 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 48 | const char *const *soc_smi_sts_array(size_t *smi_arr) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 49 | { |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 50 | static const char *const smi_sts_bits[] = { |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 51 | [2] = "BIOS", |
| 52 | [3] = "LEGACY_USB", |
| 53 | [4] = "SLP_SMI", |
| 54 | [5] = "APM", |
| 55 | [6] = "SWSMI_TMR", |
| 56 | [8] = "PM1", |
| 57 | [9] = "GPE0", |
| 58 | [10] = "GPI", |
| 59 | [11] = "MCSMI", |
| 60 | [12] = "DEVMON", |
| 61 | [13] = "TCO", |
| 62 | [14] = "PERIODIC", |
| 63 | [15] = "SERIRQ_SMI", |
| 64 | [16] = "SMBUS_SMI", |
| 65 | [17] = "LEGACY_USB2", |
| 66 | [18] = "INTEL_USB2", |
| 67 | [20] = "PCI_EXP_SMI", |
| 68 | [21] = "MONITOR", |
| 69 | [26] = "SPI", |
Duncan Laurie | 8d01902 | 2016-10-25 19:58:27 -0700 | [diff] [blame] | 70 | [27] = "GPIO_UNLOCK", |
| 71 | [28] = "ESPI_SMI", |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 72 | }; |
| 73 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 74 | *smi_arr = ARRAY_SIZE(smi_sts_bits); |
| 75 | return smi_sts_bits; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 76 | } |
| 77 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 78 | /* |
| 79 | * TCO |
| 80 | */ |
| 81 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 82 | const char *const *soc_tco_sts_array(size_t *tco_arr) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 83 | { |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 84 | static const char *const tco_sts_bits[] = { |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 85 | [0] = "NMI2SMI", |
| 86 | [1] = "SW_TCO", |
| 87 | [2] = "TCO_INT", |
| 88 | [3] = "TIMEOUT", |
| 89 | [7] = "NEWCENTURY", |
| 90 | [8] = "BIOSWR", |
| 91 | [9] = "DMISCI", |
| 92 | [10] = "DMISMI", |
| 93 | [12] = "DMISERR", |
| 94 | [13] = "SLVSEL", |
| 95 | [16] = "INTRD_DET", |
| 96 | [17] = "SECOND_TO", |
| 97 | [18] = "BOOT", |
| 98 | [20] = "SMLINK_SLV" |
| 99 | }; |
| 100 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 101 | *tco_arr = ARRAY_SIZE(tco_sts_bits); |
| 102 | return tco_sts_bits; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 103 | } |
| 104 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 105 | /* |
| 106 | * GPE0 |
| 107 | */ |
| 108 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 109 | const char *const *soc_std_gpe_sts_array(size_t *gpe_arr) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 110 | { |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 111 | static const char *const gpe_sts_bits[] = { |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 112 | [1] = "HOTPLUG", |
| 113 | [2] = "SWGPE", |
| 114 | [6] = "TCO_SCI", |
| 115 | [7] = "SMB_WAK", |
| 116 | [9] = "PCI_EXP", |
| 117 | [10] = "BATLOW", |
| 118 | [11] = "PME", |
| 119 | [12] = "ME", |
| 120 | [13] = "PME_B0", |
Aaron Durbin | 7f78849 | 2015-07-24 17:10:31 -0500 | [diff] [blame] | 121 | [14] = "eSPI", |
| 122 | [15] = "GPIO Tier-2", |
| 123 | [16] = "LAN_WAKE", |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 124 | [18] = "WADT" |
| 125 | }; |
| 126 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 127 | *gpe_arr = ARRAY_SIZE(gpe_sts_bits); |
| 128 | return gpe_sts_bits; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | int acpi_sci_irq(void) |
| 132 | { |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 133 | int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 134 | int sci_irq = 9; |
| 135 | |
| 136 | /* Determine how SCI is routed. */ |
| 137 | switch (scis) { |
| 138 | case SCIS_IRQ9: |
| 139 | case SCIS_IRQ10: |
| 140 | case SCIS_IRQ11: |
| 141 | sci_irq = scis - SCIS_IRQ9 + 9; |
| 142 | break; |
| 143 | case SCIS_IRQ20: |
| 144 | case SCIS_IRQ21: |
| 145 | case SCIS_IRQ22: |
| 146 | case SCIS_IRQ23: |
| 147 | sci_irq = scis - SCIS_IRQ20 + 20; |
| 148 | break; |
| 149 | default: |
| 150 | printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); |
| 151 | sci_irq = 9; |
| 152 | break; |
| 153 | } |
| 154 | |
| 155 | printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); |
| 156 | return sci_irq; |
| 157 | } |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 158 | |
| 159 | uint8_t *pmc_mmio_regs(void) |
| 160 | { |
| 161 | uint32_t reg32; |
| 162 | |
| 163 | reg32 = pci_read_config32(PCH_DEV_PMC, PWRMBASE); |
| 164 | |
| 165 | /* 4KiB alignment. */ |
| 166 | reg32 &= ~0xfff; |
| 167 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 168 | return (void *)(uintptr_t) reg32; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 169 | } |
| 170 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 171 | uintptr_t soc_read_pmc_base(void) |
| 172 | { |
| 173 | return (uintptr_t) (pmc_mmio_regs()); |
| 174 | } |
| 175 | |
Furquan Shaikh | c4e652f | 2017-10-11 14:44:29 -0700 | [diff] [blame] | 176 | void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 177 | { |
Aaron Durbin | e4d7abc | 2017-04-16 22:05:36 -0500 | [diff] [blame] | 178 | DEVTREE_CONST struct soc_intel_skylake_config *config; |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 179 | |
| 180 | /* Look up the device in devicetree */ |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 181 | DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 182 | if (!dev || !dev->chip_info) { |
| 183 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
Shaunak Saha | ec1a24c | 2017-10-06 12:50:38 -0700 | [diff] [blame] | 184 | return; |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 185 | } |
| 186 | config = dev->chip_info; |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 187 | |
Shaunak Saha | d347680 | 2017-07-08 01:08:40 -0700 | [diff] [blame] | 188 | /* Assign to out variable */ |
| 189 | *dw0 = config->gpe0_dw0; |
| 190 | *dw1 = config->gpe0_dw1; |
| 191 | *dw2 = config->gpe0_dw2; |
Duncan Laurie | f0ba225 | 2016-10-25 20:03:56 -0700 | [diff] [blame] | 192 | } |
Aaron Durbin | d1fc8c1 | 2017-09-15 12:37:05 -0600 | [diff] [blame] | 193 | |
| 194 | int rtc_failure(void) |
| 195 | { |
| 196 | u8 reg8; |
| 197 | int rtc_failed; |
| 198 | /* PMC Controller Device 0x1F, Func 02 */ |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 199 | #if defined(__SIMPLE_DEVICE__) |
| 200 | pci_devfn_t dev = PCH_DEV_PMC; |
| 201 | #else |
| 202 | struct device *dev = PCH_DEV_PMC; |
| 203 | #endif |
Aaron Durbin | d1fc8c1 | 2017-09-15 12:37:05 -0600 | [diff] [blame] | 204 | reg8 = pci_read_config8(dev, GEN_PMCON_B); |
| 205 | rtc_failed = reg8 & RTC_BATTERY_DEAD; |
| 206 | if (rtc_failed) { |
| 207 | reg8 &= ~RTC_BATTERY_DEAD; |
| 208 | pci_write_config8(dev, GEN_PMCON_B, reg8); |
| 209 | printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); |
| 210 | } |
| 211 | |
| 212 | return !!rtc_failed; |
| 213 | } |
Aaron Durbin | 0990fbf | 2017-09-15 15:23:04 -0600 | [diff] [blame] | 214 | |
| 215 | int vbnv_cmos_failed(void) |
| 216 | { |
| 217 | return rtc_failure(); |
| 218 | } |
Furquan Shaikh | 3efeeb2 | 2017-10-14 19:24:43 -0700 | [diff] [blame] | 219 | |
| 220 | /* Return 0, 3, or 5 to indicate the previous sleep state. */ |
| 221 | int soc_prev_sleep_state(const struct chipset_power_state *ps, |
| 222 | int prev_sleep_state) |
| 223 | { |
| 224 | /* |
| 225 | * Check for any power failure to determine if this a wake from |
| 226 | * S5 because the PCH does not set the WAK_STS bit when waking |
| 227 | * from a true G3 state. |
| 228 | */ |
| 229 | if (!(ps->pm1_sts & WAK_STS) && |
| 230 | (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))) |
| 231 | prev_sleep_state = ACPI_S5; |
| 232 | |
| 233 | /* |
| 234 | * If waking from S3 determine if deep S3 is enabled. If not, |
| 235 | * need to check both deep sleep well and normal suspend well. |
| 236 | * Otherwise just check deep sleep well. |
| 237 | */ |
| 238 | if (prev_sleep_state == ACPI_S3) { |
| 239 | /* PWR_FLR represents deep sleep power well loss. */ |
| 240 | uint32_t mask = PWR_FLR; |
| 241 | |
| 242 | /* If deep s3 isn't enabled check the suspend well too. */ |
| 243 | if (!deep_s3_enabled()) |
| 244 | mask |= SUS_PWR_FLR; |
| 245 | |
| 246 | if (ps->gen_pmcon_b & mask) |
| 247 | prev_sleep_state = ACPI_S5; |
| 248 | } |
| 249 | return prev_sleep_state; |
| 250 | } |
| 251 | |
| 252 | void soc_fill_power_state(struct chipset_power_state *ps) |
| 253 | { |
Furquan Shaikh | 3efeeb2 | 2017-10-14 19:24:43 -0700 | [diff] [blame] | 254 | uint8_t *pmc; |
| 255 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 256 | ps->tco1_sts = tco_read_reg(TCO1_STS); |
| 257 | ps->tco2_sts = tco_read_reg(TCO2_STS); |
Furquan Shaikh | 3efeeb2 | 2017-10-14 19:24:43 -0700 | [diff] [blame] | 258 | |
| 259 | printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", |
| 260 | ps->tco1_sts, ps->tco2_sts); |
| 261 | |
| 262 | ps->gen_pmcon_a = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_A); |
| 263 | ps->gen_pmcon_b = pci_read_config32(PCH_DEV_PMC, GEN_PMCON_B); |
| 264 | |
| 265 | pmc = pmc_mmio_regs(); |
| 266 | ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); |
| 267 | ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); |
| 268 | |
| 269 | printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", |
| 270 | ps->gen_pmcon_a, ps->gen_pmcon_b); |
| 271 | |
| 272 | printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", |
| 273 | ps->gblrst_cause[0], ps->gblrst_cause[1]); |
| 274 | } |