soc/intel/{sky,apollo}lake: Wait until GPE is clear when reading
When reading+clearing a GPE for use as an interrupt we need to
re-read the status register and keep setting the clear bit until
it actually reads back clear. Also add a 1ms timeout in case the
status never clears.
This is needed if a device sends a longer interrupt pulse and it
is still asserted when the "ISR" goes to clear the status.
BUG=chrome-os-partner:59299
TEST=test cr50 TPM with 20us pulse to ensure it can successfully
communicate with the TPM and does not get confused due to seeing
interrupts that it should not.
Change-Id: I384f484a1728038d3a355586146deee089b22dd9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17212
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 203a430..73dc117 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -37,6 +37,7 @@
#include <soc/pm.h>
#include <soc/pmc.h>
#include <soc/smbus.h>
+#include <timer.h>
#include "chip.h"
/* Print status bits with descriptive names */
@@ -361,6 +362,8 @@
{
int bank;
uint32_t mask, sts;
+ struct stopwatch sw;
+ int rc = 0;
if (gpe < 0 || gpe > GPE0_WADT)
return -1;
@@ -368,12 +371,20 @@
bank = gpe / 32;
mask = 1 << (gpe % 32);
- sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));
- if (sts & mask) {
- outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));
- return 1;
- }
- return 0;
+ /* Wait up to 1ms for GPE status to clear */
+ stopwatch_init_msecs_expire(&sw, 1);
+ do {
+ if (stopwatch_expired(&sw))
+ return rc;
+
+ sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));
+ if (sts & mask) {
+ outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));
+ rc = 1;
+ }
+ } while (sts & mask);
+
+ return rc;
}
/* Enable all requested GPE */