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review.coreboot.org / coreboot / f14bd79ae161e65a0f6bb675452323ecd905a27e / . / util / msrtool / geodegx2.c
blob: b70a03d9a3a5da7b8df6e2d91b57b9858d90e98c [file] [log] [blame]
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]1/*
2 * This file is part of msrtool.
3 *
4 * Copyright (c) 2008 Peter Stuge <peter@stuge.se>
5 * Copyright (c) 2009 Nils Jacobs <njacobs8@hetnet.nl>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +0100[diff] [blame]18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]19 */
20
21#include "msrtool.h"
22
Anton Kochkov59b36f12012-07-21 07:29:48 +0400[diff] [blame]23int geodegx2_probe(const struct targetdef *target, const struct cpuid_t *id) {
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]24 return 5 == id->family && 5 == id->model;
25}
26
27const struct msrdef geodegx2_msrs[] = {
Nils Jacobsfb2b5842011-01-19 06:56:33 +0000[diff] [blame]28 { 0x10000020, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM0", "GLIU0 P2D Base Mask Descriptor 0", {
29 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
30 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
31 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
32 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
33 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
34 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
35 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
36 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
37 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
38 { BITVAL_EOT }
39 }},
40 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
41 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
42 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
43 { BITVAL_EOT }
44 }},
45 { 59, 20, RESERVED },
46 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
47 { BITVAL_EOT }
48 }},
49 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
50 { BITVAL_EOT }
51 }},
52 { BITS_EOT }
53 }},
54 { 0x10000021, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM1", "GLIU0 P2D Base Mask Descriptor 1", {
55 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
56 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
57 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
58 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
59 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
60 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
61 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
62 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
63 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
64 { BITVAL_EOT }
65 }},
66 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
67 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
68 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
69 { BITVAL_EOT }
70 }},
71 { 59, 20, RESERVED },
72 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
73 { BITVAL_EOT }
74 }},
75 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
76 { BITVAL_EOT }
77 }},
78 { BITS_EOT }
79 }},
80 { 0x10000022, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM2", "GLIU0 P2D Base Mask Descriptor 2", {
81 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
82 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
83 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
84 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
85 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
86 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
87 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
88 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
89 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
90 { BITVAL_EOT }
91 }},
92 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
93 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
94 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
95 { BITVAL_EOT }
96 }},
97 { 59, 20, RESERVED },
98 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
99 { BITVAL_EOT }
100 }},
101 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
102 { BITVAL_EOT }
103 }},
104 { BITS_EOT }
105 }},
106 { 0x10000023, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM3", "GLIU0 P2D Base Mask Descriptor 3", {
107 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
108 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
109 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
110 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
111 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
112 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
113 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
114 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
115 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
116 { BITVAL_EOT }
117 }},
118 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
119 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
120 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
121 { BITVAL_EOT }
122 }},
123 { 59, 20, RESERVED },
124 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
125 { BITVAL_EOT }
126 }},
127 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
128 { BITVAL_EOT }
129 }},
130 { BITS_EOT }
131 }},
132 { 0x10000024, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM4", "GLIU0 P2D Base Mask Descriptor 4", {
133 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
134 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
135 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
136 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
137 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
138 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
139 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
140 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
141 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
142 { BITVAL_EOT }
143 }},
144 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
145 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
146 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
147 { BITVAL_EOT }
148 }},
149 { 59, 20, RESERVED },
150 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
151 { BITVAL_EOT }
152 }},
153 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
154 { BITVAL_EOT }
155 }},
156 { BITS_EOT }
157 }},
158 { 0x10000025, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_P2D_BM5", "GLIU0 P2D Base Mask Descriptor 5", {
159 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
160 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
161 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
162 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
163 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
164 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
165 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
166 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
167 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
168 { BITVAL_EOT }
169 }},
170 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
171 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
172 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
173 { BITVAL_EOT }
174 }},
175 { 59, 20, RESERVED },
176 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
177 { BITVAL_EOT }
178 }},
179 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
180 { BITVAL_EOT }
181 }},
182 { BITS_EOT }
183 }},
184 { 0x10000026, MSRTYPE_RDWR, MSR2(0x00000FF0, 0xFFF00000), "GLIU0_P2D_BMO0", "GLIU0 P2D Base Mask Offset Descriptor 0", {
185 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
186 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
187 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
188 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
189 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
190 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
191 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
192 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
193 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
194 { BITVAL_EOT }
195 }},
196 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
197 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
198 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
199 { BITVAL_EOT }
200 }},
201 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
202 { BITVAL_EOT }
203 }},
204 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
205 { BITVAL_EOT }
206 }},
207 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
208 { BITVAL_EOT }
209 }},
210 { BITS_EOT }
211 }},
212 { 0x10000027, MSRTYPE_RDWR, MSR2(0x00000FF0, 0xFFF00000), "GLIU0_P2D_BMO1", "GLIU0 P2D Base Mask Offset Descriptor 1", {
213 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
214 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
215 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
216 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
217 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
218 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
219 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
220 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
221 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
222 { BITVAL_EOT }
223 }},
224 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
225 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
226 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
227 { BITVAL_EOT }
228 }},
229 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
230 { BITVAL_EOT }
231 }},
232 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
233 { BITVAL_EOT }
234 }},
235 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
236 { BITVAL_EOT }
237 }},
238 { BITS_EOT }
239 }},
240 { 0x10000028, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R0", "GLIU0 P2D Range Descriptor 0", {
241 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
242 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
243 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
244 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
245 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
246 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
247 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
248 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
249 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
250 { BITVAL_EOT }
251 }},
252 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
253 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
254 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
255 { BITVAL_EOT }
256 }},
257 { 59, 20, RESERVED },
258 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
259 { BITVAL_EOT }
260 }},
261 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
262 { BITVAL_EOT }
263 }},
264 { BITS_EOT }
265 }},
266 { 0x10000029, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO0", "GLIU0 P2D Range Offset Descriptor 0", {
267 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
268 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
269 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
270 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
271 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
272 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
273 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
274 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
275 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
276 { BITVAL_EOT }
277 }},
278 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
279 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
280 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
281 { BITVAL_EOT }
282 }},
283 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
284 { BITVAL_EOT }
285 }},
286 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
287 { BITVAL_EOT }
288 }},
289 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
290 { BITVAL_EOT }
291 }},
292 { BITS_EOT }
293 }},
294 { 0x1000002A, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO1", "GLIU0 P2D Range Offset Descriptor 1", {
295 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
296 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
297 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
298 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
299 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
300 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
301 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
302 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
303 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
304 { BITVAL_EOT }
305 }},
306 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
307 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
308 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
309 { BITVAL_EOT }
310 }},
311 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
312 { BITVAL_EOT }
313 }},
314 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
315 { BITVAL_EOT }
316 }},
317 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
318 { BITVAL_EOT }
319 }},
320 { BITS_EOT }
321 }},
322 { 0x1000002B, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_RO2", "GLIU0 P2D Range Offset Descriptor 2", {
323 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
324 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
325 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
326 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
327 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
328 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
329 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
330 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
331 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
332 { BITVAL_EOT }
333 }},
334 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
335 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
336 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
337 { BITVAL_EOT }
338 }},
339 { 59, 20, "POFFSET", "Physical Memory Address 2s Comp Offset", PRESENT_HEX, {
340 { BITVAL_EOT }
341 }},
342 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
343 { BITVAL_EOT }
344 }},
345 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
346 { BITVAL_EOT }
347 }},
348 { BITS_EOT }
349 }},
350 { 0x1000002C, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_P2D_SC0", "GLIU0 P2D Swiss Cheese Descriptor 0", {
351 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
352 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
353 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
354 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
355 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
356 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
357 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
358 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
359 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
360 { BITVAL_EOT }
361 }},
362 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
363 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
364 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
365 { BITVAL_EOT }
366 }},
367 { 59, 12, RESERVED },
368 { 47, 16, "WEN", "Enable hits to the base for the ith 16K page for writes", PRESENT_HEX, {
369 { BITVAL_EOT }
370 }},
371 { 31, 16, "REN", "Enable hits to the base for the ith 16K page for ", PRESENT_HEX, {
372 { BITVAL_EOT }
373 }},
374 { 15, 2, RESERVED },
375 { 13, 14, "PSCBASE", "Physical Memory Address Base for hit", PRESENT_HEX, {
376 { BITVAL_EOT }
377 }},
378 { BITS_EOT }
379 }},
380 { 0x100000E0, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM0", "GLIU0 IOD Base Mask Descriptor 0", {
381 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
382 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
383 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
384 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
385 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
386 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
387 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
388 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
389 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
390 { BITVAL_EOT }
391 }},
392 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
393 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
394 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
395 { BITVAL_EOT }
396 }},
397 { 59, 20, RESERVED },
398 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
399 { BITVAL_EOT }
400 }},
401 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
402 { BITVAL_EOT }
403 }},
404 { BITS_EOT }
405 }},
406 { 0x100000E1, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM1", "GLIU0 IOD Base Mask Descriptor 1", {
407 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
408 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
409 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
410 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
411 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
412 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
413 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
414 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
415 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
416 { BITVAL_EOT }
417 }},
418 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
419 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
420 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
421 { BITVAL_EOT }
422 }},
423 { 59, 20, RESERVED },
424 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
425 { BITVAL_EOT }
426 }},
427 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
428 { BITVAL_EOT }
429 }},
430 { BITS_EOT }
431 }},
432 { 0x100000E2, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU0_IOD_BM2", "GLIU0 IOD Base Mask Descriptor 2", {
433 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
434 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
435 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
436 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
437 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
438 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
439 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
440 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
441 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
442 { BITVAL_EOT }
443 }},
444 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
445 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
446 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
447 { BITVAL_EOT }
448 }},
449 { 59, 20, RESERVED },
450 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
451 { BITVAL_EOT }
452 }},
453 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
454 { BITVAL_EOT }
455 }},
456 { BITS_EOT }
457 }},
458 { 0x100000E3, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC0", "GLIU0 IOD Swiss Cheese Descriptor 0", {
459 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
460 { BITVAL_EOT }
461 }},
462 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
463 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
464 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
465 { BITVAL_EOT }
466 }},
467 { 59, 28, RESERVED },
468 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
469 { BITVAL_EOT }
470 }},
471 { 23, 2, RESERVED },
472 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
473 { BITVAL_EOT }
474 }},
475 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
476 { BITVAL_EOT }
477 }},
478 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
479 { BITVAL_EOT }
480 }},
481 { 2, 3, RESERVED },
482 { BITS_EOT }
483 }},
484 { 0x100000E4, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC1", "GLIU0 IOD Swiss Cheese Descriptor 1", {
485 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
486 { BITVAL_EOT }
487 }},
488 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
489 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
490 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
491 { BITVAL_EOT }
492 }},
493 { 59, 28, RESERVED },
494 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
495 { BITVAL_EOT }
496 }},
497 { 23, 2, RESERVED },
498 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
499 { BITVAL_EOT }
500 }},
501 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
502 { BITVAL_EOT }
503 }},
504 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
505 { BITVAL_EOT }
506 }},
507 { 2, 3, RESERVED },
508 { BITS_EOT }
509 }},
510 { 0x100000E5, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC2", "GLIU0 IOD Swiss Cheese Descriptor 2", {
511 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
512 { BITVAL_EOT }
513 }},
514 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
515 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
516 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
517 { BITVAL_EOT }
518 }},
519 { 59, 28, RESERVED },
520 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
521 { BITVAL_EOT }
522 }},
523 { 23, 2, RESERVED },
524 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
525 { BITVAL_EOT }
526 }},
527 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
528 { BITVAL_EOT }
529 }},
530 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
531 { BITVAL_EOT }
532 }},
533 { 2, 3, RESERVED },
534 { BITS_EOT }
535 }},
536 { 0x100000E6, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC3", "GLIU0 IOD Swiss Cheese Descriptor 3", {
537 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
538 { BITVAL_EOT }
539 }},
540 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
541 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
542 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
543 { BITVAL_EOT }
544 }},
545 { 59, 28, RESERVED },
546 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
547 { BITVAL_EOT }
548 }},
549 { 23, 2, RESERVED },
550 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
551 { BITVAL_EOT }
552 }},
553 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
554 { BITVAL_EOT }
555 }},
556 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
557 { BITVAL_EOT }
558 }},
559 { 2, 3, RESERVED },
560 { BITS_EOT }
561 }},
562 { 0x100000E7, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC4", "GLIU0 IOD Swiss Cheese Descriptor 4", {
563 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
564 { BITVAL_EOT }
565 }},
566 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
567 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
568 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
569 { BITVAL_EOT }
570 }},
571 { 59, 28, RESERVED },
572 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
573 { BITVAL_EOT }
574 }},
575 { 23, 2, RESERVED },
576 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
577 { BITVAL_EOT }
578 }},
579 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
580 { BITVAL_EOT }
581 }},
582 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
583 { BITVAL_EOT }
584 }},
585 { 2, 3, RESERVED },
586 { BITS_EOT }
587 }},
588 { 0x100000E8, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU0_IOD_SC5", "GLIU0 IOD Swiss Cheese Descriptor 5", {
589 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
590 { BITVAL_EOT }
591 }},
592 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
593 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
594 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
595 { BITVAL_EOT }
596 }},
597 { 59, 28, RESERVED },
598 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
599 { BITVAL_EOT }
600 }},
601 { 23, 2, RESERVED },
602 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
603 { BITVAL_EOT }
604 }},
605 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
606 { BITVAL_EOT }
607 }},
608 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
609 { BITVAL_EOT }
610 }},
611 { 2, 3, RESERVED },
612 { BITS_EOT }
613 }},
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]614 { 0x20000018, MSRTYPE_RDWR, MSR2(0x10071007, 0x40), "MC_CF07_DATA", "Refresh and SDRAM Program", {
615 { 63, 4, "D1_SZ", "DIMM1 Size", PRESENT_BIN, {
616 { MSR1(0), "Reserved" },
617 { MSR1(1), "8 MB" },
618 { MSR1(2), "16 MB" },
619 { MSR1(3), "32 MB" },
620 { MSR1(4), "64 MB" },
621 { MSR1(5), "128 MB" },
622 { MSR1(6), "256 MB" },
623 { MSR1(7), "512 MB" },
624 { MSR1(8), "Reserved" },
625 { MSR1(9), "Reserved" },
626 { MSR1(10), "Reserved" },
627 { MSR1(11), "Reserved" },
628 { MSR1(12), "Reserved" },
629 { MSR1(13), "Reserved" },
630 { MSR1(14), "Reserved" },
631 { MSR1(15), "Reserved" },
632 { BITVAL_EOT }
633 }},
634 { 59, 3, RESERVED },
635 { 56, 1, "D1_MB", "DIMM1 Module Banks", PRESENT_BIN, {
636 { MSR1(0), "1 Module bank" },
637 { MSR1(1), "2 Module banks" },
638 { BITVAL_EOT }
639 }},
640 { 55, 3, RESERVED },
641 { 52, 1, "D1_CB", "DIMM1 Component Banks", PRESENT_BIN, {
642 { MSR1(0), "2 Component banks" },
643 { MSR1(1), "4 Component banks" },
644 { BITVAL_EOT }
645 }},
646 { 51, 1, RESERVED },
647 { 50, 3, "D1_PSZ", "DIMM1 Page Size", PRESENT_BIN, {
648 { MSR1(0), "1 KB" },
649 { MSR1(1), "2 KB" },
650 { MSR1(2), "4 KB" },
651 { MSR1(3), "8 KB" },
652 { MSR1(4), "16 KB" },
653 { MSR1(5), "Reserved" },
654 { MSR1(6), "Reserved" },
655 { MSR1(7), "DIMM1 Not Installed" },
656 { BITVAL_EOT }
657 }},
658 { 47, 4, "D0_SZ", "DIMM0 Size", PRESENT_BIN, {
659 { MSR1(0), "Reserved" },
660 { MSR1(1), "8 MB" },
661 { MSR1(2), "16 MB" },
662 { MSR1(3), "32 MB" },
663 { MSR1(4), "64 MB" },
664 { MSR1(5), "128 MB" },
665 { MSR1(6), "256 MB" },
666 { MSR1(7), "512 MB" },
667 { MSR1(8), "Reserved" },
668 { MSR1(9), "Reserved" },
669 { MSR1(10), "Reserved" },
670 { MSR1(11), "Reserved" },
671 { MSR1(12), "Reserved" },
672 { MSR1(13), "Reserved" },
673 { MSR1(14), "Reserved" },
674 { MSR1(15), "Reserved" },
675 { BITVAL_EOT }
676 }},
677 { 43, 3, RESERVED },
678 { 40, 1, "D0_MB", "DIMM0 Module Banks", PRESENT_BIN, {
679 { MSR1(0), "1 Module bank" },
680 { MSR1(1), "2 Module banks" },
681 { BITVAL_EOT }
682 }},
683 { 39, 3, RESERVED },
684 { 36, 1, "D0_CB", "DIMM0 Component Banks", PRESENT_BIN, {
685 { MSR1(0), "2 Component banks" },
686 { MSR1(1), "4 Component banks" },
687 { BITVAL_EOT }
688 }},
689 { 35, 1, RESERVED },
690 { 34, 3, "D0_PSZ", "DIMM0 Page Size", PRESENT_BIN, {
691 { MSR1(0), "1 KB" },
692 { MSR1(1), "2 KB" },
693 { MSR1(2), "4 KB" },
694 { MSR1(3), "8 KB" },
695 { MSR1(4), "16 KB" },
696 { MSR1(5), "Reserved" },
697 { MSR1(6), "Reserved" },
698 { MSR1(7), "DIMM0 Not Installed" },
699 { BITVAL_EOT }
700 }},
701 { 31, 2, RESERVED },
702 { 29, 2, "EMR_BA", "Mode Register Set Bank Address", PRESENT_BIN, {
703 { MSR1(0), "Program the DIMM Mode Register" },
704 { MSR1(1), "Program the DIMM Extended Mode Register" },
705 { MSR1(2), "Reserved" },
706 { MSR1(3), "Reserved" },
707 { BITVAL_EOT }
708 }},
709 { 27, 1, RESERVED },
710 { 26, 1, "EMR_QFC", "Extended Mode Register FET Control", PRESENT_BIN, {
711 { MSR1(0), "Enable" },
712 { MSR1(1), "Disable" },
713 { BITVAL_EOT }
714 }},
715 { 25, 1, "EMR_DRV", "Extended Mode Register Drive Strength Control", PRESENT_BIN, {
716 { MSR1(0), "Normal" },
717 { MSR1(1), "Reduced" },
718 { BITVAL_EOT }
719 }},
720 { 24, 1, "EMR_DLL", "Extended Mode Register DLL", PRESENT_BIN, {
721 { MSR1(0), "Enable" },
722 { MSR1(1), "Disable" },
723 { BITVAL_EOT }
724 }},
725 { 23, 16, "REF_INT", "Refresh Interval", PRESENT_DEC, NOBITS },
726 { 7, 2, "REF_STAG", "Refresh Staggering", PRESENT_DEC, {
727 { MSR1(0), "4 SDRAM Clks" },
728 { MSR1(1), "1 SDRAM Clks" },
729 { MSR1(2), "2 SDRAM Clks" },
730 { MSR1(3), "3 SDRAM Clks" },
731 { BITVAL_EOT }
732 }},
733 { 5, 2, RESERVED },
734 { 3, 1, "REF_TST", "Test Refresh", PRESENT_BIN, NOBITS },
735 { 2, 1, RESERVED },
736 { 1, 1, "SOFT_RST", "Software Reset", PRESENT_BIN, NOBITS },
737 { 0, 1, "PROG_DRAM", "Program Mode Register in SDRAM", PRESENT_BIN, NOBITS },
738 { BITS_EOT }
739 }},
740 { 0x20000019, MSRTYPE_RDWR, MSR2(0x18000008, 0x287337a3), "MC_CF8F_DATA", "Timing and Mode Program", {
741 { 63, 8, "STALE_REQ", "GLIU Max Stale Request Count", PRESENT_DEC, NOBITS },
742 { 55, 3, RESERVED },
743 { 52, 2, "XOR_BIT_SEL", "XOR Bit Select", PRESENT_BIN, {
744 { MSR1(0), "ADDR[18]" },
745 { MSR1(1), "ADDR[19]" },
746 { MSR1(2), "ADDR[20]" },
747 { MSR1(3), "ADDR[21]" },
748 { BITVAL_EOT }
749 }},
750 { 50, 1, "XOR_MB0", "XOR MB0 Enable", PRESENT_BIN, {
751 { MSR1(0), "Disabled" },
752 { MSR1(1), "Enabled" },
753 { BITVAL_EOT }
754 }},
755 { 49, 1, "XOR_BA1", "XOR BA1 Enable", PRESENT_BIN, {
756 { MSR1(0), "Disabled" },
757 { MSR1(1), "Enabled" },
758 { BITVAL_EOT }
759 }},
760 { 48, 1, "XOR_BA0", "XOR BA0 Enable", PRESENT_BIN, {
761 { MSR1(0), "Disabled" },
762 { MSR1(1), "Enabled" },
763 { BITVAL_EOT }
764 }},
765 { 47, 8, RESERVED },
766 { 39, 1, "AP_B2B", "Autoprecharge Back-to-Back Command", PRESENT_BIN, {
767 { MSR1(0), "Enable" },
768 { MSR1(1), "Disable" },
769 { BITVAL_EOT }
770 }},
771 { 38, 1, "AP_EN", "Autoprecharge", PRESENT_BIN, {
772 { MSR1(0), "Enable" },
773 { MSR1(1), "Disable" },
774 { BITVAL_EOT }
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]775 }},
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]776 { 37, 4, RESERVED },
777 { 33, 1, "HOI_LOI", "High / Low Order Interleave Select", PRESENT_BIN, {
778 { MSR1(0), "Low Order Interleave" },
779 { MSR1(1), "High Order Interleave" },
780 { BITVAL_EOT }
781 }},
782 { 32, 1, RESERVED },
783 { 31, 1, "THZ_DLY", "tHZ Delay", PRESENT_BIN, NOBITS },
784 { 30, 3, "CAS_LAT", "Read CAS Latency", PRESENT_BIN, {
785 { MSR1(0), "Reserved" },
786 { MSR1(1), "Reserved" },
787 { MSR1(2), "2 Clks" },
788 { MSR1(3), "Reserved" },
789 { MSR1(4), "Reserved" },
790 { MSR1(5), "1.5 Clks" },
791 { MSR1(6), "2.5 Clks" },
792 { MSR1(7), "Reserved" },
793 { BITVAL_EOT }
794 }},
795 { 27, 4, "REF2ACT", "ACT to ACT/REF Period. tRC", PRESENT_BIN, {
796 { MSR1(0), "Reserved" },
797 { MSR1(1), "1 Clks" },
798 { MSR1(2), "2 Clks" },
799 { MSR1(3), "3 Clks" },
800 { MSR1(4), "4 Clks" },
801 { MSR1(5), "5 Clks" },
802 { MSR1(6), "7 Clks" },
803 { MSR1(7), "8 Clks" },
804 { MSR1(8), "9 Clks" },
805 { MSR1(9), "10 Clks" },
806 { MSR1(10), "11 Clks" },
807 { MSR1(11), "12 Clks" },
808 { MSR1(12), "13 Clks" },
809 { MSR1(13), "14 Clks" },
810 { MSR1(14), "15 Clks" },
811 { MSR1(15), "16 Clks" },
812 { BITVAL_EOT }
813 }},
814 { 23, 4, "ACT2PRE", "ACT to PRE Period. tRAS", PRESENT_BIN, {
815 { MSR1(0), "Reserved" },
816 { MSR1(1), "1 Clks" },
817 { MSR1(2), "2 Clks" },
818 { MSR1(3), "3 Clks" },
819 { MSR1(4), "4 Clks" },
820 { MSR1(5), "5 Clks" },
821 { MSR1(6), "7 Clks" },
822 { MSR1(7), "8 Clks" },
823 { MSR1(8), "9 Clks" },
824 { MSR1(9), "10 Clks" },
825 { MSR1(10), "11 Clks" },
826 { MSR1(11), "12 Clks" },
827 { MSR1(12), "13 Clks" },
828 { MSR1(13), "14 Clks" },
829 { MSR1(14), "15 Clks" },
830 { MSR1(15), "16 Clks" },
831 { BITVAL_EOT }
832 }},
833 { 19, 1, RESERVED },
834 { 18, 3, "PRE2ACT", "PRE to ACT Period. tRP", PRESENT_BIN, {
835 { MSR1(0), "Reserved" },
836 { MSR1(1), "1 Clks" },
837 { MSR1(2), "2 Clks" },
838 { MSR1(3), "3 Clks" },
839 { MSR1(4), "4 Clks" },
840 { MSR1(5), "5 Clks" },
841 { MSR1(6), "6 Clks" },
842 { MSR1(7), "7 Clks" },
843 { BITVAL_EOT }
844 }},
845 { 15, 1, RESERVED },
846 { 14, 3, "ACT2CMD", "Delay Time from ACT to Read/Write. tRCD", PRESENT_BIN, {
847 { MSR1(0), "Reserved" },
848 { MSR1(1), "1 Clks" },
849 { MSR1(2), "2 Clks" },
850 { MSR1(3), "3 Clks" },
851 { MSR1(4), "4 Clks" },
852 { MSR1(5), "5 Clks" },
853 { MSR1(6), "6 Clks" },
854 { MSR1(7), "Reserved" },
855 { BITVAL_EOT }
856 }},
857 { 11, 4, "ACT2ACT", "ACT(0) to ACT(1) Period. tRRD", PRESENT_BIN, {
858 { MSR1(0), "Reserved" },
859 { MSR1(1), "1 Clks" },
860 { MSR1(2), "2 Clks" },
861 { MSR1(3), "3 Clks" },
862 { MSR1(4), "4 Clks" },
863 { MSR1(5), "5 Clks" },
864 { MSR1(6), "6 Clks" },
865 { MSR1(7), "7 Clks" },
866 { MSR1(8), "Reserved" },
867 { MSR1(9), "Reserved" },
868 { MSR1(10), "Reserved" },
869 { MSR1(11), "Reserved" },
870 { MSR1(12), "Reserved" },
871 { MSR1(13), "Reserved" },
872 { MSR1(14), "Reserved" },
873 { MSR1(15), "Reserved" },
874 { BITVAL_EOT }
875 }},
876 { 7, 2, "DPLWR", "Data-in to PRE Period. tDPLW", PRESENT_DEC, {
877 { MSR1(0), "Invalid value" },
878 { MSR1(1), "1 Clks" },
879 { MSR1(2), "2 Clks" },
880 { MSR1(3), "3 Clks" },
881 { BITVAL_EOT }
882 }},
883 { 5, 2, "DPLRD", "Data-in to PRE Period. tDPLR", PRESENT_DEC, {
884 { MSR1(0), "Invalid value" },
885 { MSR1(1), "1 Clks" },
886 { MSR1(2), "2 Clks" },
887 { MSR1(3), "3 Clks" },
888 { BITVAL_EOT }
889 }},
890 { 3, 1, RESERVED },
891 { 2, 3, "DAL", "Data-in to ACT (REF) Period. tDAL", PRESENT_BIN, {
892 { MSR1(0), "Reserved" },
893 { MSR1(1), "1 clks" },
894 { MSR1(2), "2 Clks" },
895 { MSR1(3), "3 Clks" },
896 { MSR1(4), "4 Clks" },
897 { MSR1(5), "5 Clks" },
898 { MSR1(6), "6 Clks" },
899 { MSR1(7), "7 Clks" },
900 { BITVAL_EOT }
901 }},
902 { BITS_EOT }
903 }},
904 { 0x2000001a, MSRTYPE_RDWR, MSR2(0, 0), "MC_CF1017_DATA", "Feature Enables", {
905 { 63, 55, RESERVED },
906 { 8, 1, "PM1_UP_DLY", "PMode1 Up Delay", PRESENT_DEC, {
907 { MSR1(0), "No delay" },
908 { MSR1(1), "Enable delay" },
909 { BITVAL_EOT }
910 }},
911 { 7, 5, RESERVED },
912 { 2, 3, "WR2DAT", "Write Command to Data Latency", PRESENT_DEC, {
913 { MSR1(0), "Reserved" },
914 { MSR1(1), "Value when unbuffered DDR SDRAMs are used" },
915 { MSR1(2), "Value when registered DDR SDRAMs are used" },
916 { MSR1(3), "Reserved" },
917 { BITVAL_EOT }
918 }},
919 { BITS_EOT }
920 }},
921 { 0x2000001b, MSRTYPE_RDONLY, MSR2(0, 0), "MC_CFPERF_CNT1", "Performance Counters", {
922 { 63, 32, "CNT0", "Counter 0", PRESENT_DEC, NOBITS },
923 { 31, 32, "CNT1", "Counter 1", PRESENT_DEC, NOBITS },
924 { BITS_EOT }
925 }},
926 { 0x2000001c, MSRTYPE_RDWR, MSR2(0, 0x00ff00ff), "MC_PERFCNT2", "Counter and CAS Control", {
927 { 63, 28, RESERVED },
928 { 35, 1, "STOP_CNT1", "Stop Counter 1", PRESENT_DEC, {
929 { MSR1(0), "Counter 1 counts" },
930 { MSR1(1), "Stop Counter" },
931 { BITVAL_EOT }
932 }},
933 { 34, 1, "RST_CNT1", "Reset Counter 1", PRESENT_DEC, {
934 { MSR1(0), "Do nothing" },
935 { MSR1(1), "Reset counter 1" },
936 { BITVAL_EOT }
937 }},
938 { 33, 1, "STOP_CNT0", "Stop Counter 0", PRESENT_DEC, {
939 { MSR1(0), "Counter 0 counts" },
940 { MSR1(1), "Stop counter 0" },
941 { BITVAL_EOT }
942 }},
943 { 32, 1, "RST_CNT0", "Reset Counter 0", PRESENT_DEC, {
944 { MSR1(0), "Do nothing" },
945 { MSR1(1), "Reset counter 0" },
946 { BITVAL_EOT }
947 }},
948 { 31, 8, "CNT1_MASK", "Counter 1 Mask", PRESENT_BIN, NOBITS },
949 { 23, 8, "CNT1_DATA", "Counter 1 Data", PRESENT_BIN, NOBITS },
950 { 15, 8, "CNT0_MASK", "Counter 0 Mask", PRESENT_BIN, NOBITS },
951 { 7, 8, "CNT0_DATA", "Counter 0 Data", PRESENT_BIN, NOBITS },
952 { BITS_EOT }
953 }},
954 { 0x2000001d, MSRTYPE_RDWR, MSR2(0, 0x300), "MC_CFCLK_DBUG", "Clocking and Debug", {
955 { 63, 29, RESERVED },
956 { 34, 1, "B2B_EN", "Back-to-Back Command Enable", PRESENT_BIN, {
957 { MSR1(0), "Allow back-to-back commands" },
958 { MSR1(1), "Disable back-to-back commands" },
959 { BITVAL_EOT }
960 }},
961 { 33, 1, RESERVED },
962 { 32, 1, "MTEST_EN", "MTEST Enable", PRESENT_BIN, {
963 { MSR1(0), "Disable" },
964 { MSR1(1), "Enable" },
965 { BITVAL_EOT }
966 }},
967 { 31, 22, RESERVED },
968 { 9, 1, "MASK_CKE[1:0]", "CKE Mask", PRESENT_BIN, {
969 { MSR1(0), "CKE1 output enable unmasked" },
970 { MSR1(1), "CKE1 output enable masked" },
971 { BITVAL_EOT }
972 }},
973 { 8, 1, "MASK_CKE0", "CKE0 Mask", PRESENT_BIN, {
974 { MSR1(0), "CKE0 output enable unmasked" },
975 { MSR1(1), "CKE0 output enable masked" },
976 { BITVAL_EOT }
977 }},
978 { 7, 1, "CNTL_MSK1", "Control Mask 1", PRESENT_BIN, {
979 { MSR1(0), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable unmasked" },
980 { MSR1(1), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable masked" },
981 { BITVAL_EOT }
982 }},
983 { 6, 1, "CNTL_MSK0", "Control Mask 0", PRESENT_BIN, {
984 { MSR1(0), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable unmasked" },
985 { MSR1(1), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable masked" },
986 { BITVAL_EOT }
987 }},
988 { 5, 1, "ADRS_MSK", "Address Mask", PRESENT_BIN, {
989 { MSR1(0), "MA and BA output enable unmasked" },
990 { MSR1(1), "MA and BA output enable masked" },
991 { BITVAL_EOT }
992 }},
993 { 4, 5, RESERVED },
994 { BITS_EOT }
995 }},
Nils Jacobsfb2b5842011-01-19 06:56:33 +0000[diff] [blame]996 { 0x40000020, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM0", "GLIU1 P2D Base Mask Descriptor 0", {
997 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
998 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
999 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1000 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1001 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1002 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1003 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1004 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1005 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1006 { BITVAL_EOT }
1007 }},
1008 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1009 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1010 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1011 { BITVAL_EOT }
1012 }},
1013 { 59, 20, RESERVED },
1014 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1015 { BITVAL_EOT }
1016 }},
1017 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1018 { BITVAL_EOT }
1019 }},
1020 { BITS_EOT }
1021 }},
1022 { 0x40000021, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM1", "GLIU1 P2D Base Mask Descriptor 1", {
1023 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1024 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1025 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1026 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1027 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1028 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1029 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1030 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1031 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1032 { BITVAL_EOT }
1033 }},
1034 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1035 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1036 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1037 { BITVAL_EOT }
1038 }},
1039 { 59, 20, RESERVED },
1040 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1041 { BITVAL_EOT }
1042 }},
1043 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1044 { BITVAL_EOT }
1045 }},
1046 { BITS_EOT }
1047 }},
1048 { 0x40000022, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM2", "GLIU1 P2D Base Mask Descriptor 2", {
1049 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1050 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1051 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1052 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1053 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1054 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1055 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1056 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1057 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1058 { BITVAL_EOT }
1059 }},
1060 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1061 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1062 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1063 { BITVAL_EOT }
1064 }},
1065 { 59, 20, RESERVED },
1066 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1067 { BITVAL_EOT }
1068 }},
1069 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1070 { BITVAL_EOT }
1071 }},
1072 { BITS_EOT }
1073 }},
1074 { 0x40000023, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM3", "GLIU1 P2D Base Mask Descriptor 3", {
1075 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1076 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1077 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1078 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1079 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1080 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1081 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1082 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1083 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1084 { BITVAL_EOT }
1085 }},
1086 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1087 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1088 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1089 { BITVAL_EOT }
1090 }},
1091 { 59, 20, RESERVED },
1092 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1093 { BITVAL_EOT }
1094 }},
1095 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1096 { BITVAL_EOT }
1097 }},
1098 { BITS_EOT }
1099 }},
1100 { 0x40000024, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM4", "GLIU1 P2D Base Mask Descriptor 4", {
1101 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1102 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1103 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1104 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1105 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1106 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1107 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1108 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1109 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1110 { BITVAL_EOT }
1111 }},
1112 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1113 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1114 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1115 { BITVAL_EOT }
1116 }},
1117 { 59, 20, RESERVED },
1118 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1119 { BITVAL_EOT }
1120 }},
1121 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1122 { BITVAL_EOT }
1123 }},
1124 { BITS_EOT }
1125 }},
1126 { 0x40000025, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM5", "GLIU1 P2D Base Mask Descriptor 5", {
1127 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1128 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1129 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1130 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1131 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1132 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1133 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1134 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1135 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1136 { BITVAL_EOT }
1137 }},
1138 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1139 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1140 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1141 { BITVAL_EOT }
1142 }},
1143 { 59, 20, RESERVED },
1144 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1145 { BITVAL_EOT }
1146 }},
1147 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1148 { BITVAL_EOT }
1149 }},
1150 { BITS_EOT }
1151 }},
1152 { 0x40000026, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM6", "GLIU1 P2D Base Mask Descriptor 6", {
1153 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1154 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1155 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1156 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1157 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1158 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1159 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1160 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1161 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1162 { BITVAL_EOT }
1163 }},
1164 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1165 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1166 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1167 { BITVAL_EOT }
1168 }},
1169 { 59, 20, RESERVED },
1170 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1171 { BITVAL_EOT }
1172 }},
1173 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1174 { BITVAL_EOT }
1175 }},
1176 { BITS_EOT }
1177 }},
1178 { 0x40000027, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM7", "GLIU1 P2D Base Mask Descriptor 7", {
1179 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1180 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1181 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1182 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1183 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1184 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1185 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1186 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1187 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1188 { BITVAL_EOT }
1189 }},
1190 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1191 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1192 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1193 { BITVAL_EOT }
1194 }},
1195 { 59, 20, RESERVED },
1196 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1197 { BITVAL_EOT }
1198 }},
1199 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1200 { BITVAL_EOT }
1201 }},
1202 { BITS_EOT }
1203 }},
1204 { 0x40000028, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_P2D_BM8", "GLIU1 P2D Base Mask Descriptor 8", {
1205 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1206 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1207 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1208 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1209 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1210 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1211 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1212 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1213 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1214 { BITVAL_EOT }
1215 }},
1216 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1217 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1218 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1219 { BITVAL_EOT }
1220 }},
1221 { 59, 20, RESERVED },
1222 { 39, 20, "PBASE", "Physical Memory Address Base", PRESENT_HEX, {
1223 { BITVAL_EOT }
1224 }},
1225 { 19, 20, "PMASK", "Physical Memory Address Mask", PRESENT_HEX, {
1226 { BITVAL_EOT }
1227 }},
1228 { BITS_EOT }
1229 }},
1230 { 0x40000029, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU1_P2D_R0", "GLIU0 P2D Range Descriptor 0", {
1231 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1232 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1233 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1234 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1235 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1236 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1237 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1238 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1239 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1240 { BITVAL_EOT }
1241 }},
1242 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1243 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1244 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1245 { BITVAL_EOT }
1246 }},
1247 { 59, 20, RESERVED },
1248 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1249 { BITVAL_EOT }
1250 }},
1251 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1252 { BITVAL_EOT }
1253 }},
1254 { BITS_EOT }
1255 }},
1256 { 0x4000002A, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU1_P2D_R1", "GLIU0 P2D Range Descriptor 1", {
1257 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1258 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1259 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1260 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1261 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1262 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1263 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1264 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1265 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1266 { BITVAL_EOT }
1267 }},
1268 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1269 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1270 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1271 { BITVAL_EOT }
1272 }},
1273 { 59, 20, RESERVED },
1274 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1275 { BITVAL_EOT }
1276 }},
1277 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1278 { BITVAL_EOT }
1279 }},
1280 { BITS_EOT }
1281 }},
1282 { 0x4000002B, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R2", "GLIU0 P2D Range Descriptor 2", {
1283 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1284 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1285 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1286 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1287 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1288 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1289 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1290 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1291 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1292 { BITVAL_EOT }
1293 }},
1294 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1295 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1296 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1297 { BITVAL_EOT }
1298 }},
1299 { 59, 20, RESERVED },
1300 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1301 { BITVAL_EOT }
1302 }},
1303 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1304 { BITVAL_EOT }
1305 }},
1306 { BITS_EOT }
1307 }},
1308 { 0x4000002C, MSRTYPE_RDWR, MSR2(0x00000000, 0x000FFFFF), "GLIU0_P2D_R3", "GLIU0 P2D Range Descriptor 3", {
1309 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1310 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1311 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1312 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1313 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1314 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1315 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1316 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1317 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1318 { BITVAL_EOT }
1319 }},
1320 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1321 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1322 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1323 { BITVAL_EOT }
1324 }},
1325 { 59, 20, RESERVED },
1326 { 39, 20, "PMAX", "Physical Memory Address Max.", PRESENT_HEX, {
1327 { BITVAL_EOT }
1328 }},
1329 { 19, 20, "PMIN", "Physical Memory Address Min.", PRESENT_HEX, {
1330 { BITVAL_EOT }
1331 }},
1332 { BITS_EOT }
1333 }},
1334 { 0x4000002D, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_P2D_SC0", "GLIU1 P2D Swiss Cheese Descriptor 0", {
1335 { 63, 3, "PDID1", "Descriptor Destination ID", PRESENT_BIN, {
1336 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1337 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1338 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1339 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1340 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1341 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1342 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1343 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1344 { BITVAL_EOT }
1345 }},
1346 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1347 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1348 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1349 { BITVAL_EOT }
1350 }},
1351 { 59, 12, RESERVED },
1352 { 47, 16, "WEN", "Enable hits to the base for the ith 16K page for writes", PRESENT_HEX, {
1353 { BITVAL_EOT }
1354 }},
1355 { 31, 16, "REN", "Enable hits to the base for the ith 16K page for ", PRESENT_HEX, {
1356 { BITVAL_EOT }
1357 }},
1358 { 15, 2, RESERVED },
1359 { 13, 14, "PSCBASE", "Physical Memory Address Base for hit", PRESENT_HEX, {
1360 { BITVAL_EOT }
1361 }},
1362 { BITS_EOT }
1363 }},
1364 { 0x400000E0, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM0", "GLIU1 IOD Base Mask Descriptor 0", {
1365 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
1366 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1367 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1368 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1369 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1370 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1371 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1372 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1373 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1374 { BITVAL_EOT }
1375 }},
1376 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1377 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1378 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1379 { BITVAL_EOT }
1380 }},
1381 { 59, 20, RESERVED },
1382 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
1383 { BITVAL_EOT }
1384 }},
1385 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
1386 { BITVAL_EOT }
1387 }},
1388 { BITS_EOT }
1389 }},
1390 { 0x400000E1, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM1", "GLIU1 IOD Base Mask Descriptor 1", {
1391 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
1392 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1393 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1394 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1395 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1396 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1397 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1398 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1399 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1400 { BITVAL_EOT }
1401 }},
1402 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1403 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1404 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1405 { BITVAL_EOT }
1406 }},
1407 { 59, 20, RESERVED },
1408 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
1409 { BITVAL_EOT }
1410 }},
1411 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
1412 { BITVAL_EOT }
1413 }},
1414 { BITS_EOT }
1415 }},
1416 { 0x400000E2, MSRTYPE_RDWR, MSR2(0x000000FF, 0xFFF00000), "GLIU1_IOD_BM2", "GLIU1 IOD Base Mask Descriptor 2", {
1417 { 63, 3, "IDID", "IO Descriptor Destination ID", PRESENT_BIN, {
1418 { MSR1(0), "Port 0 = GLIU0:GLIU GLIU1:GLIU" },
1419 { MSR1(1), "Port 1 = GLIU0:GLMC GLIU1:Interface to GLIU0" },
1420 { MSR1(2), "Port 2 = GLIU0:Interface to GLIU1 GLIU1:Not Used" },
1421 { MSR1(3), "Port 3 = GLIU0:CPU Core GLIU1:GLCP" },
1422 { MSR1(4), "Port 4 = GLIU0:DC GLIU1:GLPCI" },
1423 { MSR1(5), "Port 5 = GLIU0:GP GLIU1:GIO" },
1424 { MSR1(6), "Port 6 = GLIU0:VP GLIU1:Not Used" },
1425 { MSR1(7), "Port 7 = GLIU0:Not Used GLIU1:Not Used" },
1426 { BITVAL_EOT }
1427 }},
1428 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1429 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1430 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1431 { BITVAL_EOT }
1432 }},
1433 { 59, 20, RESERVED },
1434 { 39, 20, "IBASE", "Physical IO Address Base", PRESENT_HEX, {
1435 { BITVAL_EOT }
1436 }},
1437 { 19, 20, "IMASK", "Physical IO Address Mask", PRESENT_HEX, {
1438 { BITVAL_EOT }
1439 }},
1440 { BITS_EOT }
1441 }},
1442 { 0x400000E3, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC0", "GLIU1 IOD Swiss Cheese Descriptor 0", {
1443 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1444 { BITVAL_EOT }
1445 }},
1446 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1447 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1448 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1449 { BITVAL_EOT }
1450 }},
1451 { 59, 28, RESERVED },
1452 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1453 { BITVAL_EOT }
1454 }},
1455 { 23, 2, RESERVED },
1456 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1457 { BITVAL_EOT }
1458 }},
1459 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1460 { BITVAL_EOT }
1461 }},
1462 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1463 { BITVAL_EOT }
1464 }},
1465 { 2, 3, RESERVED },
1466 { BITS_EOT }
1467 }},
1468 { 0x400000E4, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC1", "GLIU1 IOD Swiss Cheese Descriptor 1", {
1469 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1470 { BITVAL_EOT }
1471 }},
1472 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1473 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1474 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1475 { BITVAL_EOT }
1476 }},
1477 { 59, 28, RESERVED },
1478 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1479 { BITVAL_EOT }
1480 }},
1481 { 23, 2, RESERVED },
1482 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1483 { BITVAL_EOT }
1484 }},
1485 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1486 { BITVAL_EOT }
1487 }},
1488 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1489 { BITVAL_EOT }
1490 }},
1491 { 2, 3, RESERVED },
1492 { BITS_EOT }
1493 }},
1494 { 0x400000E5, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC2", "GLIU1 IOD Swiss Cheese Descriptor 2", {
1495 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1496 { BITVAL_EOT }
1497 }},
1498 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1499 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1500 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1501 { BITVAL_EOT }
1502 }},
1503 { 59, 28, RESERVED },
1504 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1505 { BITVAL_EOT }
1506 }},
1507 { 23, 2, RESERVED },
1508 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1509 { BITVAL_EOT }
1510 }},
1511 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1512 { BITVAL_EOT }
1513 }},
1514 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1515 { BITVAL_EOT }
1516 }},
1517 { 2, 3, RESERVED },
1518 { BITS_EOT }
1519 }},
1520 { 0x400000E6, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC3", "GLIU1 IOD Swiss Cheese Descriptor 3", {
1521 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1522 { BITVAL_EOT }
1523 }},
1524 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1525 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1526 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1527 { BITVAL_EOT }
1528 }},
1529 { 59, 28, RESERVED },
1530 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1531 { BITVAL_EOT }
1532 }},
1533 { 23, 2, RESERVED },
1534 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1535 { BITVAL_EOT }
1536 }},
1537 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1538 { BITVAL_EOT }
1539 }},
1540 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1541 { BITVAL_EOT }
1542 }},
1543 { 2, 3, RESERVED },
1544 { BITS_EOT }
1545 }},
1546 { 0x400000E7, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC4", "GLIU1 IOD Swiss Cheese Descriptor 4", {
1547 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1548 { BITVAL_EOT }
1549 }},
1550 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1551 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1552 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1553 { BITVAL_EOT }
1554 }},
1555 { 59, 28, RESERVED },
1556 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1557 { BITVAL_EOT }
1558 }},
1559 { 23, 2, RESERVED },
1560 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1561 { BITVAL_EOT }
1562 }},
1563 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1564 { BITVAL_EOT }
1565 }},
1566 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1567 { BITVAL_EOT }
1568 }},
1569 { 2, 3, RESERVED },
1570 { BITS_EOT }
1571 }},
1572 { 0x400000E8, MSRTYPE_RDWR, MSR2(0x00000000, 0x00000000), "GLIU1_IOD_SC5", "GLIU1 IOD Swiss Cheese Descriptor 5", {
1573 { 63, 3, "IDID1", "Descriptor Destination ID 1", PRESENT_BIN, {
1574 { BITVAL_EOT }
1575 }},
1576 { 36, 1, "PCMP_BIZ", "Compare Bizarro Flag", PRESENT_BIN, {
1577 { MSR1(0), "Only act if Bizarro Flag = 0 (Memory or I/O)" },
1578 { MSR1(1), "Only act if Bizarro Flag = 1 (PCI, Shutdown or Halt)" },
1579 { BITVAL_EOT }
1580 }},
1581 { 59, 28, RESERVED },
1582 { 31, 8, "EN", "Enable for hits to IDID1 or else SUBP", PRESENT_HEX, {
1583 { BITVAL_EOT }
1584 }},
1585 { 23, 2, RESERVED },
1586 { 21, 1, "WEN", "Descriptor hits IDID1 on write request Types else SUBP", PRESENT_BIN, {
1587 { BITVAL_EOT }
1588 }},
1589 { 20, 1, "WEN", "Descriptor hit IDID1 on write request Types else SUBP", PRESENT_BIN, {
1590 { BITVAL_EOT }
1591 }},
1592 { 19, 17, "IBASE", "IO Memory Base", PRESENT_HEX, {
1593 { BITVAL_EOT }
1594 }},
1595 { 2, 3, RESERVED },
1596 { BITS_EOT }
1597 }},
Nils Jacobsfb333c42010-01-15 10:07:05 +0000[diff] [blame]1598 { 0x4c00000f, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_DELAY_CONTROLS", "GLCP I/O Delay Controls", {
1599 { 63, 1, "EN", "Delay Settings Enable", PRESENT_DEC, {
1600 { MSR1(0), "Use default values" },
1601 { MSR1(1), "Use value in bits [62:0]" },
1602 { BITVAL_EOT }
1603 }},
1604 { 62, 2, RESERVED },
1605 { 60, 5, "GIO", "Delay Geode Companion Device", PRESENT_DEC, NOBITS },
1606 { 55, 5, "PCI_IN", "Delay PCI Inputs", PRESENT_DEC, NOBITS },
1607 { 50, 5, "PCI_OUT", "Delay PCI Outputs", PRESENT_DEC, NOBITS },
1608 { 45, 5, RESERVED},
1609 { 40, 5, "DOTCLK", "Delay Dot Clock", PRESENT_DEC, NOBITS },
1610 { 35, 5, "DRGB", "Delay Digital RGBs", PRESENT_DEC, NOBITS },
1611 { 30, 5, "SDCLK_IN", "Delay SDRAM Clock Input", PRESENT_DEC, NOBITS },
1612 { 25, 5, "SDCLK_OUT", "Delay SDRAM Clock Output", PRESENT_DEC, NOBITS },
1613 { 20, 5, "MEM_CTL", "Delay Memory Controls", PRESENT_DEC, NOBITS },
1614 { 15, 9, RESERVED},
1615 { 6, 1, "MEM_ODDOUT", "Delay Odd Memory Data Output Bits", PRESENT_DEC, {
1616 { MSR1(0), "No Delay" },
1617 { MSR1(1), "Delay" },
1618 { BITVAL_EOT }
1619 }},
1620 { 5, 2, RESERVED },
1621 { 3, 2, "DQS_CLK_IN", "Delay DQS Before Clocking Input", PRESENT_DEC, NOBITS },
1622 { 1, 2, "DQS_CLK_OUT", "Delay DQS Before Clocking Output", PRESENT_DEC, NOBITS },
1623 { BITS_EOT }
1624 }},
1625 { 0x4c000014, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_SYS_RSTPLL", "GLCP System Reset and PLL Control", {
1626 { 63, 19, RESERVED },
1627 { 44, 4, "MDIV", "GLIU1 Divisor", PRESENT_BIN, {
1628 { MSR1(0), "Divide by 2" },
1629 { MSR1(1), "Divide by 3" },
1630 { MSR1(2), "Divide by 4" },
1631 { MSR1(3), "Divide by 5" },
1632 { MSR1(4), "Divide by 6" },
1633 { MSR1(5), "Divide by 7" },
1634 { MSR1(6), "Divide by 8" },
1635 { MSR1(7), "Divide by 9" },
1636 { MSR1(8), "Divide by 10" },
1637 { MSR1(9), "Divide by 11" },
1638 { MSR1(10), "Divide by 12" },
1639 { MSR1(11), "Divide by 13" },
1640 { MSR1(12), "Divide by 14" },
1641 { MSR1(13), "Divide by 15" },
1642 { MSR1(14), "Divide by 16" },
1643 { MSR1(15), "Divide by 17" },
1644 { BITVAL_EOT }
1645 }},
1646 { 40, 3, "VDIV", "CPU Core Divisor", PRESENT_BIN, {
1647 { MSR1(0), "Divide by 2" },
1648 { MSR1(1), "Divide by 3" },
1649 { MSR1(2), "Divide by 4" },
1650 { MSR1(3), "Divide by 5" },
1651 { MSR1(4), "Divide by 6" },
1652 { MSR1(5), "Divide by 7" },
1653 { MSR1(6), "Divide by 8" },
1654 { MSR1(7), "Divide by 9" },
1655 { BITVAL_EOT }
1656 }},
1657 { 37, 6, "FBDIV", "Feedback Devisor", PRESENT_DEC, NOBITS },
1658 { 31, 6, "SWFLAGS", "Software Flags", PRESENT_BIN, NOBITS },
1659 { 25, 1, "LOCK", "PLL Lock", PRESENT_DEC, {
1660 { MSR1(1), "PLL locked" },
1661 { MSR1(0), "PLL is not locked" },
1662 { BITVAL_EOT }
1663 }},
1664 { 24, 1, "LOCKWAIT", "Lock Wait", PRESENT_DEC, {
1665 { MSR1(0), "Disable" },
1666 { MSR1(1), "Enable" },
1667 { BITVAL_EOT }
1668 }},
1669 { 23, 8, "HOLD_COUNT", "Hold Count, divided by 16", PRESENT_DEC, NOBITS },
1670 { 15, 1, "BYPASS", "PLL Bypass", PRESENT_DEC, {
1671 { MSR1(0), "Use PLL as Clocksource" },
1672 { MSR1(1), "Use DOTREF as Clocksource" },
1673 { BITVAL_EOT }
1674 }},
1675 { 14, 1, "PD", "Power Down", PRESENT_DEC, {
1676 { MSR1(0), "PLL active" },
1677 { MSR1(1), "PLL in power down mode" },
1678 { BITVAL_EOT }
1679 }},
1680 { 13, 1, "RESETPLL", "PLL Reset", PRESENT_DEC, NOBITS },
1681 { 12, 2, RESERVED },
1682 { 10, 1, "DDRMODE", "DDR Mode", PRESENT_DEC, {
1683 { MSR1(0), "DDR communication enabled" },
1684 { MSR1(1), "Reserved" },
1685 { BITVAL_EOT }
1686 }},
1687 { 9, 1, "VA_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, {
1688 { MSR1(1), "CPU does not use GLIU1 FIFO" },
1689 { MSR1(0), "The GLIU1 FIFO is used by the CPU" },
1690 { BITVAL_EOT }
1691 }},
1692 { 8, 1, "PCI_SEMI_SYNC_MODE", "Synchronous CPU Core and GLIU1", PRESENT_DEC, {
1693 { MSR1(1), "PCI does not use mb_func_clk and pci_func_clk falling edges" },
1694 { MSR1(0), "Falling edges on mb_func_clk and pci_func_clk are used by PCI" },
1695 { BITVAL_EOT }
1696 }},
1697 { 7, 1, "DSTALL", "Debug Stall", PRESENT_DEC, NOBITS },
1698 { 6, 3, "BOOTSTRAP_STAT", "Bootstrap Status", PRESENT_BIN, NOBITS },
1699 { 3, 1, "DOTPOSTDIV3", "DOTPLL Post-Divide by 3", PRESENT_DEC, NOBITS },
1700 { 2, 1, "DOTPREMULT2", "DOTPLL Pre-Multiply by 2", PRESENT_DEC, NOBITS },
1701 { 1, 1, "DOTPREDIV2", "DOTPLL Pre-Divide by 2", PRESENT_DEC, NOBITS },
1702 { 0, 1, "CHIP_RESET", "Chip Reset", PRESENT_DEC, NOBITS },
1703 { BITS_EOT }
1704 }},
1705 { MSR_EOT }
1706};