blob: 857c8cba53151b7afd55acec88a89482bed5605d [file] [log] [blame]
Marshall Dawson9df969a2017-07-25 18:46:46 -06001config SOC_AMD_COMMON_BLOCK_CAR
2 bool
Marshall Dawson9df969a2017-07-25 18:46:46 -06003 help
4 This option allows the SOC to use a standard AMD cache-as-ram (CAR)
Marshall Dawsond61e8322017-08-09 19:59:20 -06005 implementation. CAR setup is built into bootblock and teardown is
6 in postcar. The teardown procedure does not preserve the stack so
7 it may not be appropriate for a romstage implementation without
8 additional consideration. If this option is not used, the SOC must
9 implement these functions separately.
Felix Heldbefec1e2020-11-06 00:26:03 +010010 This is only used for AMD CPU before family 17h. From family 17h on
11 the RAM is already initialized by the PSP before the x86 cores are
12 released from reset.
Felix Held9065f4f2020-11-21 02:12:54 +010013
14config SOC_AMD_COMMON_BLOCK_NONCAR
15 bool
Felix Held9065f4f2020-11-21 02:12:54 +010016 help
17 From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any
18 more, since the RAM initialization is already done by the PSP when
19 the x86 cores are released from reset.
20
21if SOC_AMD_COMMON_BLOCK_NONCAR
22
Arthur Heymans4be0f4b2022-03-30 23:08:21 +020023config BOOTBLOCK_IN_CBFS
24 bool
25 default n
26
Felix Held9065f4f2020-11-21 02:12:54 +010027config MEMLAYOUT_LD_FILE
28 string
29 default "src/soc/amd/common/block/cpu/noncar/memlayout.ld"
30
Raul E Rangel55fea112021-07-23 16:43:18 -060031config CBFS_CACHE_SIZE
32 hex
33 help
34 The size of the cbfs_cache region.
35
Felix Held64942652023-03-04 03:33:54 +010036config ACPI_CPU_STRING
37 string
Felix Heldf0a8b042023-05-12 15:55:06 +020038 default "C%03d"
Felix Held64942652023-03-04 03:33:54 +010039
Felix Held9065f4f2020-11-21 02:12:54 +010040endif # SOC_AMD_COMMON_BLOCK_NONCAR
Felix Held2f5c7592020-12-04 17:31:10 +010041
Felix Held96fd62f2023-03-24 16:55:50 +010042config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H
43 bool
44 help
45 Select this option to include code to calculate the CPU frequency
46 from the P state MSR values on AMD CPU families 15h and 16h.
47
Felix Helda63f8592023-03-24 16:30:55 +010048config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
49 bool
50 help
51 Select this option to include code to calculate the CPU frequency
52 from the P state MSR values on AMD CPU families 17h and 19h.
53
54config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH
55 bool
56 help
57 Select this option to include code to calculate the CPU frequency
58 from the P state MSR values on AMD CPU family 1Ah.
59
Felix Held1e1d4902021-07-14 00:05:39 +020060config SOC_AMD_COMMON_BLOCK_MCA_COMMON
61 bool
62 help
63 Add common machine check architecture support. Do not select this
64 in the SoC's Kconfig; select either SOC_AMD_COMMON_BLOCK_MCA or
65 SOC_AMD_COMMON_BLOCK_MCAX which will select this one.
66
67config SOC_AMD_COMMON_BLOCK_MCA
68 bool
69 select SOC_AMD_COMMON_BLOCK_MCA_COMMON
70 help
71 Add IA32 machine check architecture (MCA) support for pre-Zen CPUs.
72
73config SOC_AMD_COMMON_BLOCK_MCAX
74 bool
75 select SOC_AMD_COMMON_BLOCK_MCA_COMMON
76 help
77 Add extended machine check architecture (MCAX) support for AMD family
78 17h, 19h and possibly newer CPUs.
79
Felix Heldbc134812021-02-10 02:26:10 +010080config SOC_AMD_COMMON_BLOCK_SMM
81 bool
Arthur Heymans56776a12022-05-19 11:31:10 +020082 select X86_SMM_SKIP_RELOCATION_HANDLER if HAVE_SMI_HANDLER
Felix Heldbc134812021-02-10 02:26:10 +010083 help
Felix Held746f4382021-02-16 17:42:56 +010084 Add common SMM relocation, finalization and handler functionality to
85 the build.
Felix Heldbc134812021-02-10 02:26:10 +010086
Felix Held23a398e2023-03-23 23:44:03 +010087config SOC_AMD_COMMON_BLOCK_SVI2
88 bool
89 help
90 Select this option is the SoC uses the serial VID 2 standard for
91 encoding the voltage it requests from the VRM.
92
93config SOC_AMD_COMMON_BLOCK_SVI3
94 bool
95 help
96 Select this option is the SoC uses the serial VID 3 standard for
97 encoding the voltage it requests from the VRM.
98
Felix Held60df7ca2023-03-24 20:33:15 +010099config SOC_AMD_COMMON_BLOCK_TSC
Felix Held2f5c7592020-12-04 17:31:10 +0100100 bool
Felix Held2f5c7592020-12-04 17:31:10 +0100101 select TSC_SYNC_LFENCE
102 select UDELAY_TSC
Felix Held26d54b72023-03-24 20:37:47 +0100103 select TSC_MONOTONIC_TIMER
Felix Held2f5c7592020-12-04 17:31:10 +0100104 help
105 Select this option to add the common functions for getting the TSC
Felix Held60df7ca2023-03-24 20:33:15 +0100106 frequency of AMD family 17h, 19h and 1Ah CPUs/APUs and to provide
107 TSC-based monotonic timer functionality to the build.
Raul E Rangel394c6b02021-02-12 14:37:43 -0700108
109config SOC_AMD_COMMON_BLOCK_UCODE
110 bool
Raul E Rangel394c6b02021-02-12 14:37:43 -0700111 help
112 Builds in support for loading uCode.