Jordan Crouse | 6818245 | 2007-05-03 21:36:51 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Jordan Crouse | 6818245 | 2007-05-03 21:36:51 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee> |
| 5 | * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com> |
| 6 | * Copyright (C) 2006 Stefan Reinauer <stepan@coresystems.de> |
| 7 | * Copyright (C) 2006 Andrei Birjukov <andrei.birjukov@artecdesign.ee> |
| 8 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
Jordan Crouse | 6818245 | 2007-05-03 21:36:51 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 21 | #ifndef CPU_AMD_LXDEF_H |
| 22 | #define CPU_AMD_LXDEF_H |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 23 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 24 | #define CPU_ID_1_X 0x00000560 /* Stepping ID 1.x CPUbug fix to change it to 5A0*/ |
| 25 | #define CPU_ID_2_0 0x000005A1 |
| 26 | #define CPU_ID_3_0 0x000005A2 |
| 27 | |
| 28 | #define CPU_REV_1_0 0x010 |
| 29 | #define CPU_REV_1_1 0x011 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 30 | #define CPU_REV_2_0 0x020 |
| 31 | #define CPU_REV_2_1 0x021 |
| 32 | #define CPU_REV_2_2 0x022 |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 33 | #define CPU_REV_C_0 0x030 |
| 34 | #define CPU_REV_C_1 0x031 |
| 35 | #define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/ |
| 36 | #define CPU_REV_C_3 0x033 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 37 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 38 | |
| 39 | /* MSR routing as follows*/ |
| 40 | /* MSB = 1 means not for CPU*/ |
| 41 | /* next 3 bits 1st port*/ |
| 42 | /* next3 bits next port if through an GLIU*/ |
| 43 | /* etc...*/ |
| 44 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 45 | /* GLIU0 ports */ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 46 | #define GL0_GLIU0 0 |
| 47 | #define GL0_MC 1 |
| 48 | #define GL0_GLIU1 2 |
| 49 | #define GL0_CPU 3 |
| 50 | #define GL0_VG 4 |
| 51 | #define GL0_GP 5 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 52 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 53 | /* GLIU1 ports */ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 54 | #define GL1_GLIU0 1 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 55 | #define GL1_DF 2 |
| 56 | #define GL1_GLCP 3 |
| 57 | #define GL1_PCI 4 |
| 58 | #define GL1_VIP 5 |
| 59 | #define GL1_AES 6 |
| 60 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 61 | |
Lee Leahy | f00e446 | 2017-03-07 13:17:49 -0800 | [diff] [blame^] | 62 | #define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx, To get on GeodeLink one bit has to be set */ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 63 | #define MSR_MC (GL0_MC << 29) /* 2000xxxx */ |
| 64 | #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 65 | #define MSR_CPU (GL0_CPU << 29) /* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed*/ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 66 | #define MSR_VG (GL0_VG << 29) /* 8000xxxx */ |
| 67 | #define MSR_GP (GL0_GP << 29) /* A000xxxx */ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 68 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 69 | #define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */ |
| 70 | #define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */ |
| 71 | #define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 72 | #define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ |
| 73 | #define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 74 | #define MSR_FG MSR_GLCP |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 75 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 76 | /*GeodeLink Interface Unit 0 (GLIU0) port0*/ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 77 | |
| 78 | #define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 79 | #define GLIU0_GLD_MSR_ERROR (MSR_GLIU0 + 0x2003) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 80 | #define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004) |
| 81 | |
| 82 | #define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20) |
| 83 | #define GLIU0_CAP (MSR_GLIU0 + 0x86) |
| 84 | #define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 85 | #define GLIU0_ARB (MSR_GLIU0 + 0x82) |
| 86 | #define ARB_UPPER_QUACK_EN_SET (1 << 31) |
| 87 | #define ARB_UPPER_DACK_EN_SET (1 << 28) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 88 | |
| 89 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 90 | /* Memory Controller GLIU0 port 1*/ |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 91 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 92 | #define MC_GLD_MSR_CAP (MSR_MC + 0x2000) |
| 93 | #define MC_GLD_MSR_PM (MSR_MC + 0x2004) |
| 94 | |
| 95 | #define MC_CF07_DATA (MSR_MC + 0x18) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 96 | #define CF07_UPPER_D1_SZ_SHIFT 28 |
| 97 | #define CF07_UPPER_D1_MB_SHIFT 24 |
| 98 | #define CF07_UPPER_D1_CB_SHIFT 20 |
| 99 | #define CF07_UPPER_D1_PSZ_SHIFT 16 |
| 100 | #define CF07_UPPER_D0_SZ_SHIFT 12 |
| 101 | #define CF07_UPPER_D0_MB_SHIFT 8 |
| 102 | #define CF07_UPPER_D0_CB_SHIFT 4 |
| 103 | #define CF07_UPPER_D0_PSZ_SHIFT 0 |
| 104 | |
| 105 | #define CF07_LOWER_REF_INT_SHIFT 8 |
| 106 | #define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28) |
| 107 | #define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27) |
| 108 | #define CF07_LOWER_EMR_QFC_SET (1 << 26) |
| 109 | #define CF07_LOWER_EMR_DRV_SET (1 << 25) |
| 110 | #define CF07_LOWER_REF_TEST_SET (1 << 3) |
| 111 | #define CF07_LOWER_PROG_DRAM_SET (1 << 0) |
| 112 | |
| 113 | |
| 114 | #define MC_CF8F_DATA (MSR_MC + 0x19) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 115 | #define CF8F_UPPER_XOR_BS_SHIFT 19 |
| 116 | #define CF8F_UPPER_XOR_MB0_SHIFT 18 |
| 117 | #define CF8F_UPPER_XOR_BA1_SHIFT 17 |
| 118 | #define CF8F_UPPER_XOR_BA0_SHIFT 16 |
| 119 | #define CF8F_UPPER_REORDER_DIS_SET (1 << 8) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 120 | #define CF8F_LOWER_CAS_LAT_SHIFT 28 |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 121 | #define CF8F_LOWER_ACT2ACTREF_SHIFT 24 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 122 | #define CF8F_LOWER_ACT2PRE_SHIFT 20 |
| 123 | #define CF8F_LOWER_PRE2ACT_SHIFT 16 |
| 124 | #define CF8F_LOWER_ACT2CMD_SHIFT 12 |
| 125 | #define CF8F_LOWER_ACT2ACT_SHIFT 8 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 126 | #define CF8F_UPPER_HOI_LOI_SET (1 << 1) |
| 127 | |
| 128 | #define MC_CF1017_DATA (MSR_MC + 0x1A) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 129 | #define CF1017_LOWER_WR_TO_RD_SHIFT 28 |
| 130 | #define CF1017_LOWER_RD_TMG_CTL_SHIFT 24 |
| 131 | #define CF1017_LOWER_REF2ACT_SHIFT 16 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 132 | #define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8) |
| 133 | #define CF1017_LOWER_WR2DAT_SHIFT 0 |
| 134 | |
| 135 | #define MC_CFCLK_DBUG (MSR_MC + 0x1D) |
| 136 | |
| 137 | #define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 138 | #define CFCLK_UPPER_MTST_RBEX_EN_SET (1 << 1) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 139 | #define CFCLK_UPPER_MTEST_EN_SET (1 << 0) |
| 140 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 141 | #define CFCLK_LOWER_FORCE_PRE_SET (1 << 16) |
| 142 | #define CFCLK_LOWER_TRISTATE_DIS_SET (1 << 12) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 143 | #define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9) |
| 144 | #define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8) |
| 145 | #define CFCLK_LOWER_SDCLK_SET (0x0F << 0) |
| 146 | |
| 147 | #define MC_CF_RDSYNC (MSR_MC + 0x1F) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 148 | #define MC_CF_PMCTR (MSR_MC + 0x20) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 149 | |
| 150 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 151 | /* GLIU1 GLIU0 port2*/ |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 152 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 153 | #define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 154 | #define GLIU1_GLD_MSR_ERROR (MSR_GLIU1 + 0x2003) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 155 | #define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004) |
| 156 | |
| 157 | #define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 158 | #define GLIU1_PORT_ACTIVE (MSR_GLIU1 + 0x81) |
| 159 | #define GLIU1_ARB (MSR_GLIU1 + 0x82) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 160 | |
| 161 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 162 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 163 | /* CPU ; does not need routing instructions since we are executing there.*/ |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 164 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 165 | #define CPU_GLD_MSR_CAP 0x2000 |
| 166 | #define CPU_GLD_MSR_CONFIG 0x2001 |
| 167 | #define CPU_GLD_MSR_PM 0x2004 |
| 168 | |
| 169 | #define CPU_GLD_MSR_DIAG 0x2005 |
| 170 | #define DIAG_SEL1_MODE_SHIFT 16 |
| 171 | #define DIAG_SEL1_SET (1 << 31) |
| 172 | #define DIAG_SEL0__MODE_SHIFT 0 |
| 173 | #define DIAG_SET0_SET (1 << 15) |
| 174 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 175 | #define CPU_PF_CONF 0x1100 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 176 | #define RETURN_STACK_ENABLE_SET (1 << 4) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 177 | #define PF_CONF_CC_L1 (1 << 0) |
| 178 | #define CPU_PF_INVD 0x1102 |
| 179 | #define PF_RS_INVD_SET (1 << 1) |
| 180 | #define PF_CC_INVD_SET (1 << 0) |
| 181 | #define CPU_PF_BIST 0x1140 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 182 | |
| 183 | #define CPU_XC_CONFIG 0x1210 |
| 184 | #define XC_CONFIG_SUSP_ON_HLT (1 << 0) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 185 | #define XC_CONFIG_SUSP_ON_PAUSE (1 << 1) |
| 186 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 187 | #define CPU_ID_CONFIG 0x1250 |
| 188 | #define ID_CONFIG_SERIAL_SET (1 << 0) |
| 189 | |
| 190 | #define CPU_AC_MSR 0x1301 |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 191 | |
| 192 | /* SMM*/ |
| 193 | #define CPU_AC_SMM_CTL 0x1301 |
| 194 | #define SMM_NMI_EN_SET (1 << 0) |
| 195 | #define SMM_SUSP_EN_SET (1 << 1) |
| 196 | #define NEST_SMI_EN_SET (1 << 2) |
| 197 | #define SMM_INST_EN_SET (1 << 3) |
| 198 | #define INTL_SMI_EN_SET (1 << 4) |
| 199 | #define EXTL_SMI_EN_SET (1 << 5) |
| 200 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 201 | #define CPU_EX_BIST 0x1428 |
| 202 | |
| 203 | /*IM*/ |
| 204 | #define CPU_IM_CONFIG 0x1700 |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 205 | #define IM_CONFIG_LOWER_SERIAL_SET (1 << 2) |
| 206 | #define IM_CONFIG_LOWER_L0WE_SET (1 << 6) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 207 | #define IM_CONFIG_LOWER_ICD_SET (1 << 8) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 208 | #define IM_CONFIG_LOWER_EBE_SET (1 << 10) |
| 209 | #define IM_CONFIG_LOWER_ABSE_SET (1 << 11) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 210 | #define IM_CONFIG_LOWER_QWT_SET (1 << 20) |
| 211 | #define CPU_IC_INDEX 0x1710 |
| 212 | #define CPU_IC_DATA 0x1711 |
| 213 | #define CPU_IC_TAG 0x1712 |
| 214 | #define CPU_IC_TAG_I 0x1713 |
| 215 | #define CPU_ITB_INDEX 0x1720 |
| 216 | #define CPU_ITB_LRU 0x1721 |
| 217 | #define CPU_ITB_ENTRY 0x1722 |
| 218 | #define CPU_ITB_ENTRY_I 0x1723 |
| 219 | #define CPU_IM_BIST_TAG 0x1730 |
| 220 | #define CPU_IM_BIST_DATA 0x1731 |
| 221 | |
| 222 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 223 | /*DM MSR MAP*/ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 224 | #define CPU_DM_CONFIG0 0x1800 |
| 225 | #define DM_CONFIG0_UPPER_WSREQ_SHIFT 12 |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 226 | #define DM_CONFIG0_LOWER_EVCTONRPL_SET (1 << 14) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 227 | #define DM_CONFIG0_LOWER_WBINVD_SET (1<<5) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 228 | #define DM_CONFIG0_LOWER_DCDIS_SET (1 << 8) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 229 | #define DM_CONFIG0_LOWER_MISSER_SET (1<<1) |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 230 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 231 | #define CPU_RCONF_DEFAULT 0x1808 |
| 232 | #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 |
| 233 | #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 |
| 234 | #define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0 |
| 235 | #define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28 |
| 236 | #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 |
| 237 | #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 |
| 238 | |
| 239 | #define CPU_RCONF_BYPASS 0x180A |
| 240 | #define CPU_RCONF_A0_BF 0x180B |
| 241 | #define CPU_RCONF_C0_DF 0x180C |
| 242 | #define CPU_RCONF_E0_FF 0x180D |
| 243 | |
| 244 | #define CPU_RCONF_SMM 0x180E |
| 245 | #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 |
| 246 | #define RCONF_SMM_UPPER_RCSMM_SHIFT 0 |
| 247 | #define RCONF_SMM_LOWER_SMMBASE_SHIFT 12 |
| 248 | #define RCONF_SMM_LOWER_RCNORM_SHIFT 0 |
| 249 | #define RCONF_SMM_LOWER_EN_SET (1<<8) |
| 250 | |
| 251 | #define CPU_RCONF_DMM 0x180F |
| 252 | #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 |
| 253 | #define RCONF_DMM_UPPER_RCDMM_SHIFT 0 |
| 254 | #define RCONF_DMM_LOWER_DMMBASE_SHIFT 12 |
| 255 | #define RCONF_DMM_LOWER_RCNORM_SHIFT 0 |
| 256 | #define RCONF_DMM_LOWER_EN_SET (1<<8) |
| 257 | |
| 258 | #define CPU_RCONF0 0x1810 |
| 259 | #define CPU_RCONF1 0x1811 |
| 260 | #define CPU_RCONF2 0x1812 |
| 261 | #define CPU_RCONF3 0x1813 |
| 262 | #define CPU_RCONF4 0x1814 |
| 263 | #define CPU_RCONF5 0x1815 |
| 264 | #define CPU_RCONF6 0x1816 |
| 265 | #define CPU_RCONF7 0x1817 |
| 266 | #define CPU_CR1_MSR 0x1881 |
| 267 | #define CPU_CR2_MSR 0x1882 |
| 268 | #define CPU_CR3_MSR 0x1883 |
| 269 | #define CPU_CR4_MSR 0x1884 |
| 270 | #define CPU_DC_INDEX 0x1890 |
| 271 | #define CPU_DC_DATA 0x1891 |
| 272 | #define CPU_DC_TAG 0x1892 |
| 273 | #define CPU_DC_TAG_I 0x1893 |
| 274 | #define CPU_SNOOP 0x1894 |
| 275 | #define CPU_DTB_INDEX 0x1898 |
| 276 | #define CPU_DTB_LRU 0x1899 |
| 277 | #define CPU_DTB_ENTRY 0x189A |
| 278 | #define CPU_DTB_ENTRY_I 0x189B |
| 279 | #define CPU_L2TB_INDEX 0x189C |
| 280 | #define CPU_L2TB_LRU 0x189D |
| 281 | #define CPU_L2TB_ENTRY 0x189E |
| 282 | #define CPU_L2TB_ENTRY_I 0x189F |
| 283 | #define CPU_DM_BIST 0x18C0 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 284 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 285 | #define CPU_BC_CONF_0 0x1900 |
| 286 | #define TSC_SUSP_SET (1<<5) |
| 287 | #define SUSP_EN_SET (1<<12) |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 288 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 289 | #define CPU_BC_CONF_1 0x1901 |
| 290 | #define CPU_BC_MSR_LOCK 0x1908 |
| 291 | #define CPU_BC_L2_CONF 0x1920 |
| 292 | #define BC_L2_ENABLE_SET (1 << 0) |
| 293 | #define BC_L2_ALLOC_ENABLE_SET (1 << 1) |
| 294 | #define BC_L2_DM_ALLOC_ENABLE_SET (1 << 2) |
| 295 | #define BC_L2_IM_ALLOC_ENABLE_SET (1 << 3) |
| 296 | #define BC_L2_INVALIDATE_SET (1 << 4) |
| 297 | #define CPU_BC_L2_STATUS 0x1921 |
| 298 | #define CPU_BC_L2_INDEX 0x1922 |
| 299 | #define CPU_BC_L2_DATA 0x1923 |
| 300 | #define CPU_BC_L2_TAG 0x1924 |
| 301 | #define CPU_BC_L2_TAG_AUTOINC 0x1925 |
| 302 | #define CPU_BC_L2_BIST 0x1926 |
| 303 | #define BC_L2_BIST_TAG_ENABLE_SET (1 << 0) |
| 304 | #define BC_L2_BIST_TAG_DRT_EN_SET (1 << 1) |
| 305 | #define BC_L2_BIST_DATA_ENABLE_SET (1 << 2) |
| 306 | #define BC_L2_BIST_DATA_DRT_EN_SET (1 << 3) |
| 307 | #define BC_L2_BIST_MRU_ENABLE_SET (1 << 4) |
| 308 | #define BC_L2_BIST_MRU_DRT_EN_SET (1 << 5) |
| 309 | #define CPU_BC_PMODE_MSR 0x1930 |
| 310 | #define CPU_BC_MSS_ARRAY_CTL_ENA 0x1980 |
| 311 | #define CPU_BC_MSS_ARRAY_CTL0 0x1981 |
| 312 | #define CPU_BC_MSS_ARRAY_CTL1 0x1982 |
| 313 | #define CPU_BC_MSS_ARRAY_CTL2 0x1983 |
Indrek Kruusa | f4c0b59 | 2006-08-02 11:30:32 +0000 | [diff] [blame] | 314 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 315 | #define CPU_FPU_MSR_MODE 0x1A00 |
| 316 | #define FPU_IE_SET (1 << 0) |
Indrek Kruusa | f4c0b59 | 2006-08-02 11:30:32 +0000 | [diff] [blame] | 317 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 318 | #define CPU_FP_UROM_BIST 0x1A03 |
Indrek Kruusa | f4c0b59 | 2006-08-02 11:30:32 +0000 | [diff] [blame] | 319 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 320 | #define CPU_CPUID0 0x3000 |
| 321 | #define CPU_CPUID1 0x3001 |
| 322 | #define CPU_CPUID2 0x3002 |
| 323 | #define CPU_CPUID3 0x3003 |
| 324 | #define CPU_CPUID4 0x3004 |
| 325 | #define CPU_CPUID5 0x3005 |
| 326 | #define CPU_CPUID6 0x3006 |
| 327 | #define CPU_CPUID7 0x3007 |
| 328 | #define CPU_CPUID8 0x3008 |
| 329 | #define CPU_CPUID9 0x3009 |
| 330 | #define CPU_CPUIDA 0x300A |
| 331 | #define CPU_CPUIDB 0x300B |
| 332 | #define CPU_CPUIDC 0x300C |
| 333 | #define CPU_CPUIDD 0x300D |
| 334 | #define CPU_CPUIDE 0x300E |
| 335 | #define CPU_CPUIDF 0x300F |
| 336 | #define CPU_CPUID10 0x3010 |
| 337 | #define CPU_CPUID11 0x3011 |
| 338 | #define CPU_CPUID12 0x3012 |
| 339 | #define CPU_CPUID13 0x3013 |
Indrek Kruusa | f4c0b59 | 2006-08-02 11:30:32 +0000 | [diff] [blame] | 340 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 341 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 342 | |
| 343 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 344 | /* VG GLIU0 port4*/ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 345 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 346 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 347 | #define VG_GLD_MSR_CAP (MSR_VG + 0x2000) |
| 348 | #define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001) |
| 349 | #define VG_GLD_MSR_PM (MSR_VG + 0x2004) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 350 | #define VG_BIST (MSR_VG + 0x2010) |
| 351 | |
| 352 | |
| 353 | |
| 354 | /* GP GLIU0 port5*/ |
| 355 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 356 | |
| 357 | #define GP_GLD_MSR_CAP (MSR_GP + 0x2000) |
| 358 | #define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001) |
| 359 | #define GP_GLD_MSR_PM (MSR_GP + 0x2004) |
| 360 | |
| 361 | |
| 362 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 363 | /* DF GLIU0 port6*/ |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 364 | |
| 365 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 366 | #define DF_GLD_MSR_CAP (MSR_DF + 0x2000) |
| 367 | #define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001) |
| 368 | #define DF_LOWER_LCD_SHIFT 6 |
| 369 | #define DF_GLD_MSR_PM (MSR_DF + 0x2004) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 370 | #define DF_BIST (MSR_DF + 0x2005) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 371 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 372 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 373 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 374 | /* GeodeLink Control Processor GLIU1 port3*/ |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 375 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 376 | #define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000) |
| 377 | #define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 378 | #define GLCP_GLD_MSR_SMI (MSR_GLCP + 0x2002) |
| 379 | #define GLCP_GLD_MSR_ERROR (MSR_GLCP + 0x2003) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 380 | #define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004) |
| 381 | |
| 382 | #define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 383 | #define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14) /* R/W */ |
| 384 | #define RSTPLL_UPPER_GLMULT_SHIFT 7 |
| 385 | #define RSTPLL_UPPER_GLDIV_SHIFT 6 |
| 386 | #define RSTPLL_UPPER_CPUMULT_SHIFT 1 |
| 387 | #define RSTPLL_UPPER_CPUDIV_SHIFT 0 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 388 | #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 389 | #define RSTPLL_LOWER_SWFLAGS_MASK (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 390 | #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 391 | #define RSTPPL_LOWER_COREBYPASS_SHIFT 12 |
| 392 | #define RSTPPL_LOWER_GLBYPASS_SHIFT 11 |
| 393 | #define RSTPPL_LOWER_PCISPEED_SHIFT 7 |
| 394 | #define RSTPPL_LOWER_BOOTSTRAP_SHIFT 1 |
| 395 | #define RSTPLL_LOWER_BOOTSTRAP_MASK (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 396 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 397 | #define RSTPPL_LOWER_GLLOCK_SET (1 << 25) |
| 398 | #define RSTPPL_LOWER_CORELOCK_SET (1 << 24) |
| 399 | #define RSTPPL_LOWER_LOCKWAIT_SET (1 << 15) |
| 400 | #define RSTPPL_LOWER_CLPD_SET (1 << 14) |
| 401 | #define RSTPPL_LOWER_COREPD_SET (1 << 13) |
| 402 | #define RSTPPL_LOWER_MBBYPASS_SET (1 << 12) |
| 403 | #define RSTPPL_LOWER_COREBYPASS_SET (1 << 11) |
| 404 | #define RSTPPL_LOWER_LPFEN_SET (1 << 10) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 405 | #define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9) |
| 406 | #define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8) |
| 407 | #define RSTPPL_LOWER_CHIP_RESET_SET (1<<0) |
| 408 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 409 | #define GLCP_DOWSER (MSR_GLCP + 0x0E) |
| 410 | #define GLCP_DBGCLKCTL (MSR_GLCP + 0x16) |
| 411 | #define GLCP_REVID (MSR_GLCP + 0x17) |
| 412 | #define GLCP_TH_OD (MSR_GLCP + 0x1E) |
| 413 | #define GLCP_FIFOCTL (MSR_GLCP + 0x5E) |
| 414 | #define GLCP_BIST GLCP_FIFOCTL |
| 415 | |
| 416 | #define MSR_INIT (MSR_GLCP + 0x33) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 417 | |
| 418 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 419 | /* GLIU1 port 4*/ |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 420 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 421 | #define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000) |
| 422 | #define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001) |
| 423 | #define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004) |
| 424 | |
| 425 | #define GLPCI_CTRL (MSR_PCI + 0x2010) |
| 426 | #define GLPCI_CTRL_UPPER_FTH_SHIFT 28 |
| 427 | #define GLPCI_CTRL_UPPER_RTH_SHIFT 24 |
| 428 | #define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20 |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 429 | #define GLPCI_CTRL_UPPER_RTL_SHIFT 17 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 430 | #define GLPCI_CTRL_UPPER_DTL_SHIFT 14 |
| 431 | #define GLPCI_CTRL_UPPER_WTO_SHIFT 11 |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 432 | #define GLPCI_CTRL_UPPER_SLTO_SHIFT 10 |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 433 | #define GLPCI_CTRL_UPPER_ILTO_SHIFT 8 |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 434 | #define GLPCI_CTRL_UPPER_LAT_SHIFT 3 |
| 435 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 436 | #define GLPCI_CTRL_LOWER_IRFT_SHIFT 18 |
| 437 | #define GLPCI_CTRL_LOWER_IRFC_SHIFT 16 |
| 438 | #define GLPCI_CTRL_LOWER_ER_SET (1<<11) |
| 439 | #define GLPCI_CTRL_LOWER_LDE_SET (1<<9) |
| 440 | #define GLPCI_CTRL_LOWER_OWC_SET (1<<4) |
| 441 | #define GLPCI_CTRL_LOWER_IWC_SET (1<<3) |
| 442 | #define GLPCI_CTRL_LOWER_PCD_SET (1<<2) |
| 443 | #define GLPCI_CTRL_LOWER_ME_SET (1<<0) |
| 444 | |
| 445 | #define GLPCI_ARB (MSR_PCI + 0x2011) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 446 | #define GLPCI_ARB_UPPER_CR_SHIFT 28 |
| 447 | #define GLPCI_ARB_UPPER_R2_SHIFT 24 |
| 448 | #define GLPCI_ARB_UPPER_R1_SHIFT 20 |
| 449 | #define GLPCI_ARB_UPPER_R0_SHIFT 16 |
| 450 | #define GLPCI_ARB_UPPER_CH_SHIFT 12 |
| 451 | #define GLPCI_ARB_UPPER_H2_SHIFT 8 |
| 452 | #define GLPCI_ARB_UPPER_H1_SHIFT 4 |
| 453 | #define GLPCI_ARB_UPPER_H0_SHIFT 0 |
| 454 | |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 455 | #define GLPCI_ARB_LOWER_COV_SET (1<<23) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 456 | #define GLPCI_ARB_LOWER_VO2_SET (1 << 22) |
| 457 | #define GLPCI_ARB_LOWER_OV1_SET (1 << 21) |
| 458 | #define GLPCI_ARB_LOWER_OV0_SET (1 << 20) |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 459 | #define GLPCI_ARB_LOWER_MSK2_SET (1<<18) |
| 460 | #define GLPCI_ARB_LOWER_MSK1_SET (1<<17) |
| 461 | #define GLPCI_ARB_LOWER_MSK0_SET (1<<16) |
| 462 | #define GLPCI_ARB_LOWER_CPRE_SET (1<<11) |
| 463 | #define GLPCI_ARB_LOWER_PRE2_SET (1<<10) |
| 464 | #define GLPCI_ARB_LOWER_PRE1_SET (1<<9) |
| 465 | #define GLPCI_ARB_LOWER_PRE0_SET (1<<8) |
| 466 | #define GLPCI_ARB_LOWER_BM1_SET (1<<7) |
| 467 | #define GLPCI_ARB_LOWER_BM0_SET (1<<6) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 468 | #define GLPCI_ARB_LOWER_EA_SET (1 << 2) |
| 469 | #define GLPCI_ARB_LOWER_BMD_SET (1 << 1) |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 470 | #define GLPCI_ARB_LOWER_PARK_SET (1<<0) |
| 471 | |
| 472 | #define GLPCI_REN (MSR_PCI + 0x2014) |
| 473 | #define GLPCI_A0_BF (MSR_PCI + 0x2015) |
| 474 | #define GLPCI_C0_DF (MSR_PCI + 0x2016) |
| 475 | #define GLPCI_E0_FF (MSR_PCI + 0x2017) |
| 476 | #define GLPCI_RC0 (MSR_PCI + 0x2018) |
| 477 | #define GLPCI_RC1 (MSR_PCI + 0x2019) |
| 478 | #define GLPCI_RC2 (MSR_PCI + 0x201A) |
| 479 | #define GLPCI_RC3 (MSR_PCI + 0x201B) |
| 480 | #define GLPCI_RC4 (MSR_PCI + 0x201C) |
| 481 | #define GLPCI_RC_UPPER_TOP_SHIFT 12 |
| 482 | #define GLPCI_RC_LOWER_BASE_SHIFT 12 |
| 483 | #define GLPCI_RC_LOWER_EN_SET (1<<8) |
| 484 | #define GLPCI_RC_LOWER_PF_SET (1<<5) |
| 485 | #define GLPCI_RC_LOWER_WC_SET (1<<4) |
| 486 | #define GLPCI_RC_LOWER_WP_SET (1<<2) |
| 487 | #define GLPCI_RC_LOWER_CD_SET (1<<0) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 488 | |
| 489 | #define GLPCI_ExtMSR (MSR_PCI + 0x201E) |
| 490 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 491 | #define GLPCI_SPARE (MSR_PCI + 0x201F) |
| 492 | #define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) |
| 493 | #define GLPCI_SPARE_LOWER_PPD_SET (1<<5) |
| 494 | #define GLPCI_SPARE_LOWER_PPC_SET (1<<4) |
| 495 | #define GLPCI_SPARE_LOWER_MPC_SET (1<<3) |
| 496 | #define GLPCI_SPARE_LOWER_MME_SET (1<<2) |
| 497 | #define GLPCI_SPARE_LOWER_NSE_SET (1<<1) |
| 498 | #define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) |
| 499 | |
| 500 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 501 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 502 | /* VIP GLIU1 port 5*/ |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 503 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 504 | #define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000) |
| 505 | #define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001) |
| 506 | #define VIP_GLD_MSR_PM (MSR_VIP + 0x2004) |
| 507 | #define VIP_BIST (MSR_VIP + 0x2005) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 508 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 509 | /* AES GLIU1 port 6*/ |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 510 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 511 | #define AES_GLD_MSR_CAP (MSR_AES + 0x2000) |
| 512 | #define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001) |
| 513 | #define AES_GLD_MSR_PM (MSR_AES + 0x2004) |
| 514 | #define AES_CONTROL (MSR_AES + 0x2006) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 515 | |
| 516 | |
| 517 | /* from MC spec */ |
| 518 | #define MIN_MOD_BANKS 1 |
| 519 | #define MAX_MOD_BANKS 2 |
| 520 | #define MIN_DEV_BANKS 2 |
| 521 | #define MAX_DEV_BANKS 4 |
| 522 | #define MAX_COL_ADDR 17 |
| 523 | |
| 524 | /* GLIU typedefs */ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 525 | #define BM 1 /* Base Mask - map power of 2 size aligned region*/ |
| 526 | #define BMO 2 /* BM with an offset*/ |
| 527 | #define R 3 /* Range - 4k range minimum*/ |
| 528 | #define RO 4 /* R with offset*/ |
| 529 | #define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/ |
| 530 | #define BMIO 6 /* Base Mask IO*/ |
| 531 | #define SCIO 7 /* Swiss 0xCeese IO*/ |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 532 | #define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU*/ |
| 533 | #define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU*/ |
| 534 | #define BMO_SMM 10 /* Special marker for SMM*/ |
| 535 | #define BM_SMM 11 /* Special marker for SMM*/ |
| 536 | #define BMO_DMM 12 /* Special marker for DMM*/ |
| 537 | #define BM_DMM 13 /* Special marker for DMM*/ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 538 | #define RO_FB 14 /* special for Frame buffer.*/ |
| 539 | #define R_FB 15 /* special for FB.*/ |
| 540 | #define OTHER 0x0FE /* Special marker for other*/ |
| 541 | #define GL_END 0x0FF /* end*/ |
| 542 | |
| 543 | #define MSR_GL0 (GL1_GLIU0 << 29) |
| 544 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 545 | |
| 546 | /* Platform stuff but unlikely to change */ |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 547 | /* Set up desc addresses from 20 - 3f*/ |
| 548 | /* This is chip specific!*/ |
| 549 | #define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/ |
| 550 | #define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/ |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 551 | #define MSR_GLIU0_BASE3 (MSR_GLIU0 + 0x22) /* BM*/ |
| 552 | #define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* BM*/ |
| 553 | #define MSR_GLIU0_BASE5 (MSR_GLIU0 + 0x24) /* BM*/ |
| 554 | #define MSR_GLIU0_BASE6 (MSR_GLIU0 + 0x25) /* BM*/ |
| 555 | |
| 556 | #define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26) |
| 557 | #define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27) |
| 558 | |
| 559 | #define MSR_GLIU0_SMM (GLIU0_P2D_BMO_0) |
| 560 | #define MSR_GLIU0_DMM (GLIU0_P2D_BMO_1) |
| 561 | |
| 562 | #define GLIU0_P2D_R (MSR_GLIU0 + 0x28) |
| 563 | #define MSR_GLIU0_SYSMEM (GLIU0_P2D_R) |
| 564 | |
| 565 | #define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29) |
| 566 | #define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A) |
| 567 | #define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B) |
| 568 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 569 | #define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/ |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 570 | |
| 571 | #define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0) |
| 572 | #define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1) |
| 573 | #define GLIU0_IOD_BM_2 (MSR_GLIU0 + 0xE2) |
| 574 | |
| 575 | #define GLIU0_IOD_SC_0 (MSR_GLIU0 + 0xE3) |
| 576 | #define GLIU0_IOD_SC_1 (MSR_GLIU0 + 0xE4) |
| 577 | #define GLIU0_IOD_SC_2 (MSR_GLIU0 + 0xE5) |
| 578 | #define GLIU0_IOD_SC_3 (MSR_GLIU0 + 0xE6) |
| 579 | #define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7) |
| 580 | #define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8) |
| 581 | |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 582 | |
| 583 | #define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM*/ |
| 584 | #define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM*/ |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 585 | #define MSR_GLIU1_BASE3 (MSR_GLIU1 + 0x22) /* BM*/ |
| 586 | #define MSR_GLIU1_BASE4 (MSR_GLIU1 + 0x23) /* BM*/ |
| 587 | #define MSR_GLIU1_BASE5 (MSR_GLIU1 + 0x24) /* BM*/ |
| 588 | #define MSR_GLIU1_BASE6 (MSR_GLIU1 + 0x25) /* BM*/ |
| 589 | #define MSR_GLIU1_BASE7 (MSR_GLIU1 + 0x26) /* BM*/ |
| 590 | #define MSR_GLIU1_BASE8 (MSR_GLIU1 + 0x27) /* BM*/ |
| 591 | #define MSR_GLIU1_BASE9 (MSR_GLIU1 + 0x28) /* BM*/ |
| 592 | #define MSR_GLIU1_BASE10 (MSR_GLIU1 + 0x29) /* BM*/ |
| 593 | |
| 594 | #define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x2A) |
| 595 | #define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2B) |
| 596 | #define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2C) |
| 597 | #define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2D) |
| 598 | |
| 599 | |
| 600 | #define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2E) |
| 601 | |
| 602 | #define MSR_GLIU1_SYSMEM (GLIU1_P2D_R_0) |
| 603 | |
| 604 | #define MSR_GLIU1_SMM (MSR_GLIU1_BASE4) /* BM*/ |
| 605 | #define MSR_GLIU1_DMM (MSR_GLIU1_BASE5) /* BM*/ |
| 606 | |
| 607 | #define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0) |
| 608 | #define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1) |
| 609 | #define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2) |
| 610 | |
| 611 | #define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3) |
| 612 | #define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4) |
| 613 | #define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5) |
| 614 | #define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6) |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 615 | #define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/ |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 616 | |
| 617 | /* ------------------------ */ |
| 618 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 619 | #define SMM_OFFSET 0x80400000 /* above 2GB */ |
| 620 | #define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */ |
Indrek Kruusa | 7d94412 | 2006-09-13 21:59:09 +0000 | [diff] [blame] | 621 | |
Edwin Beasant | f333ba0 | 2010-06-10 15:24:57 +0000 | [diff] [blame] | 622 | /* DRAM_TERMINATED affects how the DELAY register is set. */ |
| 623 | #define DRAM_TERMINATED 'T' |
| 624 | #define DRAM_UNTERMINATED 't' |
| 625 | /* Bitfield definitions for the DELAY register */ |
| 626 | #define DELAY_UPPER_DISABLE_CLK135 (1 << 23) |
| 627 | #define DELAY_LOWER_STATUS_MASK 0x7C0 |
| 628 | |
Stefan Reinauer | 3f5f6d8 | 2013-05-07 20:35:29 +0200 | [diff] [blame] | 629 | #if !defined(__ASSEMBLER__) |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 630 | #if defined(__PRE_RAM__) |
Edwin Beasant | f333ba0 | 2010-06-10 15:24:57 +0000 | [diff] [blame] | 631 | void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated); |
Stefan Reinauer | 9839cbd | 2010-04-21 20:06:10 +0000 | [diff] [blame] | 632 | void SystemPreInit(void); |
| 633 | #endif |
| 634 | void cpubug(void); |
| 635 | #endif |
Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame] | 636 | |
Marc Jones | bc8176c | 2007-05-04 18:24:55 +0000 | [diff] [blame] | 637 | #endif |