Ron Minnich | 5e9dc23 | 2006-07-28 16:06:16 +0000 | [diff] [blame^] | 1 | #ifndef CPU_AMD_LXDEF_H |
| 2 | #define CPU_AMD_LXDEF_H |
| 3 | #define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/ |
| 4 | #define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/ |
| 5 | #define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/ |
| 6 | #define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/ |
| 7 | |
| 8 | #define CPU_REV_1_0 0x011 |
| 9 | #define CPU_REV_1_1 0x012 |
| 10 | #define CPU_REV_1_2 0x013 |
| 11 | #define CPU_REV_1_3 0x014 |
| 12 | #define CPU_REV_2_0 0x020 |
| 13 | #define CPU_REV_2_1 0x021 |
| 14 | #define CPU_REV_2_2 0x022 |
| 15 | #define CPU_REV_3_0 0x030 |
| 16 | /* GeodeLink Control Processor Registers, GLIU1, Port 3 */ |
| 17 | #define GLCP_CLK_DIS_DELAY 0x4c000008 |
| 18 | #define GLCP_PMCLKDISABLE 0x4c000009 |
| 19 | #define GLCP_CHIP_REVID 0x4c000017 |
| 20 | |
| 21 | /* GLCP_SYS_RSTPLL, Upper 32 bits */ |
| 22 | #define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 |
| 23 | #define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 |
| 24 | #define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 |
| 25 | |
| 26 | /* GLCP_SYS_RSTPLL, Lower 32 bits */ |
| 27 | #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 |
| 28 | #define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) |
| 29 | |
| 30 | #define GLCP_SYS_RSTPLL_LOCKWAIT 24 |
| 31 | #define GLCP_SYS_RSTPLL_HOLDCOUNT 16 |
| 32 | #define GLCP_SYS_RSTPLL_BYPASS 15 |
| 33 | #define GLCP_SYS_RSTPLL_PD 14 |
| 34 | #define GLCP_SYS_RSTPLL_RESETPLL 13 |
| 35 | #define GLCP_SYS_RSTPLL_DDRMODE 10 |
| 36 | #define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 |
| 37 | #define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 |
| 38 | #define GLCP_SYS_RSTPLL_CHIP_RESET 0 |
| 39 | |
| 40 | /* MSR routing as follows*/ |
| 41 | /* MSB = 1 means not for CPU*/ |
| 42 | /* next 3 bits 1st port*/ |
| 43 | /* next3 bits next port if through an GLIU*/ |
| 44 | /* etc...*/ |
| 45 | |
| 46 | /*Redcloud as follows.*/ |
| 47 | /* GLIU0*/ |
| 48 | /* port0 - GLIU0*/ |
| 49 | /* port1 - MC*/ |
| 50 | /* port2 - GLIU1*/ |
| 51 | /* port3 - CPU*/ |
| 52 | /* port4 - VG*/ |
| 53 | /* port5 - GP*/ |
| 54 | /* port6 - DF*/ |
| 55 | |
| 56 | /* GLIU1*/ |
| 57 | /* port1 - GLIU0*/ |
| 58 | /* port3 - GLCP*/ |
| 59 | /* port4 - PCI*/ |
| 60 | /* port5 - FG*/ |
| 61 | |
| 62 | |
| 63 | /* start GX3 def, differences are marked with GX3 comment */ |
| 64 | |
| 65 | #define GL0_GLIU0 0 |
| 66 | #define GL0_MC 1 |
| 67 | #define GL0_GLIU1 2 |
| 68 | #define GL0_CPU 3 |
| 69 | #define GL0_VG 4 |
| 70 | #define GL0_GP 5 |
| 71 | //#define GL0_DF 6 //GX3 no such thing as VP port |
| 72 | |
| 73 | #define GL1_GLIU0 1 |
| 74 | //GX3 VP port |
| 75 | #define GL1_DF 2 |
| 76 | #define GL1_GLCP 3 |
| 77 | #define GL1_PCI 4 |
| 78 | #define GL1_VIP 5 |
| 79 | #define GL1_AES 6 |
| 80 | |
| 81 | #define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */ |
| 82 | #define MSR_MC (GL0_MC << 29) /* 2000xxxx */ |
| 83 | #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ |
| 84 | #define MSR_CPU (GL0_CPU << 32) /* 0000xxxx - this is not used for BIOS */ //GX3 |
| 85 | #define MSR_VG (GL0_VG << 29) /* 8000xxxx */ |
| 86 | #define MSR_GP (GL0_GP << 29) /* A000xxxx */ |
| 87 | //#define MSR_DF (GL0_DF << 29) /* C000xxxx */ //GX3 no such thing |
| 88 | |
| 89 | #define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */ |
| 90 | #define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */ |
| 91 | //#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */ //GX3: no such thing |
| 92 | #define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ |
| 93 | #define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ |
| 94 | /* South Bridge*/ |
| 95 | #define SB_PORT 2 /* port of the SouthBridge */ |
| 96 | #define MSR_SB ((SB_PORT << 23) + MSR_PCI) /* 5100xxxx - address to the SouthBridge*/ |
| 97 | #define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/ |
| 98 | |
| 99 | |
| 100 | /**/ |
| 101 | /*GeodeLink Interface Unit 0 (GLIU0) port0*/ |
| 102 | /**/ |
| 103 | |
| 104 | #define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000) |
| 105 | #define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004) |
| 106 | |
| 107 | #define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20) |
| 108 | #define GLIU0_CAP (MSR_GLIU0 + 0x86) |
| 109 | #define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80) |
| 110 | |
| 111 | |
| 112 | /**/ |
| 113 | /* Memory Controller GLIU0 port 1*/ |
| 114 | /**/ |
| 115 | #define MC_GLD_MSR_CAP (MSR_MC + 0x2000) |
| 116 | #define MC_GLD_MSR_PM (MSR_MC + 0x2004) |
| 117 | |
| 118 | #define MC_CF07_DATA (MSR_MC + 0x18) |
| 119 | |
| 120 | #define CF07_UPPER_D1_SZ_SHIFT 28 |
| 121 | #define CF07_UPPER_D1_MB_SHIFT 24 |
| 122 | #define CF07_UPPER_D1_CB_SHIFT 20 |
| 123 | #define CF07_UPPER_D1_PSZ_SHIFT 16 |
| 124 | #define CF07_UPPER_D0_SZ_SHIFT 12 |
| 125 | #define CF07_UPPER_D0_MB_SHIFT 8 |
| 126 | #define CF07_UPPER_D0_CB_SHIFT 4 |
| 127 | #define CF07_UPPER_D0_PSZ_SHIFT 0 |
| 128 | |
| 129 | #define CF07_LOWER_REF_INT_SHIFT 8 |
| 130 | #define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28) |
| 131 | #define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27) |
| 132 | #define CF07_LOWER_EMR_QFC_SET (1 << 26) |
| 133 | #define CF07_LOWER_EMR_DRV_SET (1 << 25) |
| 134 | #define CF07_LOWER_REF_TEST_SET (1 << 3) |
| 135 | #define CF07_LOWER_PROG_DRAM_SET (1 << 0) |
| 136 | |
| 137 | |
| 138 | #define MC_CF8F_DATA (MSR_MC + 0x19) |
| 139 | |
| 140 | #define CF8F_UPPER_XOR_BS_SHIFT 19 |
| 141 | #define CF8F_UPPER_XOR_MB0_SHIFT 18 |
| 142 | #define CF8F_UPPER_XOR_BA1_SHIFT 17 |
| 143 | #define CF8F_UPPER_XOR_BA0_SHIFT 16 |
| 144 | #define CF8F_UPPER_REORDER_DIS_SET (1 << 8) |
| 145 | #define CF8F_UPPER_REG_DIMM_SHIFT 4 |
| 146 | #define CF8F_LOWER_CAS_LAT_SHIFT 28 |
| 147 | #define CF8F_LOWER_REF2ACT_SHIFT 24 |
| 148 | #define CF8F_LOWER_ACT2PRE_SHIFT 20 |
| 149 | #define CF8F_LOWER_PRE2ACT_SHIFT 16 |
| 150 | #define CF8F_LOWER_ACT2CMD_SHIFT 12 |
| 151 | #define CF8F_LOWER_ACT2ACT_SHIFT 8 |
| 152 | #define CF8F_UPPER_32BIT_SET (1 << 5) |
| 153 | #define CF8F_UPPER_HOI_LOI_SET (1 << 1) |
| 154 | |
| 155 | #define MC_CF1017_DATA (MSR_MC + 0x1A) |
| 156 | |
| 157 | #define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8) |
| 158 | #define CF1017_LOWER_WR2DAT_SHIFT 0 |
| 159 | |
| 160 | #define MC_CFCLK_DBUG (MSR_MC + 0x1D) |
| 161 | |
| 162 | #define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2) |
| 163 | #define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1) |
| 164 | #define CFCLK_UPPER_MTEST_EN_SET (1 << 0) |
| 165 | |
| 166 | #define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9) |
| 167 | #define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8) |
| 168 | #define CFCLK_LOWER_SDCLK_SET (0x0F << 0) |
| 169 | |
| 170 | #define MC_CF_RDSYNC (MSR_MC + 0x1F) |
| 171 | |
| 172 | |
| 173 | /**/ |
| 174 | /* GLIU1 GLIU0 port2*/ |
| 175 | /**/ |
| 176 | #define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000) |
| 177 | #define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004) |
| 178 | |
| 179 | #define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80) |
| 180 | |
| 181 | |
| 182 | /**/ |
| 183 | /* CPU ; does not need routing instructions since we are executing there.*/ |
| 184 | /**/ |
| 185 | #define CPU_GLD_MSR_CAP 0x2000 |
| 186 | #define CPU_GLD_MSR_CONFIG 0x2001 |
| 187 | #define CPU_GLD_MSR_PM 0x2004 |
| 188 | |
| 189 | #define CPU_GLD_MSR_DIAG 0x2005 |
| 190 | #define DIAG_SEL1_MODE_SHIFT 16 |
| 191 | #define DIAG_SEL1_SET (1 << 31) |
| 192 | #define DIAG_SEL0__MODE_SHIFT 0 |
| 193 | #define DIAG_SET0_SET (1 << 15) |
| 194 | |
| 195 | #define CPU_PF_BTB_CONF 0x1100 |
| 196 | #define BTB_ENABLE_SET (1 << 0) |
| 197 | #define RETURN_STACK_ENABLE_SET (1 << 4) |
| 198 | #define CPU_PF_BTBRMA_BIST 0x110C |
| 199 | |
| 200 | #define CPU_XC_CONFIG 0x1210 |
| 201 | #define XC_CONFIG_SUSP_ON_HLT (1 << 0) |
| 202 | #define CPU_ID_CONFIG 0x1250 |
| 203 | #define ID_CONFIG_SERIAL_SET (1 << 0) |
| 204 | |
| 205 | #define CPU_AC_MSR 0x1301 |
| 206 | #define CPU_EX_BIST 0x1428 |
| 207 | |
| 208 | /*IM*/ |
| 209 | #define CPU_IM_CONFIG 0x1700 |
| 210 | #define IM_CONFIG_LOWER_ICD_SET (1 << 8) |
| 211 | #define IM_CONFIG_LOWER_QWT_SET (1 << 20) |
| 212 | #define CPU_IC_INDEX 0x1710 |
| 213 | #define CPU_IC_DATA 0x1711 |
| 214 | #define CPU_IC_TAG 0x1712 |
| 215 | #define CPU_IC_TAG_I 0x1713 |
| 216 | #define CPU_ITB_INDEX 0x1720 |
| 217 | #define CPU_ITB_LRU 0x1721 |
| 218 | #define CPU_ITB_ENTRY 0x1722 |
| 219 | #define CPU_ITB_ENTRY_I 0x1723 |
| 220 | #define CPU_IM_BIST_TAG 0x1730 |
| 221 | #define CPU_IM_BIST_DATA 0x1731 |
| 222 | |
| 223 | |
| 224 | /* various CPU MSRs */ |
| 225 | #define CPU_DM_CONFIG0 0x1800 |
| 226 | #define DM_CONFIG0_UPPER_WSREQ_SHIFT 12 |
| 227 | #define DM_CONFIG0_LOWER_DCDIS_SET (1<<8) |
| 228 | #define DM_CONFIG0_LOWER_WBINVD_SET (1<<5) |
| 229 | #define DM_CONFIG0_LOWER_MISSER_SET (1<<1) |
| 230 | /* configuration MSRs */ |
| 231 | #define CPU_RCONF_DEFAULT 0x1808 |
| 232 | #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 |
| 233 | #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 |
| 234 | #define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0 |
| 235 | #define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28 |
| 236 | #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 |
| 237 | #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 |
| 238 | |
| 239 | #define CPU_RCONF_BYPASS 0x180A |
| 240 | #define CPU_RCONF_A0_BF 0x180B |
| 241 | #define CPU_RCONF_C0_DF 0x180C |
| 242 | #define CPU_RCONF_E0_FF 0x180D |
| 243 | |
| 244 | #define CPU_RCONF_SMM 0x180E |
| 245 | #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 |
| 246 | #define RCONF_SMM_UPPER_RCSMM_SHIFT 0 |
| 247 | #define RCONF_SMM_LOWER_SMMBASE_SHIFT 12 |
| 248 | #define RCONF_SMM_LOWER_RCNORM_SHIFT 0 |
| 249 | #define RCONF_SMM_LOWER_EN_SET (1<<8) |
| 250 | |
| 251 | #define CPU_RCONF_DMM 0x180F |
| 252 | #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 |
| 253 | #define RCONF_DMM_UPPER_RCDMM_SHIFT 0 |
| 254 | #define RCONF_DMM_LOWER_DMMBASE_SHIFT 12 |
| 255 | #define RCONF_DMM_LOWER_RCNORM_SHIFT 0 |
| 256 | #define RCONF_DMM_LOWER_EN_SET (1<<8) |
| 257 | |
| 258 | #define CPU_RCONF0 0x1810 |
| 259 | #define CPU_RCONF1 0x1811 |
| 260 | #define CPU_RCONF2 0x1812 |
| 261 | #define CPU_RCONF3 0x1813 |
| 262 | #define CPU_RCONF4 0x1814 |
| 263 | #define CPU_RCONF5 0x1815 |
| 264 | #define CPU_RCONF6 0x1816 |
| 265 | #define CPU_RCONF7 0x1817 |
| 266 | #define CPU_CR1_MSR 0x1881 |
| 267 | #define CPU_CR2_MSR 0x1882 |
| 268 | #define CPU_CR3_MSR 0x1883 |
| 269 | #define CPU_CR4_MSR 0x1884 |
| 270 | #define CPU_DC_INDEX 0x1890 |
| 271 | #define CPU_DC_DATA 0x1891 |
| 272 | #define CPU_DC_TAG 0x1892 |
| 273 | #define CPU_DC_TAG_I 0x1893 |
| 274 | #define CPU_SNOOP 0x1894 |
| 275 | #define CPU_DTB_INDEX 0x1898 |
| 276 | #define CPU_DTB_LRU 0x1899 |
| 277 | #define CPU_DTB_ENTRY 0x189A |
| 278 | #define CPU_DTB_ENTRY_I 0x189B |
| 279 | #define CPU_L2TB_INDEX 0x189C |
| 280 | #define CPU_L2TB_LRU 0x189D |
| 281 | #define CPU_L2TB_ENTRY 0x189E |
| 282 | #define CPU_L2TB_ENTRY_I 0x189F |
| 283 | #define CPU_DM_BIST 0x18C0 |
| 284 | /* SMM*/ |
| 285 | #define CPU_AC_SMM_CTL 0x1301 |
| 286 | #define SMM_NMI_EN_SET (1<<0) |
| 287 | #define SMM_SUSP_EN_SET (1<<1) |
| 288 | #define NEST_SMI_EN_SET (1<<2) |
| 289 | #define SMM_INST_EN_SET (1<<3) |
| 290 | #define INTL_SMI_EN_SET (1<<4) |
| 291 | #define EXTL_SMI_EN_SET (1<<5) |
| 292 | |
| 293 | #define CPU_FPU_MSR_MODE 0x1A00 |
| 294 | #define FPU_IE_SET (1<<0) |
| 295 | |
| 296 | #define CPU_FP_UROM_BIST 0x1A03 |
| 297 | |
| 298 | #define CPU_BC_CONF_0 0x1900 |
| 299 | #define TSC_SUSP_SET (1<<5) |
| 300 | #define SUSP_EN_SET (1<<12) |
| 301 | |
| 302 | /**/ |
| 303 | /* VG GLIU0 port4*/ |
| 304 | /**/ |
| 305 | |
| 306 | #define VG_GLD_MSR_CAP (MSR_VG + 0x2000) |
| 307 | #define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001) |
| 308 | #define VG_GLD_MSR_PM (MSR_VG + 0x2004) |
| 309 | |
| 310 | #define GP_GLD_MSR_CAP (MSR_GP + 0x2000) |
| 311 | #define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001) |
| 312 | #define GP_GLD_MSR_PM (MSR_GP + 0x2004) |
| 313 | |
| 314 | |
| 315 | |
| 316 | /**/ |
| 317 | /* DF GLIU0 port6*/ |
| 318 | /**/ |
| 319 | /* |
| 320 | #define DF_GLD_MSR_CAP (MSR_DF + 0x2000) |
| 321 | #define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001) |
| 322 | #define DF_LOWER_LCD_SHIFT 6 |
| 323 | #define DF_GLD_MSR_PM (MSR_DF + 0x2004) |
| 324 | |
| 325 | */ |
| 326 | |
| 327 | /**/ |
| 328 | /* GeodeLink Control Processor GLIU1 port3*/ |
| 329 | /**/ |
| 330 | #define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000) |
| 331 | #define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001) |
| 332 | #define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004) |
| 333 | |
| 334 | #define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F) |
| 335 | |
| 336 | #define GLCP_SYS_RSTPLL (MSR_GLCP +0x14 /* R/W*/) |
| 337 | #define RSTPLL_UPPER_MDIV_SHIFT 9 |
| 338 | #define RSTPLL_UPPER_VDIV_SHIFT 6 |
| 339 | #define RSTPLL_UPPER_FBDIV_SHIFT 0 |
| 340 | |
| 341 | #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 |
| 342 | #define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT) |
| 343 | |
| 344 | #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16 |
| 345 | #define RSTPPL_LOWER_BYPASS_SHIFT 15 |
| 346 | #define RSTPPL_LOWER_TST_SHIFT 11 |
| 347 | #define RSTPPL_LOWER_SDRMODE_SHIFT 10 |
| 348 | #define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4 |
| 349 | |
| 350 | #define RSTPPL_LOWER_LOCK_SET (1<<25) |
| 351 | #define RSTPPL_LOWER_LOCKWAIT_SET (1<<24) |
| 352 | #define RSTPPL_LOWER_BYPASS_SET (1<<15) |
| 353 | #define RSTPPL_LOWER_PD_SET (1<<14) |
| 354 | #define RSTPPL_LOWER_PLL_RESET_SET (1<<13) |
| 355 | #define RSTPPL_LOWER_SDRMODE_SET (1<<10) |
| 356 | #define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9) |
| 357 | #define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8) |
| 358 | #define RSTPPL_LOWER_CHIP_RESET_SET (1<<0) |
| 359 | |
| 360 | #define GLCP_DOTPLL (MSR_GLCP + 0x15 /* R/W*/) |
| 361 | #define DOTPPL_LOWER_PD_SET (1<<14) |
| 362 | |
| 363 | |
| 364 | /**/ |
| 365 | /* GLIU1 port 4*/ |
| 366 | /**/ |
| 367 | #define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000) |
| 368 | #define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001) |
| 369 | #define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004) |
| 370 | |
| 371 | #define GLPCI_CTRL (MSR_PCI + 0x2010) |
| 372 | #define GLPCI_CTRL_UPPER_FTH_SHIFT 28 |
| 373 | #define GLPCI_CTRL_UPPER_RTH_SHIFT 24 |
| 374 | #define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20 |
| 375 | #define GLPCI_CTRL_UPPER_DTL_SHIFT 14 |
| 376 | #define GLPCI_CTRL_UPPER_WTO_SHIFT 11 |
| 377 | #define GLPCI_CTRL_UPPER_LAT_SHIFT 3 |
| 378 | #define GLPCI_CTRL_UPPER_ILTO_SHIFT 8 |
| 379 | #define GLPCI_CTRL_LOWER_IRFT_SHIFT 18 |
| 380 | #define GLPCI_CTRL_LOWER_IRFC_SHIFT 16 |
| 381 | #define GLPCI_CTRL_LOWER_ER_SET (1<<11) |
| 382 | #define GLPCI_CTRL_LOWER_LDE_SET (1<<9) |
| 383 | #define GLPCI_CTRL_LOWER_OWC_SET (1<<4) |
| 384 | #define GLPCI_CTRL_LOWER_IWC_SET (1<<3) |
| 385 | #define GLPCI_CTRL_LOWER_PCD_SET (1<<2) |
| 386 | #define GLPCI_CTRL_LOWER_ME_SET (1<<0) |
| 387 | |
| 388 | #define GLPCI_ARB (MSR_PCI + 0x2011) |
| 389 | #define GLPCI_ARB_UPPER_BM1_SET (1<<17) |
| 390 | #define GLPCI_ARB_UPPER_BM0_SET (1<<16) |
| 391 | #define GLPCI_ARB_UPPER_CPRE_SET (1<<15) |
| 392 | #define GLPCI_ARB_UPPER_PRE2_SET (1<<10) |
| 393 | #define GLPCI_ARB_UPPER_PRE1_SET (1<<9) |
| 394 | #define GLPCI_ARB_UPPER_PRE0_SET (1<<8) |
| 395 | #define GLPCI_ARB_UPPER_CRME_SET (1<<7) |
| 396 | #define GLPCI_ARB_UPPER_RME2_SET (1<<2) |
| 397 | #define GLPCI_ARB_UPPER_RME1_SET (1<<1) |
| 398 | #define GLPCI_ARB_UPPER_RME0_SET (1<<0) |
| 399 | #define GLPCI_ARB_LOWER_PRCM_SHIFT 24 |
| 400 | #define GLPCI_ARB_LOWER_FPVEC_SHIFT 16 |
| 401 | #define GLPCI_ARB_LOWER_RMT_SHIFT 6 |
| 402 | #define GLPCI_ARB_LOWER_IIE_SET (1<<8) |
| 403 | #define GLPCI_ARB_LOWER_PARK_SET (1<<0) |
| 404 | |
| 405 | #define GLPCI_REN (MSR_PCI + 0x2014) |
| 406 | #define GLPCI_A0_BF (MSR_PCI + 0x2015) |
| 407 | #define GLPCI_C0_DF (MSR_PCI + 0x2016) |
| 408 | #define GLPCI_E0_FF (MSR_PCI + 0x2017) |
| 409 | #define GLPCI_RC0 (MSR_PCI + 0x2018) |
| 410 | #define GLPCI_RC1 (MSR_PCI + 0x2019) |
| 411 | #define GLPCI_RC2 (MSR_PCI + 0x201A) |
| 412 | #define GLPCI_RC3 (MSR_PCI + 0x201B) |
| 413 | #define GLPCI_RC4 (MSR_PCI + 0x201C) |
| 414 | #define GLPCI_RC_UPPER_TOP_SHIFT 12 |
| 415 | #define GLPCI_RC_LOWER_BASE_SHIFT 12 |
| 416 | #define GLPCI_RC_LOWER_EN_SET (1<<8) |
| 417 | #define GLPCI_RC_LOWER_PF_SET (1<<5) |
| 418 | #define GLPCI_RC_LOWER_WC_SET (1<<4) |
| 419 | #define GLPCI_RC_LOWER_WP_SET (1<<2) |
| 420 | #define GLPCI_RC_LOWER_CD_SET (1<<0) |
| 421 | #define GLPCI_EXT_MSR (MSR_PCI + 0x201E) |
| 422 | #define GLPCI_SPARE (MSR_PCI + 0x201F) |
| 423 | #define GLPCI_SPARE_LOWER_AILTO_SET (1<<6) |
| 424 | #define GLPCI_SPARE_LOWER_PPD_SET (1<<5) |
| 425 | #define GLPCI_SPARE_LOWER_PPC_SET (1<<4) |
| 426 | #define GLPCI_SPARE_LOWER_MPC_SET (1<<3) |
| 427 | #define GLPCI_SPARE_LOWER_MME_SET (1<<2) |
| 428 | #define GLPCI_SPARE_LOWER_NSE_SET (1<<1) |
| 429 | #define GLPCI_SPARE_LOWER_SUPO_SET (1<<0) |
| 430 | |
| 431 | |
| 432 | /**/ |
| 433 | /* FooGlue GLIU1 port 5*/ |
| 434 | /**/ |
| 435 | /* GX3 not needed? |
| 436 | #define FG_GLD_MSR_CAP (MSR_FG + 0x2000) |
| 437 | #define FG_GLD_MSR_PM (MSR_FG + 0x2004) |
| 438 | */ |
| 439 | /* VIP GLIU1 port 5*/ |
| 440 | /* */ |
| 441 | #define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000) |
| 442 | #define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001) |
| 443 | #define VIP_GLD_MSR_PM (MSR_VIP + 0x2004) |
| 444 | #define VIP_BIST (MSR_VIP + 0x2005) |
| 445 | /* */ |
| 446 | /* AES GLIU1 port 6*/ |
| 447 | /* */ |
| 448 | #define AES_GLD_MSR_CAP (MSR_AES + 0x2000) |
| 449 | #define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001) |
| 450 | #define AES_GLD_MSR_PM (MSR_AES + 0x2004) |
| 451 | #define AES_CONTROL (MSR_AES + 0x2006) |
| 452 | /* more fun stuff */ |
| 453 | #define BM 1 /* Base Mask - map power of 2 size aligned region*/ |
| 454 | #define BMO 2 /* BM with an offset*/ |
| 455 | #define R 3 /* Range - 4k range minimum*/ |
| 456 | #define RO 4 /* R with offset*/ |
| 457 | #define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/ |
| 458 | #define BMIO 6 /* Base Mask IO*/ |
| 459 | #define SCIO 7 /* Swiss 0xCeese IO*/ |
| 460 | #define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU*/ |
| 461 | #define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU*/ |
| 462 | #define BMO_SMM 10 /* Specail marker for SMM*/ |
| 463 | #define BM_SMM 11 /* Specail marker for SMM*/ |
| 464 | #define BMO_DMM 12 /* Specail marker for DMM*/ |
| 465 | #define BM_DMM 13 /* Specail marker for DMM*/ |
| 466 | #define RO_FB 14 /* special for Frame buffer.*/ |
| 467 | #define R_FB 15 /* special for FB.*/ |
| 468 | #define OTHER 0x0FE /* Special marker for other*/ |
| 469 | #define GL_END 0x0FF /* end*/ |
| 470 | |
| 471 | #define MSR_GL0 (GL1_GLIU0 << 29) |
| 472 | |
| 473 | /* Set up desc addresses from 20 - 3f*/ |
| 474 | /* This is chip specific!*/ |
| 475 | #define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/ |
| 476 | #define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/ |
| 477 | #define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/ |
| 478 | #define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R*/ |
| 479 | #define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO*/ |
| 480 | #define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO*/ |
| 481 | |
| 482 | #define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM*/ |
| 483 | #define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM*/ |
| 484 | #define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC*/ |
| 485 | #define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R*/ |
| 486 | #define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM*/ |
| 487 | #define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM*/ |
| 488 | #define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU*/ |
| 489 | |
| 490 | /* definitions that are "once you are mostly up, start VSA" type things */ |
| 491 | #define SMM_OFFSET (0x40400000) |
| 492 | #define SMM_SIZE (128) /* changed SMM_SIZE from 256 KB to 128 KB */ |
| 493 | #define DMM_OFFSET (0x0C0000000) |
| 494 | #define DMM_SIZE (128) |
| 495 | #define FB_OFFSET (0x41000000) |
| 496 | #define PCI_MEM_TOP (0x0EFFFFFFF) // Top of PCI mem allocation region |
| 497 | #define PCI_IO_TOP (0x0EFFF) // Top of PCI I/O allocation region |
| 498 | #define END_OPTIONROM_SPACE (0x0DFFF) // E0000 is reserved for SystemROMs. |
| 499 | |
| 500 | |
| 501 | #define CS5535_IDSEL (0x02000000) // IDSEL = AD25, device #15 |
| 502 | #define CHIPSET_DEV_NUM (15) |
| 503 | #define IDSEL_BASE (11) // bit 11 = device 1 |
| 504 | |
| 505 | |
| 506 | /* standard AMD post definitions -- might as well use them. */ |
| 507 | #define POST_Output_Port (0x080) /* port to write post codes to*/ |
| 508 | |
| 509 | #define POST_preSioInit (0x000) /* geode.asm*/ |
| 510 | #define POST_clockInit (0x001) /* geode.asm*/ |
| 511 | #define POST_CPURegInit (0x002) /* geode.asm*/ |
| 512 | #define POST_UNREAL (0x003) /* geode.asm*/ |
| 513 | #define POST_CPUMemRegInit (0x004) /* geode.asm*/ |
| 514 | #define POST_CPUTest (0x005) /* geode.asm*/ |
| 515 | #define POST_memSetup (0x006) /* geode.asm*/ |
| 516 | #define POST_memSetUpStack (0x007) /* geode.asm*/ |
| 517 | #define POST_memTest (0x008) /* geode.asm*/ |
| 518 | #define POST_shadowRom (0x009) /* geode.asm*/ |
| 519 | #define POST_memRAMoptimize (0x00A) /* geode.asm*/ |
| 520 | #define POST_cacheInit (0x00B) /* geode.asm*/ |
| 521 | #define POST_northBridgeInit (0x00C) /* geode.asm*/ |
| 522 | #define POST_chipsetInit (0x00D) /* geode.asm*/ |
| 523 | #define POST_sioTest (0x00E) /* geode.asm*/ |
| 524 | #define POST_pcATjunk (0x00F) /* geode.asm*/ |
| 525 | |
| 526 | |
| 527 | #define POST_intTable (0x010) /* geode.asm*/ |
| 528 | #define POST_memInfo (0x011) /* geode.asm*/ |
| 529 | #define POST_romCopy (0x012) /* geode.asm*/ |
| 530 | #define POST_PLLCheck (0x013) /* geode.asm*/ |
| 531 | #define POST_keyboardInit (0x014) /* geode.asm*/ |
| 532 | #define POST_cpuCacheOff (0x015) /* geode.asm*/ |
| 533 | #define POST_BDAInit (0x016) /* geode.asm*/ |
| 534 | #define POST_pciScan (0x017) /* geode.asm*/ |
| 535 | #define POST_optionRomInit (0x018) /* geode.asm*/ |
| 536 | #define POST_ResetLimits (0x019) /* geode.asm*/ |
| 537 | #define POST_summary_screen (0x01A) /* geode.asm*/ |
| 538 | #define POST_Boot (0x01B) /* geode.asm*/ |
| 539 | #define POST_SystemPreInit (0x01C) /* geode.asm*/ |
| 540 | #define POST_ClearRebootFlag (0x01D) /* geode.asm*/ |
| 541 | #define POST_GLIUInit (0x01E) /* geode.asm*/ |
| 542 | #define POST_BootFailed (0x01F) /* geode.asm*/ |
| 543 | |
| 544 | |
| 545 | #define POST_CPU_ID (0x020) /* cpucpuid.asm*/ |
| 546 | #define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/ |
| 547 | #define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/ |
| 548 | #define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/ |
| 549 | #define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/ |
| 550 | #define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/ |
| 551 | #define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/ |
| 552 | #define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/ |
| 553 | #define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/ |
| 554 | #define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/ |
| 555 | #define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/ |
| 556 | #define POST_CHIPSET_ID (0x02b) /* chipset.asm*/ |
| 557 | #define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/ |
| 558 | #define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/ |
| 559 | #define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/ |
| 560 | #define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/ |
| 561 | |
| 562 | |
| 563 | |
| 564 | /* PCI config*/ |
| 565 | #define P80_PCICFG (0x030) /* pcispace.asm*/ |
| 566 | |
| 567 | |
| 568 | /* PCI io*/ |
| 569 | #define P80_PCIIO (0x040) /* pcispace.asm*/ |
| 570 | |
| 571 | |
| 572 | /* PCI memory*/ |
| 573 | #define P80_PCIMEM (0x050) /* pcispace.asm*/ |
| 574 | |
| 575 | |
| 576 | /* SIO*/ |
| 577 | #define P80_SIO (0x060) /* *sio.asm*/ |
| 578 | |
| 579 | /* Memory Setp*/ |
| 580 | #define P80_MEM_SETUP (0x070) /* docboot meminit*/ |
| 581 | #define POST_MEM_SETUP (0x070) /* memsize.asm*/ |
| 582 | #define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/ |
| 583 | #define POST_MEM_SETUP2 (0x072) /* memsize.asm*/ |
| 584 | #define POST_MEM_SETUP3 (0x073) /* memsize.asm*/ |
| 585 | #define POST_MEM_SETUP4 (0x074) /* memsize.asm*/ |
| 586 | #define POST_MEM_SETUP5 (0x075) /* memsize.asm*/ |
| 587 | #define POST_MEM_ENABLE (0x076) /* memsize.asm*/ |
| 588 | #define ERROR_NO_DIMMS (0x077) /* memsize.asm*/ |
| 589 | #define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/ |
| 590 | #define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/ |
| 591 | #define ERROR_SET_PAGE (0x07a) /* memsize.asm*/ |
| 592 | #define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/ |
| 593 | #define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/ |
| 594 | #define ERROR_BANK_SET (0x07d) /* memsize.asm*/ |
| 595 | #define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/ |
| 596 | #define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/ |
| 597 | |
| 598 | |
| 599 | #define POST_UserPreInit (0x080) /* geode.asm*/ |
| 600 | #define POST_UserPostInit (0x081) /* geode.asm*/ |
| 601 | #define POST_Equipment_check (0x082) /* geode.asm*/ |
| 602 | #define POST_InitNVRAMBX (0x083) /* geode.asm*/ |
| 603 | #define POST_NoPIRTable (0x084) /* pci.asm*/ |
| 604 | #define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/ |
| 605 | #define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/ |
| 606 | #define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/ |
| 607 | #define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/ |
| 608 | #define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/ |
| 609 | #define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/ |
| 610 | #define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/ |
| 611 | #define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/ |
| 612 | #define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/ |
| 613 | #define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/ |
| 614 | |
| 615 | |
| 616 | #define POST_STACK_SETUP (0x090) /* memstack.asm*/ |
| 617 | #define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/ |
| 618 | #define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/ |
| 619 | #define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/ |
| 620 | #define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/ |
| 621 | #define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/ |
| 622 | #define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/ |
| 623 | #define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/ |
| 624 | #define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/ |
| 625 | |
| 626 | |
| 627 | #define POST_PLL_INIT (0x0A0) /* pllinit.asm*/ |
| 628 | #define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/ |
| 629 | #define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/ |
| 630 | #define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/ |
| 631 | #define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/ |
| 632 | #define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/ |
| 633 | #define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/ |
| 634 | |
| 635 | |
| 636 | #define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/ |
| 637 | #define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/ |
| 638 | #define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/ |
| 639 | #define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/ |
| 640 | #define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/ |
| 641 | #define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/ |
| 642 | #define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/ |
| 643 | |
| 644 | |
| 645 | #define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/ |
| 646 | #define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/ |
| 647 | #define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/ |
| 648 | #define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/ |
| 649 | #define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/ |
| 650 | #define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/ |
| 651 | #define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/ |
| 652 | #define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/ |
| 653 | #define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/ |
| 654 | #define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/ |
| 655 | #define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/ |
| 656 | #define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/ |
| 657 | #define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/ |
| 658 | #define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/ |
| 659 | |
| 660 | #define POST_RCONFInitError (0x0CE) /* cache.asm*/ |
| 661 | #define POST_CacheInitError (0x0CF) /* cache.asm*/ |
| 662 | |
| 663 | |
| 664 | #define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/ |
| 665 | #define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/ |
| 666 | #define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/ |
| 667 | #define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/ |
| 668 | #define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/ |
| 669 | #define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/ |
| 670 | #define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/ |
| 671 | #define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/ |
| 672 | #define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/ |
| 673 | #define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/ |
| 674 | #define POST_ROM_POSTUNCOMPRESS (0x0DE) |
| 675 | |
| 676 | |
| 677 | #define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/ |
| 678 | #define POST_PreChipsetInit (0x0E1) /* geode.asm*/ |
| 679 | #define POST_LateChipsetInit (0x0E2) /* geode.asm*/ |
| 680 | #define POST_NORTHB_INIT (0x0E8) /* northb.asm*/ |
| 681 | |
| 682 | |
| 683 | #define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/ |
| 684 | |
| 685 | |
| 686 | /* I don't mind if somebody decides this needs to be in a seperate file. I don't see much point |
| 687 | * in it, either. |
| 688 | * RGM |
| 689 | */ |
| 690 | #define Cx5535_ID ( 0x002A100B) |
| 691 | #define Cx5536_ID ( 0x208F1022) |
| 692 | |
| 693 | /* Cs5535 as follows. */ |
| 694 | /* SB_GLIU*/ |
| 695 | /* port0 - GLIU*/ |
| 696 | /* port1 - GLPCI*/ |
| 697 | /* port2 - USB Controller #2*/ |
| 698 | /* port3 - ATA-5 Controller*/ |
| 699 | /* port4 - MDD*/ |
| 700 | /* port5 - AC97*/ |
| 701 | /* port6 - USB Controller #1*/ |
| 702 | /* port7 - GLCP*/ |
| 703 | |
| 704 | |
| 705 | /* SouthBridge Equates*/ |
| 706 | /* MSR_SB and SB_SHIFT are located in CPU.inc*/ |
| 707 | #define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */ |
| 708 | #define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */ |
| 709 | #define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */ |
| 710 | #define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */ |
| 711 | #define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */ |
| 712 | #define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */ |
| 713 | #define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */ |
| 714 | #define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */ |
| 715 | |
| 716 | /* */ |
| 717 | /* GLIU*/ |
| 718 | /* */ |
| 719 | #define GLIU_SB_GLD_MSR_CAP ( MSR_SB_GLIU + 0x00) |
| 720 | #define GLIU_SB_GLD_MSR_CONF ( MSR_SB_GLIU + 0x01) |
| 721 | #define GLIU_SB_GLD_MSR_PM ( MSR_SB_GLIU + 0x04) |
| 722 | |
| 723 | /* */ |
| 724 | /* USB1*/ |
| 725 | /* */ |
| 726 | #define USB1_SB_GLD_MSR_CAP ( MSR_SB_USB1 + 0x00) |
| 727 | #define USB1_SB_GLD_MSR_CONF ( MSR_SB_USB1 + 0x01) |
| 728 | #define USB1_SB_GLD_MSR_PM ( MSR_SB_USB1 + 0x04) |
| 729 | /* */ |
| 730 | /* USB2*/ |
| 731 | /* */ |
| 732 | #define USB2_SB_GLD_MSR_CAP ( MSR_SB_USB2 + 0x00) |
| 733 | #define USB2_SB_GLD_MSR_CONF ( MSR_SB_USB2 + 0x01) |
| 734 | #define USB2_SB_GLD_MSR_PM ( MSR_SB_USB2 + 0x04) |
| 735 | |
| 736 | |
| 737 | /* */ |
| 738 | /* ATA*/ |
| 739 | /* */ |
| 740 | #define ATA_SB_GLD_MSR_CAP ( MSR_SB_ATA + 0x00) |
| 741 | #define ATA_SB_GLD_MSR_CONF ( MSR_SB_ATA + 0x01) |
| 742 | #define ATA_SB_GLD_MSR_ERR ( MSR_SB_ATA + 0x03) |
| 743 | #define ATA_SB_GLD_MSR_PM ( MSR_SB_ATA + 0x04) |
| 744 | |
| 745 | /* */ |
| 746 | /* AC97*/ |
| 747 | /* */ |
| 748 | #define AC97_SB_GLD_MSR_CAP ( MSR_SB_AC97 + 0x00) |
| 749 | #define AC97_SB_GLD_MSR_CONF ( MSR_SB_AC97 + 0x01) |
| 750 | #define AC97_SB_GLD_MSR_PM ( MSR_SB_AC97 + 0x04) |
| 751 | |
| 752 | /* */ |
| 753 | /* GLPCI*/ |
| 754 | /* */ |
| 755 | #define GLPCI_SB_GLD_MSR_CAP ( MSR_SB_GLPCI + 0x00) |
| 756 | #define GLPCI_SB_GLD_MSR_CONF ( MSR_SB_GLPCI + 0x01) |
| 757 | #define GLPCI_SB_GLD_MSR_PM ( MSR_SB_GLPCI + 0x04) |
| 758 | #define GLPCI_SB_CTRL ( MSR_SB_GLPCI + 0x10) |
| 759 | #define GLPCI_CRTL_PPIDE_SET ( 1 << 17) |
| 760 | /* */ |
| 761 | /* GLCP*/ |
| 762 | /* */ |
| 763 | #define GLCP_SB_GLD_MSR_CAP ( MSR_SB_GLCP + 0x00) |
| 764 | #define GLCP_SB_GLD_MSR_CONF ( MSR_SB_GLCP + 0x01) |
| 765 | #define GLCP_SB_GLD_MSR_PM ( MSR_SB_GLCP + 0x04) |
| 766 | |
| 767 | /* */ |
| 768 | /* MDD*/ |
| 769 | /* */ |
| 770 | |
| 771 | #define MDD_SMBUS (0x6000) |
| 772 | #define MDD_GPIO (0x6100) |
| 773 | #define MDD_MFGPT (0x6200) |
| 774 | #define MDD_FLASH_BAR_0 (0x6400) |
| 775 | #define MDD_FLASH_BAR_1 (0x6500) |
| 776 | #define MDD_FLASH_BAR_2 (0x6600) |
| 777 | #define MDD_FLASH_BAR_3 (0x6700) |
| 778 | |
| 779 | #define MDD_ACPI_BASE (0x9C00) |
| 780 | #define MDD_PM (0x9D00) |
| 781 | |
| 782 | |
| 783 | // # FIXME |
| 784 | #define GPIO_BASE MDD_GPIO |
| 785 | #define ACPI_BASE MDD_ACPI_BASE |
| 786 | #define PMLogic_BASE MDD_PM |
| 787 | |
| 788 | |
| 789 | #define MDD_SB_GLD_MSR_CAP ( MSR_SB_MDD + 0x00) |
| 790 | #define MDD_SB_GLD_MSR_CONF ( MSR_SB_MDD + 0x01) |
| 791 | #define MDD_SB_GLD_MSR_PM ( MSR_SB_MDD + 0x04) |
| 792 | #define LBAR_EN ( 0x01) |
| 793 | #define IO_MASK ( 0x1f) |
| 794 | #define MEM_MASK ( 0x0FFFFF) |
| 795 | #define MDD_LBAR_IRQ ( MSR_SB_MDD + 0x08) |
| 796 | #define MDD_LBAR_KEL1 ( MSR_SB_MDD + 0x09) |
| 797 | #define MDD_LBAR_KEL2 ( MSR_SB_MDD + 0x0A) |
| 798 | #define MDD_LBAR_SMB ( MSR_SB_MDD + 0x0B) |
| 799 | #define MDD_LBAR_GPIO ( MSR_SB_MDD + 0x0C) |
| 800 | #define MDD_LBAR_MFGPT ( MSR_SB_MDD + 0x0D) |
| 801 | #define MDD_LBAR_ACPI ( MSR_SB_MDD + 0x0E) |
| 802 | #define MDD_LBAR_PMS ( MSR_SB_MDD + 0x0F) |
| 803 | |
| 804 | #define MDD_LBAR_FLSH0 ( MSR_SB_MDD + 0x010) |
| 805 | #define MDD_LBAR_FLSH1 ( MSR_SB_MDD + 0x011) |
| 806 | #define MDD_LBAR_FLSH2 ( MSR_SB_MDD + 0x012) |
| 807 | #define MDD_LBAR_FLSH3 ( MSR_SB_MDD + 0x013) |
| 808 | #define MDD_LEG_IO ( MSR_SB_MDD + 0x014) |
| 809 | #define MDD_PIN_OPT ( MSR_SB_MDD + 0x015) |
| 810 | #define MDD_SOFT_IRQ ( MSR_SB_MDD + 0x016) |
| 811 | #define MDD_SOFT_RESET ( MSR_SB_MDD + 0x017) |
| 812 | #define MDD_NORF_CNTRL ( MSR_SB_MDD + 0x018) |
| 813 | #define MDD_NORF_T01 ( MSR_SB_MDD + 0x019) |
| 814 | #define MDD_NORF_T23 ( MSR_SB_MDD + 0x01A) |
| 815 | #define MDD_NANDF_DATA ( MSR_SB_MDD + 0x01B) |
| 816 | #define MDD_NADF_CNTL ( MSR_SB_MDD + 0x01C) |
| 817 | #define MDD_AC_DMA ( MSR_SB_MDD + 0x01E) |
| 818 | #define MDD_KEL_CNTRL ( MSR_SB_MDD + 0x01F) |
| 819 | |
| 820 | #define MDD_IRQM_YLOW ( MSR_SB_MDD + 0x020) |
| 821 | #define MDD_IRQM_YHIGH ( MSR_SB_MDD + 0x021) |
| 822 | #define MDD_IRQM_ZLOW ( MSR_SB_MDD + 0x022) |
| 823 | #define MDD_IRQM_ZHIGH ( MSR_SB_MDD + 0x023) |
| 824 | #define MDD_IRQM_PRIM ( MSR_SB_MDD + 0x024) |
| 825 | #define MDD_IRQM_LPC ( MSR_SB_MDD + 0x025) |
| 826 | #define MDD_IRQM_LXIRR ( MSR_SB_MDD + 0x026) |
| 827 | #define MDD_IRQM_HXIRR ( MSR_SB_MDD + 0x027) |
| 828 | |
| 829 | #define MDD_MFGPT_IRQ ( MSR_SB_MDD + 0x028) |
| 830 | #define MDD_MFGPT_NR ( MSR_SB_MDD + 0x029) |
| 831 | #define MDD_MFGPT_RES0 ( MSR_SB_MDD + 0x02A) |
| 832 | #define MDD_MFGPT_RES1 ( MSR_SB_MDD + 0x02B) |
| 833 | |
| 834 | #define MDD_FLOP_S3F2 ( MSR_SB_MDD + 0x030) |
| 835 | #define MDD_FLOP_S3F7 ( MSR_SB_MDD + 0x031) |
| 836 | #define MDD_FLOP_S372 ( MSR_SB_MDD + 0x032) |
| 837 | #define MDD_FLOP_S377 ( MSR_SB_MDD + 0x033) |
| 838 | |
| 839 | #define MDD_PIC_S ( MSR_SB_MDD + 0x034) |
| 840 | #define MDD_PIT_S ( MSR_SB_MDD + 0x036) |
| 841 | #define MDD_PIT_CNTRL ( MSR_SB_MDD + 0x037) |
| 842 | |
| 843 | #define MDD_UART1_MOD ( MSR_SB_MDD + 0x038) |
| 844 | #define MDD_UART1_DON ( MSR_SB_MDD + 0x039) |
| 845 | #define MDD_UART1_CONF ( MSR_SB_MDD + 0x03A) |
| 846 | #define MDD_UART2_MOD ( MSR_SB_MDD + 0x03C) |
| 847 | #define MDD_UART2_DON ( MSR_SB_MDD + 0x03D) |
| 848 | #define MDD_UART2_CONF ( MSR_SB_MDD + 0x03E) |
| 849 | |
| 850 | #define MDD_DMA_MAP ( MSR_SB_MDD + 0x040) |
| 851 | #define MDD_DMA_SHAD1 ( MSR_SB_MDD + 0x041) |
| 852 | #define MDD_DMA_SHAD2 ( MSR_SB_MDD + 0x042) |
| 853 | #define MDD_DMA_SHAD3 ( MSR_SB_MDD + 0x043) |
| 854 | #define MDD_DMA_SHAD4 ( MSR_SB_MDD + 0x044) |
| 855 | #define MDD_DMA_SHAD5 ( MSR_SB_MDD + 0x045) |
| 856 | #define MDD_DMA_SHAD6 ( MSR_SB_MDD + 0x046) |
| 857 | #define MDD_DMA_SHAD7 ( MSR_SB_MDD + 0x047) |
| 858 | #define MDD_DMA_SHAD8 ( MSR_SB_MDD + 0x048) |
| 859 | #define MDD_DMA_SHAD9 ( MSR_SB_MDD + 0x049) |
| 860 | |
| 861 | #define MDD_LPC_EADDR ( MSR_SB_MDD + 0x04C) |
| 862 | #define MDD_LPC_ESTAT ( MSR_SB_MDD + 0x04D) |
| 863 | #define MDD_LPC_SIRQ ( MSR_SB_MDD + 0x04E) |
| 864 | #define MDD_LPC_RES ( MSR_SB_MDD + 0x04F) |
| 865 | |
| 866 | #define MDD_PML_TMR ( MSR_SB_MDD + 0x050) |
| 867 | #define MDD_RTC_RAM_LO_CK ( MSR_SB_MDD + 0x054) |
| 868 | #define MDD_RTC_DOMA_IND ( MSR_SB_MDD + 0x055) |
| 869 | #define MDD_RTC_MONA_IND ( MSR_SB_MDD + 0x056) |
| 870 | #define MDD_RTC_CENTURY_OFFSET ( MSR_SB_MDD + 0x057) |
| 871 | |
| 872 | /* ***********************************************************/ |
| 873 | /* LBUS Device Equates - */ |
| 874 | /* ***********************************************************/ |
| 875 | |
| 876 | /* */ |
| 877 | /* SMBus*/ |
| 878 | /* */ |
| 879 | |
| 880 | #define SMBUS_SMBSDA ( SMBUS_BASE + 0x00) |
| 881 | #define SMBUS_SMBST ( SMBUS_BASE + 0x01) |
| 882 | #define SMBST_SLVSTP_SET ( 1 << 7) |
| 883 | #define SMBST_SDAST_SET ( 1 << 6) |
| 884 | #define SMBST_BER_SET ( 1 << 5) |
| 885 | #define SMBST_NEGACK_SET ( 1 << 4) |
| 886 | #define SMBST_STASTR_SET ( 1 << 3) |
| 887 | #define SMBST_NMATCH_SET ( 1 << 2) |
| 888 | #define SMBST_MASTER_SET ( 1 << 1) |
| 889 | #define SMBST_XMIT_SET ( 1 << 0) |
| 890 | #define SMBUS_SMBCST ( SMBUS_BASE + 0x02) |
| 891 | #define SMBCST_TGSCL_SET ( 1 << 5) |
| 892 | #define SMBCST_TSDA_SET ( 1 << 4) |
| 893 | #define SMBCST_GCMTCH_SET ( 1 << 3) |
| 894 | #define SMBCST_MATCH_SET ( 1 << 2) |
| 895 | #define SMBCST_BB_SET ( 1 << 1) |
| 896 | #define SMBCST_BUSY_SET ( 1 << 0) |
| 897 | #define SMBUS_SMBCTL1 ( SMBUS_BASE + 0x03) |
| 898 | #define SMBCTL1_STASTRE_SET ( 1 << 7) |
| 899 | #define SMBCTL1_NMINTE_SET ( 1 << 6) |
| 900 | #define SMBCTL1_GCMEN_SET ( 1 << 5) |
| 901 | #define SMBCTL1_RECACK_SET ( 1 << 4) |
| 902 | #define SMBCTL1_DMAEN_SET ( 1 << 3) |
| 903 | #define SMBCTL1_INTEN_SET ( 1 << 2) |
| 904 | #define SMBCTL1_STOP_SET ( 1 << 1) |
| 905 | #define SMBCTL1_START_SET ( 1 << 0) |
| 906 | #define SMBUS_SMBADDR ( SMBUS_BASE + 0x04) |
| 907 | #define SMBADDR_SAEN_SET ( 1 << 7) |
| 908 | #define SMBUS_SMBCTL2 ( SMBUS_BASE + 0x05) |
| 909 | #define SMBCTL2_SCLFRQ_SHIFT ( 1 << 1) |
| 910 | #define SMBCTL2_ENABLE_SET ( 1 << 0) |
| 911 | |
| 912 | /* */ |
| 913 | /* GPIO*/ |
| 914 | /* */ |
| 915 | |
| 916 | #define GPIOL_0_SET ( 1 << 0) |
| 917 | #define GPIOL_1_SET ( 1 << 1) |
| 918 | #define GPIOL_2_SET ( 1 << 2) |
| 919 | #define GPIOL_3_SET ( 1 << 3) |
| 920 | #define GPIOL_4_SET ( 1 << 4) |
| 921 | #define GPIOL_5_SET ( 1 << 5) |
| 922 | #define GPIOL_6_SET ( 1 << 6) |
| 923 | #define GPIOL_7_SET ( 1 << 7) |
| 924 | #define GPIOL_8_SET ( 1 << 8) |
| 925 | #define GPIOL_9_SET ( 1 << 9) |
| 926 | #define GPIOL_10_SET ( 1 << 10) |
| 927 | #define GPIOL_11_SET ( 1 << 11) |
| 928 | #define GPIOL_12_SET ( 1 << 12) |
| 929 | #define GPIOL_13_SET ( 1 << 13) |
| 930 | #define GPIOL_14_SET ( 1 << 14) |
| 931 | #define GPIOL_15_SET ( 1 << 15) |
| 932 | |
| 933 | #define GPIOL_0_CLEAR ( 1 << 16) |
| 934 | #define GPIOL_1_CLEAR ( 1 << 17) |
| 935 | #define GPIOL_2_CLEAR ( 1 << 18) |
| 936 | #define GPIOL_3_CLEAR ( 1 << 19) |
| 937 | #define GPIOL_4_CLEAR ( 1 << 20) |
| 938 | #define GPIOL_5_CLEAR ( 1 << 21) |
| 939 | #define GPIOL_6_CLEAR ( 1 << 22) |
| 940 | #define GPIOL_7_CLEAR ( 1 << 23) |
| 941 | #define GPIOL_8_CLEAR ( 1 << 24) |
| 942 | #define GPIOL_9_CLEAR ( 1 << 25) |
| 943 | #define GPIOL_10_CLEAR ( 1 << 26) |
| 944 | #define GPIOL_11_CLEAR ( 1 << 27) |
| 945 | #define GPIOL_12_CLEAR ( 1 << 28) |
| 946 | #define GPIOL_13_CLEAR ( 1 << 29) |
| 947 | #define GPIOL_14_CLEAR ( 1 << 30) |
| 948 | #define GPIOL_15_CLEAR ( 1 << 31) |
| 949 | |
| 950 | #define GPIOH_16_SET ( 1 << 0) |
| 951 | #define GPIOH_17_SET ( 1 << 1) |
| 952 | #define GPIOH_18_SET ( 1 << 2) |
| 953 | #define GPIOH_19_SET ( 1 << 3) |
| 954 | #define GPIOH_20_SET ( 1 << 4) |
| 955 | #define GPIOH_21_SET ( 1 << 5) |
| 956 | #define GPIOH_22_SET ( 1 << 6) |
| 957 | #define GPIOH_23_SET ( 1 << 7) |
| 958 | #define GPIOH_24_SET ( 1 << 8) |
| 959 | #define GPIOH_25_SET ( 1 << 9) |
| 960 | #define GPIOH_26_SET ( 1 << 10) |
| 961 | #define GPIOH_27_SET ( 1 << 11) |
| 962 | #define GPIOH_28_SET ( 1 << 12) |
| 963 | #define GPIOH_29_SET ( 1 << 13) |
| 964 | #define GPIOH_30_SET ( 1 << 14) |
| 965 | #define GPIOH_31_SET ( 1 << 15) |
| 966 | |
| 967 | #define GPIOH_16_CLEAR ( 1 << 16) |
| 968 | #define GPIOH_17_CLEAR ( 1 << 17) |
| 969 | #define GPIOH_18_CLEAR ( 1 << 18) |
| 970 | #define GPIOH_19_CLEAR ( 1 << 19) |
| 971 | #define GPIOH_20_CLEAR ( 1 << 20) |
| 972 | #define GPIOH_21_CLEAR ( 1 << 21) |
| 973 | #define GPIOH_22_CLEAR ( 1 << 22) |
| 974 | #define GPIOH_23_CLEAR ( 1 << 23) |
| 975 | #define GPIOH_24_CLEAR ( 1 << 24) |
| 976 | #define GPIOH_25_CLEAR ( 1 << 25) |
| 977 | #define GPIOH_26_CLEAR ( 1 << 26) |
| 978 | #define GPIOH_27_CLEAR ( 1 << 27) |
| 979 | #define GPIOH_28_CLEAR ( 1 << 28) |
| 980 | #define GPIOH_29_CLEAR ( 1 << 29) |
| 981 | #define GPIOH_30_CLEAR ( 1 << 30) |
| 982 | #define GPIOH_31_CLEAR ( 1 << 31) |
| 983 | |
| 984 | |
| 985 | /* GPIO LOW Bank Bit Registers*/ |
| 986 | #define GPIOL_OUTPUT_VALUE ( GPIO_BASE + 0x00) |
| 987 | #define GPIOL_OUTPUT_ENABLE ( GPIO_BASE + 0x04) |
| 988 | #define GPIOL_OUT_OPENDRAIN ( GPIO_BASE + 0x08) |
| 989 | #define GPIOL_OUTPUT_INVERT_ENABLE ( GPIO_BASE + 0x0C) |
| 990 | #define GPIOL_OUT_AUX1_SELECT ( GPIO_BASE + 0x10) |
| 991 | #define GPIOL_OUT_AUX2_SELECT ( GPIO_BASE + 0x14) |
| 992 | #define GPIOL_PULLUP_ENABLE ( GPIO_BASE + 0x18) |
| 993 | #define GPIOL_PULLDOWN_ENABLE ( GPIO_BASE + 0x1C) |
| 994 | #define GPIOL_INPUT_ENABLE ( GPIO_BASE + 0x20) |
| 995 | #define GPIOL_INPUT_INVERT_ENABLE ( GPIO_BASE + 0x24) |
| 996 | #define GPIOL_IN_FILTER_ENABLE ( GPIO_BASE + 0x28) |
| 997 | #define GPIOL_IN_EVENTCOUNT_ENABLE ( GPIO_BASE + 0x2C) |
| 998 | #define GPIOL_READ_BACK ( GPIO_BASE + 0x30) |
| 999 | #define GPIOL_IN_AUX1_SELECT ( GPIO_BASE + 0x34) |
| 1000 | #define GPIOL_EVENTS_ENABLE ( GPIO_BASE + 0x38) |
| 1001 | #define GPIOL_LOCK_ENABLE ( GPIO_BASE + 0x3C) |
| 1002 | #define GPIOL_IN_POSEDGE_ENABLE ( GPIO_BASE + 0x40) |
| 1003 | #define GPIOL_IN_NEGEDGE_ENABLE ( GPIO_BASE + 0x44) |
| 1004 | #define GPIOL_IN_POSEDGE_STATUS ( GPIO_BASE + 0x48) |
| 1005 | #define GPIOL_IN_NEGEDGE_STATUS ( GPIO_BASE + 0x4C) |
| 1006 | |
| 1007 | /* GPIO High Bank Bit Registers*/ |
| 1008 | #define GPIOH_OUTPUT_VALUE ( GPIO_BASE + 0x80) |
| 1009 | #define GPIOH_OUTPUT_ENABLE ( GPIO_BASE + 0x84) |
| 1010 | #define GPIOH_OUT_OPENDRAIN ( GPIO_BASE + 0x88) |
| 1011 | #define GPIOH_OUTPUT_INVERT_ENABLE ( GPIO_BASE + 0x8C) |
| 1012 | #define GPIOH_OUT_AUX1_SELECT ( GPIO_BASE + 0x90) |
| 1013 | #define GPIOH_OUT_AUX2_SELECT ( GPIO_BASE + 0x94) |
| 1014 | #define GPIOH_PULLUP_ENABLE ( GPIO_BASE + 0x98) |
| 1015 | #define GPIOH_PULLDOWN_ENABLE ( GPIO_BASE + 0x9C) |
| 1016 | #define GPIOH_INPUT_ENABLE ( GPIO_BASE + 0x0A0) |
| 1017 | #define GPIOH_INPUT_INVERT_ENABLE ( GPIO_BASE + 0x0A4) |
| 1018 | #define GPIOH_IN_FILTER_ENABLE ( GPIO_BASE + 0x0A8) |
| 1019 | #define GPIOH_IN_EVENTCOUNT_ENABLE ( GPIO_BASE + 0x0AC) |
| 1020 | #define GPIOH_READ_BACK ( GPIO_BASE + 0x0B0) |
| 1021 | #define GPIOH_IN_AUX1_SELECT ( GPIO_BASE + 0x0B4) |
| 1022 | #define GPIOH_EVENTS_ENABLE ( GPIO_BASE + 0x0B8) |
| 1023 | #define GPIOH_LOCK_ENABLE ( GPIO_BASE + 0x0BC) |
| 1024 | #define GPIOH_IN_POSEDGE_ENABLE ( GPIO_BASE + 0x0C0) |
| 1025 | #define GPIOH_IN_NEGEDGE_ENABLE ( GPIO_BASE + 0x0C4) |
| 1026 | #define GPIOH_IN_POSEDGE_STATUS ( GPIO_BASE + 0x0C8) |
| 1027 | #define GPIOH_IN_NEGEDGE_STATUS ( GPIO_BASE + 0x0CC) |
| 1028 | |
| 1029 | /* Input Conditioning Function Registers*/ |
| 1030 | #define GPIO_00_FILTER_AMOUNT ( GPIO_BASE + 0x50) |
| 1031 | #define GPIO_00_FILTER_COUNT ( GPIO_BASE + 0x52) |
| 1032 | #define GPIO_00_EVENT_COUNT ( GPIO_BASE + 0x54) |
| 1033 | #define GPIO_00_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x56) |
| 1034 | #define GPIO_01_FILTER_AMOUNT ( GPIO_BASE + 0x58) |
| 1035 | #define GPIO_01_FILTER_COUNT ( GPIO_BASE + 0x5A) |
| 1036 | #define GPIO_01_EVENT_COUNT ( GPIO_BASE + 0x5C) |
| 1037 | #define GPIO_01_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x5E) |
| 1038 | #define GPIO_02_FILTER_AMOUNT ( GPIO_BASE + 0x60) |
| 1039 | #define GPIO_02_FILTER_COUNT ( GPIO_BASE + 0x62) |
| 1040 | #define GPIO_02_EVENT_COUNT ( GPIO_BASE + 0x64) |
| 1041 | #define GPIO_02_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x66) |
| 1042 | #define GPIO_03_FILTER_AMOUNT ( GPIO_BASE + 0x68) |
| 1043 | #define GPIO_03_FILTER_COUNT ( GPIO_BASE + 0x6A) |
| 1044 | #define GPIO_03_EVENT_COUNT ( GPIO_BASE + 0x6C) |
| 1045 | #define GPIO_03_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x6E) |
| 1046 | #define GPIO_04_FILTER_AMOUNT ( GPIO_BASE + 0x70) |
| 1047 | #define GPIO_04_FILTER_COUNT ( GPIO_BASE + 0x72) |
| 1048 | #define GPIO_04_EVENT_COUNT ( GPIO_BASE + 0x74) |
| 1049 | #define GPIO_04_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x76) |
| 1050 | #define GPIO_05_FILTER_AMOUNT ( GPIO_BASE + 0x78) |
| 1051 | #define GPIO_05_FILTER_COUNT ( GPIO_BASE + 0x7A) |
| 1052 | #define GPIO_05_EVENT_COUNT ( GPIO_BASE + 0x7C) |
| 1053 | #define GPIO_05_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x7E) |
| 1054 | #define GPIO_06_FILTER_AMOUNT ( GPIO_BASE + 0x0D0) |
| 1055 | #define GPIO_06_FILTER_COUNT ( GPIO_BASE + 0x0D2) |
| 1056 | #define GPIO_06_EVENT_COUNT ( GPIO_BASE + 0x0D4) |
| 1057 | #define GPIO_06_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x0D6) |
| 1058 | #define GPIO_07_FILTER_AMOUNT ( GPIO_BASE + 0x0D8) |
| 1059 | #define GPIO_07_FILTER_COUNT ( GPIO_BASE + 0x0DA) |
| 1060 | #define GPIO_07_EVENT_COUNT ( GPIO_BASE + 0x0DC) |
| 1061 | #define GPIO_07_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x0DE) |
| 1062 | |
| 1063 | /* R/W GPIO Interrupt &PME Mapper Registers*/ |
| 1064 | #define GPIO_MAPPER_X ( GPIO_BASE + 0x0E0) |
| 1065 | #define GPIO_MAPPER_Y ( GPIO_BASE + 0x0E4) |
| 1066 | #define GPIO_MAPPER_Z ( GPIO_BASE + 0x0E8) |
| 1067 | #define GPIO_MAPPER_W ( GPIO_BASE + 0x0EC) |
| 1068 | #define GPIO_FE_SELECT_0 ( GPIO_BASE + 0x0F0) |
| 1069 | #define GPIO_FE_SELECT_1 ( GPIO_BASE + 0x0F1) |
| 1070 | #define GPIO_FE_SELECT_2 ( GPIO_BASE + 0x0F2) |
| 1071 | #define GPIO_FE_SELECT_3 ( GPIO_BASE + 0x0F3) |
| 1072 | #define GPIO_FE_SELECT_4 ( GPIO_BASE + 0x0F4) |
| 1073 | #define GPIO_FE_SELECT_5 ( GPIO_BASE + 0x0F5) |
| 1074 | #define GPIO_FE_SELECT_6 ( GPIO_BASE + 0x0F6) |
| 1075 | #define GPIO_FE_SELECT_7 ( GPIO_BASE + 0x0F7) |
| 1076 | |
| 1077 | /* Event Counter Decrement Registers*/ |
| 1078 | #define GPIOL_IN_EVENT_DECREMENT ( GPIO_BASE + 0x0F8) |
| 1079 | #define GPIOH_IN_EVENT_DECREMENT ( GPIO_BASE + 0x0FC) |
| 1080 | |
| 1081 | /* This is for 286reset compatibility. 0xCange to mat0xc 5535 virtualized stuff.*/ |
| 1082 | #define FUNC0 ( 0x90) |
| 1083 | |
| 1084 | |
| 1085 | /* sworley, PMC register*/ |
| 1086 | #define PM_SSD ( PMLogic_BASE + 0x00) |
| 1087 | #define PM_SCXA ( PMLogic_BASE + 0x04) |
| 1088 | #define PM_SCYA ( PMLogic_BASE + 0x08) |
| 1089 | #define PM_SODA ( PMLogic_BASE + 0x0C) |
| 1090 | #define PM_SCLK ( PMLogic_BASE + 0x10) |
| 1091 | #define PM_SED ( PMLogic_BASE + 0x14) |
| 1092 | #define PM_SCXD ( PMLogic_BASE + 0x18) |
| 1093 | #define PM_SCYD ( PMLogic_BASE + 0x1C) |
| 1094 | #define PM_SIDD ( PMLogic_BASE + 0x20) |
| 1095 | #define PM_WKD ( PMLogic_BASE + 0x30) |
| 1096 | #define PM_WKXD ( PMLogic_BASE + 0x34) |
| 1097 | #define PM_RD ( PMLogic_BASE + 0x38) |
| 1098 | #define PM_WKXA ( PMLogic_BASE + 0x3C) |
| 1099 | #define PM_FSD ( PMLogic_BASE + 0x40) |
| 1100 | #define PM_TSD ( PMLogic_BASE + 0x44) |
| 1101 | #define PM_PSD ( PMLogic_BASE + 0x48) |
| 1102 | #define PM_NWKD ( PMLogic_BASE + 0x4C) |
| 1103 | #define PM_AWKD ( PMLogic_BASE + 0x50) |
| 1104 | #define PM_SSC ( PMLogic_BASE + 0x54) |
| 1105 | |
| 1106 | |
| 1107 | /* FLASH device macros */ |
| 1108 | #define FLASH_TYPE_NONE 0 /* No flash device installed */ |
| 1109 | #define FLASH_TYPE_NAND 1 /* NAND device */ |
| 1110 | #define FLASH_TYPE_NOR 2 /* NOR device */ |
| 1111 | |
| 1112 | #define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */ |
| 1113 | #define FLASH_IF_IO 2 /* I/O interface for Flash device */ |
| 1114 | |
| 1115 | /* Flash Memory Mask values */ |
| 1116 | #define FLASH_MEM_DEFAULT 0x00000000 |
| 1117 | #define FLASH_MEM_4K 0xFFFFF000 |
| 1118 | #define FLASH_MEM_8K 0xFFFFE000 |
| 1119 | #define FLASH_MEM_16K 0xFFFFC000 |
| 1120 | #define FLASH_MEM_128K 0xFFFE0000 |
| 1121 | #define FLASH_MEM_512K 0xFFFC0000 |
| 1122 | #define FLASH_MEM_4M 0xFFC00000 |
| 1123 | #define FLASH_MEM_8M 0xFF800000 |
| 1124 | #define FLASH_MEM_16M 0xFF000000 |
| 1125 | |
| 1126 | /* Flash IO Mask values */ |
| 1127 | #define FLASH_IO_DEFAULT 0x00000000 |
| 1128 | #define FLASH_IO_16B 0x0000FFF0 |
| 1129 | #define FLASH_IO_32B 0x0000FFE0 |
| 1130 | #define FLASH_IO_64B 0x0000FFC0 |
| 1131 | #define FLASH_IO_128B 0x0000FF80 |
| 1132 | #define FLASH_IO_256B 0x0000FF00 |
| 1133 | |
| 1134 | |
| 1135 | |
| 1136 | #endif /* CPU_AMD_LXDEF_H */ |