blob: 84d6982968cd59c1dd0a2ec5b5747c7f9814317a [file] [log] [blame]
Angel Ponsae593872020-04-04 18:50:57 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Martin Roth5c354b92019-04-22 14:55:16 -06002
3#include <console/uart.h>
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -06004#include <commonlib/helpers.h>
Julius Werner55009af2019-12-02 22:03:27 -08005#include <device/mmio.h>
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -06006#include <amdblocks/gpio_banks.h>
7#include <amdblocks/acpimmio.h>
Martin Roth5c354b92019-04-22 14:55:16 -06008#include <soc/southbridge.h>
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -06009#include <soc/gpio.h>
10
11static const struct _uart_info {
12 uintptr_t base;
13 struct soc_amd_gpio mux[2];
14} uart_info[] = {
15 [0] = { APU_UART0_BASE, {
16 PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
17 PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
18 } },
19 [1] = { APU_UART1_BASE, {
20 PAD_NF(GPIO_143, UART1_TXD, PULL_NONE),
21 PAD_NF(GPIO_141, UART1_RXD, PULL_NONE),
22 } },
23 [2] = { APU_UART2_BASE, {
24 PAD_NF(GPIO_137, UART2_TXD, PULL_NONE),
25 PAD_NF(GPIO_135, UART2_RXD, PULL_NONE),
26 } },
27 [3] = { APU_UART3_BASE, {
28 PAD_NF(GPIO_140, UART3_TXD, PULL_NONE),
29 PAD_NF(GPIO_142, UART3_RXD, PULL_NONE),
30 } },
31};
Martin Roth5c354b92019-04-22 14:55:16 -060032
33uintptr_t uart_platform_base(int idx)
34{
Felix Heldefd23d92020-06-10 19:39:51 +020035 if (idx < 0 || idx >= ARRAY_SIZE(uart_info))
Martin Roth5c354b92019-04-22 14:55:16 -060036 return 0;
37
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -060038 return uart_info[idx].base;
39}
40
41void set_uart_config(int idx)
42{
43 uint32_t uart_ctrl;
44 uint16_t uart_leg;
45
Felix Heldefd23d92020-06-10 19:39:51 +020046 if (idx < 0 || idx >= ARRAY_SIZE(uart_info))
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -060047 return;
48
49 program_gpios(uart_info[idx].mux, 2);
50
51 if (CONFIG(PICASSO_UART_1_8MZ)) {
52 uart_ctrl = sm_pci_read32(SMB_UART_CONFIG);
53 uart_ctrl |= 1 << (SMB_UART_1_8M_SHIFT + idx);
54 sm_pci_write32(SMB_UART_CONFIG, uart_ctrl);
55 }
56
57 if (CONFIG(PICASSO_UART_LEGACY) && idx != 3) {
58 /* Force 3F8 if idx=0, 2F8 if idx=1, 3E8 if idx=2 */
59
60 /* TODO: make clearer once PPR is updated */
61 uart_leg = (idx << 8) | (idx << 10) | (idx << 12) | (idx << 14);
62 if (idx == 0)
63 uart_leg |= 1 << FCH_LEGACY_3F8_SH;
64 else if (idx == 1)
65 uart_leg |= 1 << FCH_LEGACY_2F8_SH;
66 else if (idx == 2)
67 uart_leg |= 1 << FCH_LEGACY_3E8_SH;
68
69 write16((void *)FCH_UART_LEGACY_DECODE, uart_leg);
70 }
Martin Roth5c354b92019-04-22 14:55:16 -060071}
72
73unsigned int uart_platform_refclk(void)
74{
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -060075 return CONFIG(PICASSO_UART_48MZ) ? 48000000 : 115200 * 16;
Martin Roth5c354b92019-04-22 14:55:16 -060076}
Furquan Shaikhb07e2622020-06-03 16:50:32 -070077
78static const char *uart_acpi_name(const struct device *dev)
79{
80 switch (dev->path.mmio.addr) {
81 case APU_UART0_BASE:
82 return "FUR0";
83 case APU_UART1_BASE:
84 return "FUR1";
85 case APU_UART2_BASE:
86 return "FUR2";
87 case APU_UART3_BASE:
88 return "FUR3";
89 default:
90 return NULL;
91 }
92}
93
94struct device_operations picasso_uart_mmio_ops = {
95 .read_resources = noop_read_resources,
96 .set_resources = noop_set_resources,
97 .scan_bus = scan_static_bus,
98 .acpi_name = uart_acpi_name,
99};