Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ALDERLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Alderlake support |
| 5 | |
| 6 | if SOC_INTEL_ALDERLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ARCH_BOOTBLOCK_X86_32 |
| 11 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 13 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 14 | select IDT_IN_EVERY_STAGE |
| 15 | select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED |
| 16 | select MICROCODE_BLOB_UNDISCLOSED |
| 17 | select SOC_INTEL_COMMON |
| 18 | select SOC_INTEL_COMMON_BLOCK |
| 19 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 20 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 21 | select SOC_INTEL_COMMON_BLOCK_SA |
| 22 | select SOC_INTEL_COMMON_PCH_BASE |
| 23 | select SOC_INTEL_COMMON_RESET |
| 24 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 25 | select SSE2 |
| 26 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 27 | select TSC_MONOTONIC_TIMER |
| 28 | select UDELAY_TSC |
| 29 | |
| 30 | config DCACHE_RAM_BASE |
| 31 | default 0xfef00000 |
| 32 | |
| 33 | config DCACHE_RAM_SIZE |
| 34 | default 0x80000 |
| 35 | help |
| 36 | The size of the cache-as-ram region required during bootblock |
| 37 | and/or romstage. |
| 38 | |
| 39 | config DCACHE_BSP_STACK_SIZE |
| 40 | hex |
| 41 | default 0x40400 |
| 42 | help |
| 43 | The amount of anticipated stack usage in CAR by bootblock and |
| 44 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 45 | sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement |
| 46 | (~1KiB). |
| 47 | |
| 48 | config FSP_TEMP_RAM_SIZE |
| 49 | hex |
| 50 | default 0x20000 |
| 51 | help |
| 52 | The amount of anticipated heap usage in CAR by FSP. |
| 53 | Refer to Platform FSP integration guide document to know |
| 54 | the exact FSP requirement for Heap setup. |
| 55 | |
| 56 | config IFD_CHIPSET |
| 57 | string |
| 58 | default "adl" |
| 59 | |
| 60 | config IED_REGION_SIZE |
| 61 | hex |
| 62 | default 0x400000 |
| 63 | |
| 64 | config HEAP_SIZE |
| 65 | hex |
| 66 | default 0x10000 |
| 67 | |
| 68 | config PCR_BASE_ADDRESS |
| 69 | hex |
| 70 | default 0xfd000000 |
| 71 | help |
| 72 | This option allows you to select MMIO Base Address of sideband bus. |
| 73 | |
| 74 | config MMCONF_BASE_ADDRESS |
| 75 | hex |
| 76 | default 0xc0000000 |
| 77 | |
| 78 | config CPU_BCLK_MHZ |
| 79 | int |
| 80 | default 100 |
| 81 | |
| 82 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 83 | int |
| 84 | default 120 |
| 85 | |
| 86 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 87 | int |
| 88 | default 133 |
| 89 | |
| 90 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 91 | int |
| 92 | default 7 |
| 93 | |
| 94 | config SOC_INTEL_I2C_DEV_MAX |
| 95 | int |
| 96 | default 6 |
| 97 | |
| 98 | config SOC_INTEL_UART_DEV_MAX |
| 99 | int |
| 100 | default 7 |
| 101 | |
| 102 | config CONSOLE_UART_BASE_ADDRESS |
| 103 | hex |
| 104 | default 0xfe032000 |
| 105 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 106 | |
| 107 | # Clock divider parameters for 115200 baud rate |
| 108 | # Baudrate = (UART source clcok * M) /(N *16) |
| 109 | # ADL UART source clock: 120MHz |
| 110 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 111 | hex |
| 112 | default 0x25a |
| 113 | |
| 114 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 115 | hex |
| 116 | default 0x7fff |
| 117 | |
| 118 | config CHROMEOS |
| 119 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 120 | |
| 121 | config C_ENV_BOOTBLOCK_SIZE |
| 122 | hex |
| 123 | default 0xC000 |
| 124 | |
| 125 | config CBFS_SIZE |
| 126 | hex |
| 127 | default 0x200000 |
| 128 | |
| 129 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 130 | hex |
| 131 | default 0x1400 |
| 132 | endif |