Angel Pons | feedf23 | 2020-04-05 13:22:01 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 2 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 3 | #include <device/pci_ops.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 4 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 5 | #include <northbridge/intel/sandybridge/raminit.h> |
Patrick Rudolph | da9302a | 2019-03-24 17:01:41 +0100 | [diff] [blame] | 6 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 7 | #include <southbridge/intel/common/gpio.h> |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 8 | #include "ec/google/chromeec/ec.h" |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 9 | |
| 10 | #include <southbridge/intel/bd82x6x/chip.h> |
| 11 | |
Arthur Heymans | 2b28a16 | 2019-11-12 17:21:08 +0100 | [diff] [blame] | 12 | void mainboard_pch_lpc_setup(void) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 13 | { |
Nico Huber | e036aae | 2019-11-17 01:24:44 +0100 | [diff] [blame] | 14 | /* Enable additional 0x200..0x207 for EC */ |
| 15 | pci_or_config16(PCH_LPC_DEV, LPC_EN, GAMEL_LPC_EN); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 16 | } |
| 17 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 18 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 19 | { |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 20 | /* |
| 21 | * GFX INTA -> PIRQA (MSI) |
| 22 | * D28IP_P3IP WLAN INTA -> PIRQB |
| 23 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 24 | * D26IP_E2P EHCI2 INTA -> PIRQF |
| 25 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 26 | * D31IP_SMIP SMBUS INTB -> PIRQH |
| 27 | * D31IP_TTIP THRT INTC -> PIRQA |
| 28 | * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| 29 | * |
| 30 | * TRACKPAD -> PIRQE (Edge Triggered) |
| 31 | * TOUCHSCREEN -> PIRQG (Edge Triggered) |
| 32 | */ |
| 33 | |
| 34 | /* Device interrupt pin register (board specific) */ |
| 35 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 36 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 37 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 38 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 39 | RCBA32(D28IP) = (INTA << D28IP_P3IP); |
| 40 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 41 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 42 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 43 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 44 | |
| 45 | /* Device interrupt route registers */ |
| 46 | DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| 47 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 48 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 49 | DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| 50 | DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| 51 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 52 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 53 | } |
| 54 | |
Keith Hui | 45e4ab4 | 2023-07-22 12:49:05 -0400 | [diff] [blame] | 55 | static unsigned int get_spd_index(void) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 56 | { |
| 57 | const int gpio_vector[] = {41, 42, 43, 10, -1}; |
Keith Hui | 45e4ab4 | 2023-07-22 12:49:05 -0400 | [diff] [blame] | 58 | return get_gpios(gpio_vector); |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 59 | } |
| 60 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 61 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 62 | { |
Keith Hui | 7039edd | 2023-07-21 10:12:05 -0400 | [diff] [blame] | 63 | /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 64 | } |
| 65 | |
| 66 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
Elyes HAOUAS | 44f558e | 2020-02-24 13:26:04 +0100 | [diff] [blame] | 67 | /* enabled power USB oc pin */ |
Vladimir Serbinenko | b2ad810 | 2016-02-10 03:07:42 +0100 | [diff] [blame] | 68 | { 0, 0, -1 }, /* P0: Empty */ |
| 69 | { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ |
| 70 | { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ |
| 71 | { 1, 0, -1 }, /* P3: SDCARD (no OC) */ |
| 72 | { 0, 0, -1 }, /* P4: Empty */ |
| 73 | { 1, 0, -1 }, /* P5: WWAN (no OC) */ |
| 74 | { 0, 0, -1 }, /* P6: Empty */ |
| 75 | { 0, 0, -1 }, /* P7: Empty */ |
| 76 | { 1, 0, -1 }, /* P8: Camera (no OC) */ |
| 77 | { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ |
| 78 | { 0, 0, -1 }, /* P10: Empty */ |
| 79 | { 0, 0, -1 }, /* P11: Empty */ |
| 80 | { 0, 0, -1 }, /* P12: Empty */ |
| 81 | { 0, 0, -1 }, /* P13: Empty */ |
| 82 | }; |
| 83 | |
Keith Hui | 45e4ab4 | 2023-07-22 12:49:05 -0400 | [diff] [blame] | 84 | void mb_get_spd_map(struct spd_info *spdi) |
Peter Lemenkov | 498f1cc | 2019-02-07 10:48:10 +0100 | [diff] [blame] | 85 | { |
Keith Hui | 45e4ab4 | 2023-07-22 12:49:05 -0400 | [diff] [blame] | 86 | /* LINK has 2 channels of memory down */ |
| 87 | spdi->addresses[0] = SPD_MEMORY_DOWN; |
| 88 | spdi->addresses[2] = SPD_MEMORY_DOWN; |
| 89 | spdi->spd_index = get_spd_index(); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 90 | } |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 91 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 92 | void mainboard_early_init(int s3resume) |
| 93 | { |
| 94 | if (!s3resume) { |
Stefan Reinauer | 49428d8 | 2013-02-21 15:48:37 -0800 | [diff] [blame] | 95 | /* This is the fastest way to let users know |
| 96 | * the Intel CPU is now alive. |
| 97 | */ |
| 98 | google_chromeec_kbbacklight(100); |
| 99 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 100 | } |