commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da
author Keith Hui <buurin@gmail.com> Sat Jul 22 12:49:05 2023 -0400
committer Felix Held <felix-coreboot@felixheld.de> Mon Nov 13 20:31:23 2023 +0000
tree 8b0fb3b07ecb3cfa84aa77b51c0e1053a1415c73
parent 940fe080bf1ed2dac827b569c70fb0ea11496041

mb/*: Update SPD mapping for sandybridge boards

Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.

Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.

Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

src/mainboard/google/link/early_init.c

diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c
index a4127f1..e40531d 100644
--- a/src/mainboard/google/link/early_init.c
+++ b/src/mainboard/google/link/early_init.c
@@ -1,17 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
-#include <stdint.h>
-#include <string.h>
 #include <device/pci_ops.h>
-#include <console/console.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 #include "ec/google/chromeec/ec.h"
-#include <cbfs.h>
 
 #include <southbridge/intel/bd82x6x/chip.h>
 
@@ -58,39 +52,15 @@
 	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
 }
 
-static uint8_t *locate_spd(void)
+static unsigned int get_spd_index(void)
 {
 	const int gpio_vector[] = {41, 42, 43, 10, -1};
-	uint8_t *spd_file;
-	size_t spd_file_len;
-	int spd_index = get_gpios(gpio_vector);
-
-	printk(BIOS_DEBUG, "spd index %d\n", spd_index);
-	spd_file = cbfs_map("spd.bin", &spd_file_len);
-	if (!spd_file)
-		die("SPD data not found.");
-
-	if (spd_file_len < ((spd_index + 1) * 256)) {
-		printk(BIOS_ERR, "spd index override to 0 - old hardware?\n");
-		spd_index = 0;
-	}
-
-	if (spd_file_len < 256)
-		die("Missing SPD data.");
-
-	return spd_file + spd_index * 256;
+	return get_gpios(gpio_vector);
 }
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
-
-	/* LINK has 2 channels of memory down, so spd_data[0] and [2]
-	   both need to be populated */
-	memcpy(pei_data->spd_data[0], locate_spd(),
-	       sizeof(pei_data->spd_data[0]));
-	memcpy(pei_data->spd_data[2], pei_data->spd_data[0],
-	       sizeof(pei_data->spd_data[0]));
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
@@ -111,12 +81,12 @@
 	{ 0, 0, -1 }, /* P13: Empty */
 };
 
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+void mb_get_spd_map(struct spd_info *spdi)
 {
-	/* LINK has 2 channels of memory down, so spd_data[0] and [2]
-	   both need to be populated */
-	memcpy(&spd[0], locate_spd(), 128);
-	memcpy(&spd[2], &spd[0], 128);
+	/* LINK has 2 channels of memory down */
+	spdi->addresses[0] = SPD_MEMORY_DOWN;
+	spdi->addresses[2] = SPD_MEMORY_DOWN;
+	spdi->spd_index = get_spd_index();
 }
 
 void mainboard_early_init(int s3resume)