Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
| 5 | #include <cpu/x86/msr.h> |
Meera Ravindranath | 3b03798 | 2021-11-11 18:02:13 +0530 | [diff] [blame] | 6 | #include <cpu/intel/cpu_ids.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 7 | #include <device/device.h> |
Tim Wawrzynczak | 6f73a20 | 2022-02-04 12:45:37 -0700 | [diff] [blame] | 8 | #include <drivers/wifi/generic/wifi.h> |
Subrata Banik | 7cb6d72 | 2022-03-23 01:33:27 +0530 | [diff] [blame] | 9 | #include <fsp/fsp_debug_event.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 10 | #include <fsp/util.h> |
| 11 | #include <intelblocks/cpulib.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 12 | #include <intelblocks/pcie_rp.h> |
Felix Singer | a182fae | 2021-12-31 00:30:55 +0100 | [diff] [blame] | 13 | #include <option.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 14 | #include <soc/gpio_soc_defs.h> |
| 15 | #include <soc/iomap.h> |
| 16 | #include <soc/msr.h> |
| 17 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 18 | #include <soc/pcie.h> |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 19 | #include <soc/romstage.h> |
| 20 | #include <soc/soc_chip.h> |
| 21 | #include <string.h> |
| 22 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 23 | #define FSP_CLK_NOTUSED 0xFF |
| 24 | #define FSP_CLK_LAN 0x70 |
| 25 | #define FSP_CLK_FREE_RUNNING 0x80 |
| 26 | |
| 27 | #define CPU_PCIE_BASE 0x40 |
| 28 | |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 29 | enum vtd_base_index_type { |
| 30 | VTD_GFX, |
| 31 | VTD_IPU, |
| 32 | VTD_VTVCO, |
Sridhar Siricilla | d047927 | 2021-05-28 20:00:02 +0530 | [diff] [blame] | 33 | VTD_TBT0, |
| 34 | VTD_TBT1, |
| 35 | VTD_TBT2, |
| 36 | VTD_TBT3, |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 37 | }; |
| 38 | |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 39 | static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number) |
| 40 | { |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 41 | assert(type == PCIE_RP_PCH || type == PCIE_RP_CPU); |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 42 | |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 43 | if (type == PCIE_RP_PCH) |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 44 | return rp_number; |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 45 | else // type == PCIE_RP_CPU |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 46 | return CPU_PCIE_BASE + rp_number; |
| 47 | } |
| 48 | |
| 49 | static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_type type, |
| 50 | const struct pcie_rp_config *cfg, size_t cfg_count) |
| 51 | { |
| 52 | size_t i; |
Kane Chen | ff553ba | 2021-12-16 17:46:33 +0800 | [diff] [blame] | 53 | /* bitmask to save the status of clkreq assignment */ |
| 54 | static unsigned int clk_req_mapping = 0; |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 55 | |
| 56 | for (i = 0; i < cfg_count; i++) { |
| 57 | if (!(en_mask & BIT(i))) |
| 58 | continue; |
| 59 | if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) |
| 60 | continue; |
Cliff Huang | edf71a0 | 2022-04-28 18:55:48 -0700 | [diff] [blame^] | 61 | if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) { |
| 62 | printk(BIOS_WARNING, "Missing root port clock structure definition\n"); |
| 63 | continue; |
| 64 | } |
Kane Chen | ff553ba | 2021-12-16 17:46:33 +0800 | [diff] [blame] | 65 | if (clk_req_mapping & (1 << cfg[i].clk_req)) |
| 66 | printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n" |
| 67 | , cfg[i].clk_req); |
| 68 | if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 69 | m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; |
Kane Chen | ff553ba | 2021-12-16 17:46:33 +0800 | [diff] [blame] | 70 | clk_req_mapping |= 1 << cfg[i].clk_req; |
| 71 | } |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 72 | m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i); |
| 73 | } |
| 74 | } |
| 75 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 76 | static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg, |
| 77 | const struct soc_intel_alderlake_config *config) |
| 78 | { |
| 79 | /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ |
| 80 | unsigned int i; |
| 81 | |
| 82 | for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) { |
| 83 | if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) |
| 84 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; |
| 85 | else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) |
| 86 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; |
| 87 | else |
| 88 | m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; |
| 89 | m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; |
| 90 | } |
| 91 | |
| 92 | /* Configure PCH PCIE ports */ |
| 93 | m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 94 | pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCIE_RP_PCH, config->pch_pcie_rp, |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 95 | CONFIG_MAX_PCH_ROOT_PORTS); |
| 96 | |
| 97 | /* Configure CPU PCIE ports */ |
| 98 | m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); |
Tim Wawrzynczak | 461ff1d | 2021-12-02 16:16:48 -0700 | [diff] [blame] | 99 | pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, PCIE_RP_CPU, config->cpu_pcie_rp, |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 100 | CONFIG_MAX_CPU_ROOT_PORTS); |
| 101 | } |
| 102 | |
| 103 | static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg, |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 104 | const struct soc_intel_alderlake_config *config) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 105 | { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 106 | unsigned int i; |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 107 | const struct ddi_port_upds { |
| 108 | uint8_t *ddc; |
| 109 | uint8_t *hpd; |
| 110 | } ddi_port_upds[] = { |
| 111 | [DDI_PORT_A] = {&m_cfg->DdiPortADdc, &m_cfg->DdiPortAHpd}, |
| 112 | [DDI_PORT_B] = {&m_cfg->DdiPortBDdc, &m_cfg->DdiPortBHpd}, |
| 113 | [DDI_PORT_C] = {&m_cfg->DdiPortCDdc, &m_cfg->DdiPortCHpd}, |
| 114 | [DDI_PORT_1] = {&m_cfg->DdiPort1Ddc, &m_cfg->DdiPort1Hpd}, |
| 115 | [DDI_PORT_2] = {&m_cfg->DdiPort2Ddc, &m_cfg->DdiPort2Hpd}, |
| 116 | [DDI_PORT_3] = {&m_cfg->DdiPort3Ddc, &m_cfg->DdiPort3Hpd}, |
| 117 | [DDI_PORT_4] = {&m_cfg->DdiPort4Ddc, &m_cfg->DdiPort4Hpd}, |
| 118 | }; |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 119 | m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD); |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 120 | if (m_cfg->InternalGfx) { |
| 121 | /* IGD is enabled, set IGD stolen size to 60MB. */ |
| 122 | m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB; |
| 123 | /* DP port config */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 124 | m_cfg->DdiPortAConfig = config->ddi_portA_config; |
| 125 | m_cfg->DdiPortBConfig = config->ddi_portB_config; |
Subrata Banik | 8a18bd8 | 2021-06-09 21:57:49 +0530 | [diff] [blame] | 126 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 127 | *ddi_port_upds[i].ddc = !!(config->ddi_ports_config[i] & |
| 128 | DDI_ENABLE_DDC); |
| 129 | *ddi_port_upds[i].hpd = !!(config->ddi_ports_config[i] & |
| 130 | DDI_ENABLE_HPD); |
| 131 | } |
| 132 | } else { |
| 133 | /* IGD is disabled, skip IGD init in FSP. */ |
| 134 | m_cfg->IgdDvmt50PreAlloc = 0; |
| 135 | /* DP port config */ |
| 136 | m_cfg->DdiPortAConfig = 0; |
| 137 | m_cfg->DdiPortBConfig = 0; |
| 138 | for (i = 0; i < ARRAY_SIZE(ddi_port_upds); i++) { |
| 139 | *ddi_port_upds[i].ddc = 0; |
| 140 | *ddi_port_upds[i].hpd = 0; |
| 141 | } |
| 142 | } |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 143 | } |
| 144 | static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, |
| 145 | const struct soc_intel_alderlake_config *config) |
| 146 | { |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 147 | m_cfg->SaGv = config->sagv; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 148 | m_cfg->RMT = config->RMT; |
Scott Chao | ab638c1 | 2022-04-20 15:16:06 +0800 | [diff] [blame] | 149 | if (config->max_dram_speed_mts) |
| 150 | m_cfg->DdrFreqLimit = config->max_dram_speed_mts; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 151 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 152 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 153 | static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, |
| 154 | const struct soc_intel_alderlake_config *config) |
| 155 | { |
| 156 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 157 | /* CpuRatio Settings */ |
| 158 | if (config->cpu_ratio_override) |
| 159 | m_cfg->CpuRatio = config->cpu_ratio_override; |
| 160 | else |
| 161 | /* Set CpuRatio to match existing MSR value */ |
| 162 | m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; |
| 163 | |
Subrata Banik | 80835a1 | 2020-09-23 17:46:11 +0530 | [diff] [blame] | 164 | m_cfg->PrmrrSize = get_valid_prmrr_size(); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 165 | m_cfg->EnableC6Dram = config->enable_c6dram; |
Felix Singer | a182fae | 2021-12-31 00:30:55 +0100 | [diff] [blame] | 166 | m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, |
| 170 | const struct soc_intel_alderlake_config *config) |
| 171 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 172 | /* Disable BIOS Guard */ |
| 173 | m_cfg->BiosGuard = 0; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 174 | m_cfg->TmeEnable = CONFIG(INTEL_TME); |
| 175 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 176 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 177 | static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, |
| 178 | const struct soc_intel_alderlake_config *config) |
| 179 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 180 | /* UART Debug Log */ |
| 181 | m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? |
| 182 | DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; |
| 183 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 184 | m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; |
| 185 | m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; |
| 186 | m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 187 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 188 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 189 | static void fill_fspm_ipu_params(FSP_M_CONFIG *m_cfg, |
| 190 | const struct soc_intel_alderlake_config *config) |
| 191 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 192 | /* Image clock: disable all clocks for bypassing FSP pin mux */ |
| 193 | memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 194 | /* IPU */ |
| 195 | m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU); |
| 196 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 197 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 198 | static void fill_fspm_smbus_params(FSP_M_CONFIG *m_cfg, |
| 199 | const struct soc_intel_alderlake_config *config) |
| 200 | { |
| 201 | m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS); |
| 202 | } |
| 203 | |
| 204 | static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, |
| 205 | const struct soc_intel_alderlake_config *config) |
| 206 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 207 | /* Disable Lock PCU Thermal Management registers */ |
| 208 | m_cfg->LockPTMregs = 0; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 209 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 210 | /* Skip CPU replacement check */ |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 211 | m_cfg->SkipCpuReplacementCheck = !config->cpu_replacement_check; |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 212 | |
| 213 | /* Skip GPIO configuration from FSP */ |
| 214 | m_cfg->GpioOverride = 0x1; |
MAULIK V VAGHELA | 9a7fbbc | 2021-10-13 11:52:17 +0530 | [diff] [blame] | 215 | |
Ronak Kanabar | fc69b9d | 2021-10-06 13:02:34 +0530 | [diff] [blame] | 216 | /* CNVi DDR RFI Mitigation */ |
Tim Wawrzynczak | 6f73a20 | 2022-02-04 12:45:37 -0700 | [diff] [blame] | 217 | const struct device_path path[] = { |
| 218 | { .type = DEVICE_PATH_PCI, .pci.devfn = PCH_DEVFN_CNVI_WIFI }, |
| 219 | { .type = DEVICE_PATH_GENERIC, .generic.id = 0 } }; |
| 220 | const struct device *dev = find_dev_nested_path(pci_root_bus(), path, |
| 221 | ARRAY_SIZE(path)); |
| 222 | if (is_dev_enabled(dev)) |
| 223 | m_cfg->CnviDdrRfim = wifi_generic_cnvi_ddr_rfim_enabled(dev); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, |
| 227 | const struct soc_intel_alderlake_config *config) |
| 228 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 229 | /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 230 | m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA); |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 231 | m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable; |
| 232 | m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; |
| 233 | m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; |
| 234 | m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; |
Furquan Shaikh | c1c1ba5 | 2021-04-20 16:57:59 -0700 | [diff] [blame] | 235 | /* |
| 236 | * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to |
| 237 | * configure GPIO pads for audio. Mainboard is expected to perform all GPIO |
| 238 | * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO |
| 239 | * configuration for audio pads. |
| 240 | */ |
| 241 | m_cfg->PchHdaAudioLinkHdaEnable = 0; |
| 242 | memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); |
| 243 | memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); |
| 244 | memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 245 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 246 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 247 | static void fill_fspm_ish_params(FSP_M_CONFIG *m_cfg, |
| 248 | const struct soc_intel_alderlake_config *config) |
| 249 | { |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 250 | m_cfg->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 251 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 252 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 253 | static void fill_fspm_tcss_params(FSP_M_CONFIG *m_cfg, |
| 254 | const struct soc_intel_alderlake_config *config) |
| 255 | { |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 256 | /* Tcss USB */ |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 257 | m_cfg->TcssXhciEn = is_devfn_enabled(SA_DEVFN_TCSS_XHCI); |
| 258 | m_cfg->TcssXdciEn = is_devfn_enabled(SA_DEVFN_TCSS_XDCI); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 259 | |
| 260 | /* TCSS DMA */ |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 261 | m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0); |
| 262 | m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 263 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 264 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 265 | static void fill_fspm_usb4_params(FSP_M_CONFIG *m_cfg, |
| 266 | const struct soc_intel_alderlake_config *config) |
| 267 | { |
Subrata Banik | 50134ec | 2021-06-09 04:14:50 +0530 | [diff] [blame] | 268 | m_cfg->TcssItbtPcie0En = is_devfn_enabled(SA_DEVFN_TBT0); |
| 269 | m_cfg->TcssItbtPcie1En = is_devfn_enabled(SA_DEVFN_TBT1); |
| 270 | m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2); |
| 271 | m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 272 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 273 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 274 | static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, |
| 275 | const struct soc_intel_alderlake_config *config) |
| 276 | { |
Meera Ravindranath | 3b03798 | 2021-11-11 18:02:13 +0530 | [diff] [blame] | 277 | const uint32_t cpuid = cpu_get_cpuid(); |
| 278 | |
| 279 | /* Disable VT-d for early silicon steppings as it results in a CPU hard hang */ |
Lean Sheng Tan | 9e78dd1 | 2022-04-01 12:03:51 +0200 | [diff] [blame] | 280 | if (cpuid == CPUID_ALDERLAKE_J0 || cpuid == CPUID_ALDERLAKE_Q0) { |
Meera Ravindranath | 3b03798 | 2021-11-11 18:02:13 +0530 | [diff] [blame] | 281 | m_cfg->VtdDisable = 1; |
| 282 | return; |
| 283 | } |
| 284 | |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 285 | m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; |
| 286 | m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS; |
| 287 | m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS; |
| 288 | |
| 289 | m_cfg->VtdDisable = 0; |
| 290 | m_cfg->VtdIopEnable = !m_cfg->VtdDisable; |
| 291 | m_cfg->VtdIgdEnable = m_cfg->InternalGfx; |
| 292 | m_cfg->VtdIpuEnable = m_cfg->SaIpuEnable; |
| 293 | |
| 294 | if (m_cfg->VtdIgdEnable && m_cfg->VtdBaseAddress[VTD_GFX] == 0) { |
| 295 | m_cfg->VtdIgdEnable = 0; |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 296 | printk(BIOS_ERR, "Requested IGD VT-d, but GFXVT_BASE_ADDRESS is 0\n"); |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | if (m_cfg->VtdIpuEnable && m_cfg->VtdBaseAddress[VTD_IPU] == 0) { |
| 300 | m_cfg->VtdIpuEnable = 0; |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 301 | printk(BIOS_ERR, "Requested IPU VT-d, but IPUVT_BASE_ADDRESS is 0\n"); |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | if (!m_cfg->VtdDisable && m_cfg->VtdBaseAddress[VTD_VTVCO] == 0) { |
| 305 | m_cfg->VtdDisable = 1; |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 306 | printk(BIOS_ERR, "Requested VT-d, but VTVCO_BASE_ADDRESS is 0\n"); |
Meera Ravindranath | a3f7deb | 2021-03-26 15:10:48 +0530 | [diff] [blame] | 307 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 308 | |
Sridhar Siricilla | d047927 | 2021-05-28 20:00:02 +0530 | [diff] [blame] | 309 | if (m_cfg->TcssDma0En || m_cfg->TcssDma1En) |
| 310 | m_cfg->VtdItbtEnable = 1; |
| 311 | |
| 312 | if (m_cfg->TcssItbtPcie0En) |
| 313 | m_cfg->VtdBaseAddress[VTD_TBT0] = TBT0_BASE_ADDRESS; |
| 314 | |
| 315 | if (m_cfg->TcssItbtPcie1En) |
| 316 | m_cfg->VtdBaseAddress[VTD_TBT1] = TBT1_BASE_ADDRESS; |
| 317 | |
| 318 | if (m_cfg->TcssItbtPcie2En) |
| 319 | m_cfg->VtdBaseAddress[VTD_TBT2] = TBT2_BASE_ADDRESS; |
| 320 | |
| 321 | if (m_cfg->TcssItbtPcie3En) |
| 322 | m_cfg->VtdBaseAddress[VTD_TBT3] = TBT3_BASE_ADDRESS; |
| 323 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 324 | /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ |
| 325 | m_cfg->VmxEnable = CONFIG(ENABLE_VMX); |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 326 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 327 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 328 | static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, |
| 329 | const struct soc_intel_alderlake_config *config) |
| 330 | { |
| 331 | /* Set debug probe type */ |
| 332 | m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; |
Francois Toguo | cea4f92 | 2021-04-16 21:20:39 -0700 | [diff] [blame] | 333 | |
| 334 | /* CrashLog config */ |
Subrata Banik | 7b8d11b | 2021-07-14 13:11:53 +0530 | [diff] [blame] | 335 | m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT); |
| 336 | m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 337 | } |
| 338 | |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 339 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, |
| 340 | const struct soc_intel_alderlake_config *config) |
| 341 | { |
Arthur Heymans | 02967e6 | 2022-02-18 13:22:25 +0100 | [diff] [blame] | 342 | void (*const fill_fspm_params[])(FSP_M_CONFIG *m_cfg, |
Subrata Banik | 85c9dda | 2021-06-09 22:03:57 +0530 | [diff] [blame] | 343 | const struct soc_intel_alderlake_config *config) = { |
| 344 | fill_fspm_igd_params, |
| 345 | fill_fspm_mrc_params, |
| 346 | fill_fspm_cpu_params, |
| 347 | fill_fspm_security_params, |
| 348 | fill_fspm_uart_params, |
| 349 | fill_fspm_ipu_params, |
| 350 | fill_fspm_smbus_params, |
| 351 | fill_fspm_misc_params, |
| 352 | fill_fspm_audio_params, |
| 353 | fill_fspm_pcie_rp_params, |
| 354 | fill_fspm_ish_params, |
| 355 | fill_fspm_tcss_params, |
| 356 | fill_fspm_usb4_params, |
| 357 | fill_fspm_vtd_params, |
| 358 | fill_fspm_trace_params, |
| 359 | }; |
| 360 | |
| 361 | for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) |
| 362 | fill_fspm_params[i](m_cfg, config); |
| 363 | } |
| 364 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 365 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 366 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 367 | const struct soc_intel_alderlake_config *config; |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 368 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
Subrata Banik | 7cb6d72 | 2022-03-23 01:33:27 +0530 | [diff] [blame] | 369 | FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; |
| 370 | |
Subrata Banik | 88381c9 | 2022-03-29 11:26:11 +0530 | [diff] [blame] | 371 | if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) { |
| 372 | if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) { |
| 373 | enum fsp_log_level log_level = fsp_map_console_log_level(); |
| 374 | arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *) |
| 375 | fsp_debug_event_handler); |
| 376 | /* Set Serial debug message level */ |
| 377 | m_cfg->PcdSerialDebugLevel = log_level; |
| 378 | /* Set MRC debug level */ |
| 379 | m_cfg->SerialDebugMrcLevel = log_level; |
| 380 | } else { |
| 381 | /* Disable Serial debug message */ |
| 382 | m_cfg->PcdSerialDebugLevel = 0; |
| 383 | /* Disable MRC debug message */ |
| 384 | m_cfg->SerialDebugMrcLevel = 0; |
| 385 | } |
| 386 | } |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 387 | config = config_of_soc(); |
| 388 | |
| 389 | soc_memory_init_params(m_cfg, config); |
Zhuohao Lee | 09f3b6c | 2022-01-20 21:30:12 +0800 | [diff] [blame] | 390 | mainboard_memory_init_params(mupd); |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 391 | } |
| 392 | |
Zhuohao Lee | 09f3b6c | 2022-01-20 21:30:12 +0800 | [diff] [blame] | 393 | __weak void mainboard_memory_init_params(FSPM_UPD *memupd) |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 394 | { |
| 395 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 396 | } |