Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 1 | package main |
| 2 | |
| 3 | type sandybridgemc struct { |
| 4 | variant string |
| 5 | } |
| 6 | |
| 7 | func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) { |
| 8 | inteltool := ctx.InfoSource.GetInteltool() |
| 9 | |
| 10 | /* FIXME:XX Move this somewhere else. */ |
| 11 | MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h") |
| 12 | MainboardEnable += (` /* FIXME: fix those values*/ |
| 13 | install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); |
| 14 | `) |
| 15 | |
| 16 | pchLVDS := inteltool.IGD[0xe1180] |
| 17 | dualChannel := pchLVDS&(3<<2) == (3 << 2) |
| 18 | pipe := (pchLVDS >> 30) & 1 |
| 19 | data_m1 := inteltool.IGD[0x60030+0x1000*pipe] & 0xffffff |
| 20 | data_n1 := inteltool.IGD[0x60034+0x1000*pipe] |
| 21 | link_m1 := inteltool.IGD[0x60040+0x1000*pipe] |
| 22 | link_n1 := inteltool.IGD[0x60044+0x1000*pipe] |
| 23 | data_factor := float32(data_m1) / float32(data_n1) |
| 24 | link_factor := float32(link_m1) / float32(link_n1) |
| 25 | num_lanes := uint32((link_factor/data_factor)*18.0/8.0 + 0.5) |
| 26 | fp0 := inteltool.IGD[0xc6040+8*pipe] |
| 27 | dpll := inteltool.IGD[0xc6014+4*pipe] |
| 28 | pixel_m2 := fp0 & 0xff |
| 29 | pixel_m1 := (fp0>>8)&0xff + 2 |
| 30 | pixel_p1 := uint32(1) |
| 31 | for i := dpll & 0x1ffff; i != 0 && i&1 == 0; i >>= 1 { |
| 32 | pixel_p1++ |
| 33 | } |
| 34 | pixel_n := ((fp0 >> 16) & 0xff) + 2 |
| 35 | pixel_frequency := float32(120000*(5*pixel_m1+pixel_m2)) / float32(pixel_n*pixel_p1*7.0) |
| 36 | if !dualChannel { |
| 37 | pixel_frequency /= 2 |
| 38 | } |
| 39 | link_frequency := pixel_frequency / link_factor |
| 40 | DevTree = DevTreeNode{ |
| 41 | Chip: "northbridge/intel/sandybridge", |
| 42 | MissingParent: "northbridge", |
| 43 | Comment: "FIXME: check gfx.ndid and gfx.did", |
| 44 | Registers: map[string]string{ |
| 45 | "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7), |
| 46 | "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7), |
| 47 | "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7), |
| 48 | "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3), |
| 49 | "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff), |
| 50 | "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff), |
| 51 | "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff), |
| 52 | "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff), |
| 53 | "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff), |
| 54 | "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]), |
| 55 | "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), |
| 56 | "gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0), |
| 57 | "gfx.lvds_dual_channel": FormatBool(dualChannel), |
| 58 | "gfx.lvds_num_lanes": FormatInt32(num_lanes), |
| 59 | "gfx.link_frequency_270_mhz": FormatBool(link_frequency > 200000), |
| 60 | /* FIXME:XX hardcoded. */ |
| 61 | "gfx.ndid": "3", |
| 62 | "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", |
| 63 | }, |
| 64 | Children: []DevTreeNode{ |
| 65 | { |
| 66 | Chip: "cpu_cluster", |
| 67 | Dev: 0, |
| 68 | Children: []DevTreeNode{ |
| 69 | { |
| 70 | Chip: "cpu/intel/socket_rPGA989", |
| 71 | Children: []DevTreeNode{ |
| 72 | { |
| 73 | Chip: "lapic", |
| 74 | Dev: 0, |
| 75 | }, |
| 76 | }, |
| 77 | }, |
| 78 | |
| 79 | { |
| 80 | Chip: "cpu/intel/model_206ax", |
| 81 | Comment: "FIXME: check all registers", |
| 82 | Registers: map[string]string{ |
| 83 | /* FIXME:XX hardcoded. */ |
| 84 | "c1_acpower": "1", |
| 85 | "c2_acpower": "3", |
| 86 | "c3_acpower": "5", |
| 87 | "c1_battery": "1", |
| 88 | "c2_battery": "3", |
| 89 | "c3_battery": "5", |
| 90 | }, |
| 91 | Children: []DevTreeNode{ |
| 92 | { |
| 93 | Chip: "lapic", |
| 94 | Dev: 0xacac, |
| 95 | Disabled: true, |
| 96 | }, |
| 97 | }, |
| 98 | }, |
| 99 | }, |
| 100 | }, |
| 101 | |
| 102 | { |
| 103 | Chip: "domain", |
| 104 | Dev: 0, |
| 105 | PCIController: true, |
| 106 | ChildPCIBus: 0, |
| 107 | PCISlots: []PCISlot{ |
| 108 | PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, |
| 109 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, |
| 110 | PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, |
| 111 | }, |
| 112 | }, |
| 113 | }, |
| 114 | } |
| 115 | |
| 116 | PutPCIDev(addr, "Host bridge") |
| 117 | |
| 118 | /* FIXME:XX Move part to northbridge? */ |
| 119 | /* FIXME:XX some configs are unsupported. */ |
| 120 | KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT"] = true |
| 121 | KconfigBool["MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG"] = true |
| 122 | KconfigBool[i.variant+"BRIDGE_LVDS"] = true |
| 123 | |
| 124 | KconfigBool["VGA"] = true |
| 125 | KconfigBool["INTEL_EDID"] = true |
| 126 | KconfigBool["CPU_INTEL_SOCKET_RPGA989"] = true |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame^] | 127 | KconfigBool["NORTHBRIDGE_INTEL_"+i.variant+"BRIDGE"] = true |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 128 | KconfigBool["INTEL_INT15"] = true |
| 129 | KconfigBool["HAVE_ACPI_TABLES"] = true |
| 130 | KconfigBool["HAVE_ACPI_RESUME"] = true |
| 131 | |
| 132 | KconfigBool["HAVE_IFD_BIN"] = false |
| 133 | KconfigBool["HAVE_ME_BIN"] = false |
| 134 | |
| 135 | KconfigHex["MMCONF_BASE_ADDRESS"] = 0xf0000000 |
| 136 | KconfigInt["MAX_CPUS"] = 8 |
| 137 | |
| 138 | DSDTIncludes = append(DSDTIncludes, DSDTInclude{ |
| 139 | File: "cpu/intel/model_206ax/acpi/cpu.asl", |
| 140 | }) |
| 141 | |
| 142 | DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ |
| 143 | File: "northbridge/intel/sandybridge/acpi/sandybridge.asl", |
| 144 | }) |
| 145 | } |
| 146 | |
| 147 | func init() { |
| 148 | RegisterPCI(0x8086, 0x0100, sandybridgemc{variant: "SANDY"}) |
| 149 | RegisterPCI(0x8086, 0x0104, sandybridgemc{variant: "SANDY"}) |
| 150 | RegisterPCI(0x8086, 0x0150, sandybridgemc{variant: "IVY"}) |
| 151 | RegisterPCI(0x8086, 0x0154, sandybridgemc{variant: "IVY"}) |
| 152 | for _, id := range []uint16{ |
| 153 | 0x0102, 0x0106, 0x010a, 0x0112, |
| 154 | 0x0116, 0x0122, 0x0126, 0x0156, |
| 155 | 0x0166, |
| 156 | } { |
| 157 | RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}}) |
| 158 | } |
| 159 | } |