Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 One Laptop per Child, Association, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | /* |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 21 | * Part of this file is from cx700 port, part of is from cn700 port, |
| 22 | * and acpi_is_wakeup_early_via_VX800() is part of Rudolf's S3 patch. |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 23 | */ |
| 24 | |
Stefan Reinauer | 17b60a9 | 2010-04-14 17:11:47 +0000 | [diff] [blame] | 25 | #define PAYLOAD_IS_SEABIOS 0 |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 26 | |
| 27 | #include <stdint.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <device/pci_ids.h> |
Kyösti Mälkki | 207880c | 2013-12-10 09:03:17 +0200 | [diff] [blame] | 30 | #include <arch/acpi.h> |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 31 | #include <arch/io.h> |
| 32 | #include <device/pnp_def.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 33 | #include <console/console.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 34 | #include <lib.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 35 | #include <northbridge/via/vx800/vx800.h> |
| 36 | #include <cpu/x86/bist.h> |
Stefan Reinauer | ae5e11d | 2012-04-27 02:31:28 +0200 | [diff] [blame] | 37 | #include "drivers/pc80/udelay_io.c" |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame^] | 38 | #include <delay.h> |
Myles Watson | 42f75c3 | 2009-07-07 17:54:26 +0000 | [diff] [blame] | 39 | #include <string.h> |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 40 | /* This file contains the board-special SI value for raminit.c. */ |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame] | 41 | #include "driving_clk_phase_data.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 42 | #include <northbridge/via/vx800/raminit.h> |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 43 | #include "northbridge/via/vx800/raminit.c" |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame] | 44 | #include "wakeup.h" |
Edward O'Callaghan | 9492b9d | 2014-05-14 01:00:43 +1000 | [diff] [blame] | 45 | #include <superio/winbond/common/winbond.h> |
| 46 | #include <superio/winbond/w83697hf/w83697hf.h> |
Uwe Hermann | 4e2ffb8 | 2009-07-15 00:03:28 +0000 | [diff] [blame] | 47 | |
| 48 | #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) |
Uwe Hermann | 9b9791c | 2010-12-06 18:17:01 +0000 | [diff] [blame] | 49 | #define DUMMY_DEV PNP_DEV(0x2e, 0) |
Uwe Hermann | 4e2ffb8 | 2009-07-15 00:03:28 +0000 | [diff] [blame] | 50 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 51 | /* |
| 52 | * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: |
| 53 | * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. |
| 54 | */ |
Stefan Reinauer | 8816cdf | 2010-04-14 16:39:30 +0000 | [diff] [blame] | 55 | static int acpi_is_wakeup_early_via_vx800(void) |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 56 | { |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 57 | device_t dev; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 58 | u16 tmp, result; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 59 | |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 60 | print_debug("In acpi_is_wakeup_early_via_vx800\n"); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 61 | /* Power management controller */ |
| 62 | dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, |
| 63 | PCI_DEVICE_ID_VIA_VX855_LPC), 0); |
| 64 | |
| 65 | if (dev == PCI_DEV_INVALID) |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 66 | die("Power management controller not found\n"); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 67 | |
| 68 | /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ |
| 69 | pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); |
| 70 | |
Paul Menzel | 475e1b9 | 2013-12-27 15:21:58 +0100 | [diff] [blame] | 71 | /* Enable ACPI access RTC signal gated with PSON. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 72 | pci_write_config8(dev, 0x81, 0x84); |
| 73 | |
| 74 | tmp = inw(VX800_ACPI_IO_BASE + 0x04); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 75 | result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 76 | print_debug(" boot_mode="); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 77 | print_debug_hex16(result); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 78 | print_debug("\n"); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 79 | return result; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 80 | } |
| 81 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 82 | /* All content of this function came from the cx700 port of coreboot. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 83 | static void enable_mainboard_devices(void) |
| 84 | { |
| 85 | device_t dev; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 86 | #if 0 |
| 87 | /* |
| 88 | * Add and close this switch, since some line cause error, some |
| 89 | * written at elsewhere (stage1 stage2). |
| 90 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 91 | u8 regdata; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 92 | dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, |
| 93 | PCI_DEVICE_ID_VIA_VX855_LPC), 0); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 94 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 95 | /* Disable GP3. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 96 | pci_write_config8(dev, 0x98, 0x00); |
| 97 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 98 | pci_write_config8(dev, 0x50, 0x80); /* Disable mc97. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 99 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 100 | /* |
| 101 | * Martin: Disable internal KBC configuration. |
| 102 | * |
| 103 | * Internal Config is needed to decide which key can be pressed to |
| 104 | * resume from s3. |
| 105 | */ |
| 106 | pci_write_config8(dev, 0x51, 0x2d); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 107 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 108 | /* This causes irq0 can not be triggerd, since bit 5 was set to 0. */ |
| 109 | /* pci_write_config8(dev, 0x58, 0x42); */ |
| 110 | |
| 111 | /* These writing may... TODO */ |
| 112 | regdata = pci_read_config8(dev, 0x58); |
| 113 | regdata |= 0x41; |
| 114 | pci_write_config8(dev, 0x58, regdata); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 115 | pci_write_config8(dev, 0x59, 0x80); |
| 116 | pci_write_config8(dev, 0x5b, 0x01); |
| 117 | #endif |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 118 | |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 119 | print_debug("In enable_mainboard_devices\n"); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 120 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 121 | /* Enable P2P Bridge Header for external PCI bus. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 122 | dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 123 | pci_write_config8(dev, 0x4f, 0x41); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 124 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 125 | /* |
| 126 | * "5324" already is the default value of the PCI IDE device, cancel |
| 127 | * this PCI write. |
| 128 | * |
| 129 | * [william 20080124]: Fix bug that can not boot Ubuntu at the |
| 130 | * beginning time. |
| 131 | */ |
| 132 | #if 0 |
| 133 | dev = 0; |
| 134 | dev = pci_locate_device(PCI_ID(0x1106, PCI_DEVICE_ID_VIA_VX855_IDE), 0); |
Stefan Reinauer | 8816cdf | 2010-04-14 16:39:30 +0000 | [diff] [blame] | 135 | |
| 136 | uint16_t values; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 137 | values = pci_read_config16(dev, 0xBA); |
| 138 | values &= ~0xffff; |
| 139 | values |= 0x5324; |
| 140 | pci_write_config16(dev, 0xBA, values); |
| 141 | #endif |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 142 | } |
| 143 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 144 | /* |
| 145 | * Most content of this function came from the cx700 port of coreboot. |
| 146 | * Turn on the shadow of E-seg. |
| 147 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 148 | static void enable_shadow_ram(void) |
| 149 | { |
| 150 | uint8_t shadowreg; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 151 | |
| 152 | /* |
| 153 | * Changed the value from 0x2a to 0x3f. "read only" may block "write"? |
| 154 | * and maybe in C-seg "write" will be needed? |
| 155 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 156 | pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 157 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 158 | /* 0xf0000-0xfffff - ACPI tables */ |
| 159 | shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83); |
| 160 | shadowreg |= 0x30; |
| 161 | pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 162 | |
| 163 | /* 0xe0000-0xeffff - elfload? */ |
| 164 | /* |
| 165 | * In s3 resume process, wakeup.c, I use E-seg to hold the code |
| 166 | * (which can not locate in the area to be covered) that will copy |
| 167 | * 0-A-seg and F-seg from TOP-mem back to their normal location. |
| 168 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 169 | pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 170 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 171 | #if 0 |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 172 | /* Enable shadow RAM as normal DRAM */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 173 | /* 0xc0000-0xcffff - VGA BIOS */ |
| 174 | pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a); |
| 175 | pci_write_config8(PCI_DEV(0, 0, 7), 0x61, 0x00); |
| 176 | /* 0xd0000-0xdffff - ?? */ |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 177 | /* pci_write_config8(PCI_DEV(0, 0, 3), 0x81, 0xff); */ |
| 178 | /* pci_write_config8(PCI_DEV(0, 0, 7), 0x62, 0xff); */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 179 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 180 | /* Do it again for the vlink controller. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 181 | shadowreg = pci_read_config8(PCI_DEV(0, 0, 7), 0x63); |
| 182 | shadowreg |= 0x30; |
| 183 | pci_write_config8(PCI_DEV(0, 0, 7), 0x63, shadowreg); |
| 184 | #endif |
| 185 | } |
| 186 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 187 | /* |
| 188 | * Added this table 2008-11-28. |
| 189 | * This table contains the value needed to be set before begin to init DRAM. |
| 190 | * Note: REV_Bx should be checked for changes when porting a new board! |
| 191 | */ |
| 192 | static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { |
| 193 | /* VT3409 no PCI-E */ |
Stefan Reinauer | 8816cdf | 2010-04-14 16:39:30 +0000 | [diff] [blame] | 194 | { 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E }, // Set Exxxxxxx as pcie mmio config range |
| 195 | { 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B }, // Support extended cfg address of pcie |
| 196 | // { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 197 | // Set ROMSIP value by software |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 198 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 199 | /* |
Stefan Reinauer | 8816cdf | 2010-04-14 16:39:30 +0000 | [diff] [blame] | 200 | { 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pullup Driving = 3 |
| 201 | { 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pulldown Driving = 3 |
| 202 | { 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pullup Driving = 3 |
| 203 | { 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pulldown Driving = 3 |
| 204 | { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21 }, // Memory I/F timing ctrl |
| 205 | { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1 }, // Memory I/F timing ctrl |
| 206 | { 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18 }, // AGTL+ I/O Circuit |
| 207 | { 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C }, // AGTL+ Compensation Status |
| 208 | { 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33 }, // 2X AGTL+ Auto Compensation Offset |
| 209 | { 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33 }, // 4X AGTL+ Auto Compensation Offset |
| 210 | { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72 }, // AGTL Compensation Status |
| 211 | { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77 }, // AGTL Compensation Status |
| 212 | { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44 }, // Input Host Address / Host Strobe Delay Control for HA Group |
| 213 | { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22 }, // Input Host Address / Host Strobe Delay Control for HA Group |
| 214 | { 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00 }, // Output Delay Control of PAD for HA Group |
| 215 | { 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA }, // Host Address / Address Clock Output Delay Control (Only for P4 Bus) |
| 216 | { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) |
| 217 | { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) |
| 218 | { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) |
| 219 | { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) |
| 220 | { 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 1 |
| 221 | { 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 2 |
| 222 | { 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00 }, // Output Delay of PAD for HDSTB |
| 223 | { 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00 }, // Output Delay of PAD for HD |
| 224 | { 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 0) |
| 225 | { 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 1) |
| 226 | { 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 2) |
| 227 | { 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 3) |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame] | 228 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 229 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 230 | // CPU Host Bus Control |
Stefan Reinauer | 8816cdf | 2010-04-14 16:39:30 +0000 | [diff] [blame] | 231 | { 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08 }, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 |
| 232 | // { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW |
| 233 | { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW |
| 234 | { 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB }, // CPU I/F Ctrl-2: Enable all for performance |
| 235 | // { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88 }, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK |
| 236 | { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44 }, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK |
| 237 | { 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C }, // Misc Ctrl: Enable 8QW burst Mem Access |
| 238 | // { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06 }, // Miscellaneous Control 2 |
| 239 | { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04 }, // Miscellaneous Control 2 |
| 240 | { 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63 }, // Write Policy 1 |
| 241 | // { 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01 }, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL |
| 242 | // { 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00 }, // CPU Miscellaneous Control 2 |
| 243 | { 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2 }, // Write Policy |
| 244 | { 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88 }, // Bandwidth Timer |
| 245 | { 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46 }, // CPU Misc Ctrl |
| 246 | // { 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B }, // CPU Miscellaneous Control 3 |
| 247 | // { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B }, // CPU Miscellaneous Control 2 |
| 248 | { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A }, // CPU Miscellaneous Control 2 |
| 249 | { 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41 }, // CPU Miscellaneous Control 3 |
| 250 | { 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06 }, // CPU Miscellaneous Control 4 |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 251 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 252 | // Set APIC and SMRAM |
Stefan Reinauer | 8816cdf | 2010-04-14 16:39:30 +0000 | [diff] [blame] | 253 | { 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00 }, // APIC Related Control |
| 254 | { 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29 }, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg |
| 255 | { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } // End of the table |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 256 | }; |
| 257 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 258 | #define USE_VCP 1 /* 0 means "use DVP". */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 259 | #define USE_COM1 1 |
| 260 | #define USE_COM2 0 |
| 261 | |
| 262 | #define gCom1Base 0x3f8 |
| 263 | #define gCom2Base 0x2f8 |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 264 | |
Stefan Reinauer | 17b60a9 | 2010-04-14 17:11:47 +0000 | [diff] [blame] | 265 | #if 0 |
| 266 | static void EmbedComInit(void) |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 267 | { |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 268 | u8 ByteVal; |
| 269 | u16 ComBase; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 270 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 271 | /* Enable NB multiple function control. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 272 | ByteVal = pci_read_config8(PCI_DEV(0, 0, 0), 0x4f); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 273 | ByteVal = ByteVal | 0x01; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 274 | pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, ByteVal); |
| 275 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 276 | /* VGA enable. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 277 | ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA1); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 278 | ByteVal = ByteVal | 0x80; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 279 | pci_write_config8(PCI_DEV(0, 0, 3), 0xA1, ByteVal); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 280 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 281 | ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA7); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 282 | ByteVal = ByteVal | 0x08; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 283 | pci_write_config8(PCI_DEV(0, 0, 3), 0xA7, ByteVal); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 284 | |
| 285 | /* Enable P2P IO/mem. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 286 | ByteVal = pci_read_config8(PCI_DEV(0, 1, 0), 0x4); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 287 | ByteVal = ByteVal | 0x07; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 288 | pci_write_config8(PCI_DEV(0, 1, 0), 0x4, ByteVal); |
| 289 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 290 | /* Turn on graphic chip I/O port port access. */ |
| 291 | ByteVal = inb(0x3C3); |
| 292 | ByteVal = ByteVal | 0x01; |
| 293 | outb(ByteVal, 0x3C3); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 294 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 295 | /* Turn off graphic chip register protection. */ |
| 296 | outb(0x10, 0x3C4); |
| 297 | ByteVal = inb(0x3C5); |
| 298 | ByteVal = ByteVal | 0x01; |
| 299 | outb(ByteVal, 0x3C5); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 300 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 301 | /* South module pad share enable 0x3C5.78[7]. */ |
| 302 | outb(0x78, 0x3C4); |
| 303 | ByteVal = inb(0x3C5); |
| 304 | ByteVal = ByteVal | 0x80; |
| 305 | outb(ByteVal, 0x3C5); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 306 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 307 | /* Enable UART function multiplex with DVP or VCP pad D17F0Rx46[7,6]. */ |
| 308 | ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0x46); |
| 309 | if (USE_VCP == 1) |
| 310 | ByteVal = (ByteVal & 0x3F) | 0x40; /* Multiplex with VCP. */ |
| 311 | else |
| 312 | ByteVal = (ByteVal & 0x3F) | 0xC0; /* Multiplex with DVP. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 313 | pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal); |
| 314 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 315 | /* Enable embedded COM1 and COM2 D17F0RxB0[5,4]. */ |
| 316 | ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0); |
| 317 | ByteVal = ByteVal & 0xcf; |
| 318 | /* Multiplex with VCP. */ |
| 319 | if (USE_COM1 == 1) |
| 320 | ByteVal = ByteVal | 0x10; |
| 321 | if (USE_COM2 == 1) |
| 322 | ByteVal = ByteVal | 0x20; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 323 | pci_write_config8(PCI_DEV(0, 17, 0), 0xB0, ByteVal); |
| 324 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 325 | if (USE_COM1 == 1) |
| 326 | ComBase = gCom1Base; |
| 327 | else |
| 328 | ComBase = gCom2Base; |
| 329 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 330 | //noharddrive |
| 331 | |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame] | 332 | /* Set embedded COM1 I/O base = 0x3E8 (D17F0RB4, ByteVal = 0xFD) */ |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 333 | if (USE_COM1 == 1) { |
| 334 | ByteVal = (u8) ((gCom1Base >> 3) | 0x80); |
| 335 | pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal); |
| 336 | ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); |
| 337 | ByteVal = (ByteVal & 0xf0) | 0x04; |
| 338 | pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); |
| 339 | } |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 340 | |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame] | 341 | /* Set embedded COM2 I/O base = 0x2E8 (D17F0RB5, ByteVal = 0xDD). */ |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 342 | if (USE_COM2 == 1) { |
| 343 | ByteVal = (u8) ((gCom2Base >> 3) | 0x80); |
| 344 | pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal); |
| 345 | ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); |
| 346 | ByteVal = (ByteVal & 0x0f) | 0x30; |
| 347 | pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); |
| 348 | } |
| 349 | /* No port 80 biger then 0x10. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 350 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 351 | /* Disable interrupt. */ |
| 352 | ByteVal = inb(ComBase + 3); |
| 353 | outb(ByteVal & 0x7F, ComBase + 3); |
| 354 | outb(0x00, ComBase + 1); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 355 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 356 | /* Set BAUD rate. */ |
| 357 | ByteVal = inb(ComBase + 3); |
| 358 | outb(ByteVal | 0x80, ComBase + 3); |
| 359 | outb(0x01, ComBase); |
| 360 | outb(0x00, ComBase + 1); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 361 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 362 | /* Set frame format. */ |
| 363 | ByteVal = inb(ComBase + 3); |
| 364 | outb(ByteVal & 0x3F, ComBase + 3); |
| 365 | outb(0x03, ComBase + 3); |
| 366 | outb(0x00, ComBase + 2); |
| 367 | outb(0x00, ComBase + 4); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 368 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 369 | /* SOutput("Embedded COM output\n"); */ |
| 370 | /* while(1); */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 371 | } |
Stefan Reinauer | 17b60a9 | 2010-04-14 17:11:47 +0000 | [diff] [blame] | 372 | #endif |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 373 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 374 | /* cache_as_ram.inc jumps to here. */ |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 375 | #include <cpu/intel/romstage.h> |
Stefan Reinauer | 314e551 | 2010-04-09 20:36:29 +0000 | [diff] [blame] | 376 | void main(unsigned long bist) |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 377 | { |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 378 | u16 boot_mode; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 379 | u8 rambits, Data8, Data; |
| 380 | device_t device; |
| 381 | /* device_t dev; */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 382 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 383 | /* |
| 384 | * Enable multifunction for northbridge. These 4 lines (until |
| 385 | * console_init()) are the same with epia-cn port. |
| 386 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 387 | pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); |
Uwe Hermann | 4e2ffb8 | 2009-07-15 00:03:28 +0000 | [diff] [blame] | 388 | /* EmbedComInit(); */ |
Uwe Hermann | 9b9791c | 2010-12-06 18:17:01 +0000 | [diff] [blame] | 389 | w83697hf_set_clksel_48(DUMMY_DEV); |
Edward O'Callaghan | 9492b9d | 2014-05-14 01:00:43 +1000 | [diff] [blame] | 390 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 391 | /* enable_vx800_serial(); */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 392 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 393 | /* |
| 394 | * 1. D15F0 |
| 395 | * a) RxBAh = 71h |
| 396 | * b) RxBBh = 05h |
| 397 | * c) RxBEh = 71h |
| 398 | * d) RxBFh = 05h |
| 399 | * |
| 400 | * 2. D17F0 |
| 401 | * a) RxA0h = 06h |
| 402 | * b) RxA1h = 11h |
| 403 | * c) RxA2h = 27h |
| 404 | * d) RxA3h = 32h |
| 405 | * e) Rx79h = 40h |
| 406 | * f) Rx72h = 27h |
| 407 | * g) Rx73h = 32h |
| 408 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 409 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 410 | pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA, |
| 411 | PCI_DEVICE_ID_VIA_VX855_IDE); |
| 412 | pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE, |
| 413 | PCI_DEVICE_ID_VIA_VX855_IDE); |
| 414 | pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA0, PCI_VENDOR_ID_VIA); |
| 415 | pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA2, |
| 416 | PCI_DEVICE_ID_VIA_VX855_LPC); |
| 417 | Data8 = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x79); |
| 418 | Data8 &= ~0x40; |
| 419 | Data8 |= 0x40; |
| 420 | pci_write_config8(PCI_DEV(0, 0x11, 0), 0x79, Data8); |
| 421 | pci_write_config16(PCI_DEV(0, 0x11, 0), 0x72, |
| 422 | PCI_DEVICE_ID_VIA_VX855_LPC); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 423 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 424 | /* |
| 425 | * There are two function definitions of console_init(), while the |
Stefan Reinauer | 8677a23 | 2010-12-11 20:33:41 +0000 | [diff] [blame] | 426 | * src/arch/x86/lib is the right one. |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 427 | */ |
| 428 | console_init(); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 429 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 430 | /* Decide if this is a s3 wakeup or a normal boot. */ |
| 431 | boot_mode = acpi_is_wakeup_early_via_vx800(); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 432 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 433 | /* |
| 434 | * 2008-11-27 Add this, to transfer "cpu restart" to "cold boot". |
| 435 | * When this boot is not a S3 resume, and PCI registers had been |
| 436 | * written, then this must be a CPU restart (result of OS reboot cmd), |
| 437 | * so we need a real "cold boot". |
| 438 | */ |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 439 | if ((boot_mode != 3) |
| 440 | && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) { |
| 441 | outb(6, 0xcf9); |
| 442 | } |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 443 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 444 | /* x86 cold boot I/O cmd. */ |
| 445 | /* These 2 lines are the same with epia-cn port. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 446 | enable_smbus(); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 447 | |
| 448 | /* This fix does help vx800!, but vx855 doesn't need this. */ |
| 449 | /* smbus_fixup(&ctrl); */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 450 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 451 | /* Halt if there was a built-in self test failure. */ |
| 452 | report_bist_failure(bist); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 453 | |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 454 | print_debug("Enabling mainboard devices\n"); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 455 | enable_mainboard_devices(); |
| 456 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 457 | /* |
| 458 | * Get NB chip revision from D0F4RxF6, revision will be used in |
| 459 | * via_pci_inittable. |
| 460 | */ |
| 461 | device = PCI_DEV(0, 0, 4); |
| 462 | Data = pci_read_config8(device, 0xf6); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 463 | print_debug("NB chip revision ="); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 464 | print_debug_hex8(Data); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 465 | print_debug("\n"); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 466 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 467 | /* Make NB ready before DRAM init. */ |
| 468 | via_pci_inittable(Data, mNbStage1InitTbl); |
| 469 | |
| 470 | /* |
| 471 | * When resume from s3, DRAM init is skipped, so need to recovery |
| 472 | * any PCI register related to DRAM init. d0f3 didn't lose its power |
| 473 | * during whole s3 time, so any register not belonging to d0f3 needs |
| 474 | * to be recovered. |
| 475 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 476 | #if 1 |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 477 | if (boot_mode == 3) { |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 478 | u8 i; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 479 | u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 480 | DRAM_SYS_ATTR DramAttr; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 481 | |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 482 | print_debug("This is an S3 wakeup\n"); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 483 | |
| 484 | memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR)); |
| 485 | /* |
| 486 | * Step 1: DRAM detection; DDR1 or DDR2; Get SPD Data; |
| 487 | * Rank Presence; 64 or 128bit; Unbuffered or registered; |
| 488 | * 1T or 2T. |
| 489 | */ |
| 490 | DRAMDetect(&DramAttr); |
| 491 | |
| 492 | /* |
| 493 | * Begin to get RAM size, 43,42 41 40 contains the end |
| 494 | * address of last rank in DDR2 slot. |
| 495 | */ |
| 496 | device = PCI_DEV(0, 0, 3); |
| 497 | for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 498 | rambits = pci_read_config8(device, ramregs[i]); |
| 499 | if (rambits != 0) |
| 500 | break; |
| 501 | } |
| 502 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 503 | DRAMDRDYSetting(&DramAttr); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 504 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 505 | Data = 0x80; /* This value is same with DevInit.c. */ |
| 506 | pci_write_config8(PCI_DEV(0, 0, 4), 0xa3, Data); |
| 507 | pci_write_config8(PCI_DEV(0, 17, 7), 0x60, rambits << 2); |
| 508 | Data = pci_read_config8(MEMCTRL, 0x88); |
| 509 | pci_write_config8(PCI_DEV(0, 17, 7), 0xE5, Data); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 510 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 511 | /* Just copy this function from draminit to here! */ |
| 512 | DRAMRegFinalValue(&DramAttr); |
| 513 | |
| 514 | /* Just copy this function from draminit to here! */ |
| 515 | SetUMARam(); |
| 516 | |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 517 | print_debug("Resume from S3, RAM init was ignored\n"); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 518 | } else { |
| 519 | ddr2_ram_setup(); |
| 520 | ram_check(0, 640 * 1024); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 521 | } |
| 522 | #endif |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 523 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 524 | /* ddr2_ram_setup(); */ |
| 525 | /* This line is the same with cx700 port. */ |
| 526 | enable_shadow_ram(); |
| 527 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 528 | /* |
| 529 | * For coreboot most time of S3 resume is the same as normal boot, |
| 530 | * so some memory area under 1M become dirty, so before this happen, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 531 | * I need to backup the content of mem to top-mem. |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 532 | * |
| 533 | * I will reserve the 1M top-men in LBIO table in coreboot_table.c |
| 534 | * and recovery the content of 1M-mem in wakeup.c. |
| 535 | */ |
| 536 | #if PAYLOAD_IS_SEABIOS == 1 |
| 537 | if (boot_mode == 3) { |
| 538 | /* An idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html |
| 539 | * |
| 540 | * I want move the 1M data, I have to set some MTRRs myself. |
| 541 | * Setting MTRR before back memory save s3 resume time about |
| 542 | * 0.14 seconds. |
| 543 | * |
| 544 | * !!! Since CAR stack uses cache, and we are using cache |
| 545 | * here, we must be careful: |
| 546 | * |
| 547 | * 1. during this MTRR code, must no function call (after |
| 548 | * this MTRR, I think it should be OK to use function). |
| 549 | * 2. Before stack switch, no use variable that have value |
| 550 | * set before this. |
| 551 | * 3. Due to 2, take care of "cpu_reset", I directlly set it |
| 552 | * to ZERO. |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 553 | */ |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 554 | u32 memtop = *(u32 *) WAKE_MEM_INFO; |
| 555 | u32 memtop1 = *(u32 *) WAKE_MEM_INFO - 0x100000; |
| 556 | u32 memtop2 = *(u32 *) WAKE_MEM_INFO - 0x200000; |
| 557 | u32 memtop3 = *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000; |
| 558 | u32 memtop4 = |
| 559 | *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 + 0xe0000; |
| 560 | #if 0 |
| 561 | __asm__ volatile ( |
| 562 | "movl $0x204, %%ecx\n\t" |
| 563 | "xorl %%edx, %%edx\n\t" |
| 564 | "movl %0,%%eax\n\t" |
| 565 | "orl $(0 | 6), %%eax\n\t" |
| 566 | "wrmsr\n\t" |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 567 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 568 | "movl $0x205, %%ecx\n\t" |
| 569 | "xorl %%edx, %%edx\n\t" |
| 570 | "movl $0x100000,%%eax\n\t" |
| 571 | "decl %%eax\n\t" |
| 572 | "notl %%eax\n\t" |
| 573 | "orl $(0 | 0x800), %%eax\n\t" |
| 574 | "wrmsr\n\t" |
| 575 | ::"g"(memtop2) |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 576 | ); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 577 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 578 | __asm__ volatile ( |
| 579 | "movl $0x206, %%ecx\n\t" |
| 580 | "xorl %%edx, %%edx\n\t" |
| 581 | "movl %0,%%eax\n\t" |
| 582 | "orl $(0 | 6), %%eax\n\t" |
| 583 | "wrmsr\n\t" |
| 584 | |
| 585 | "movl $0x207, %%ecx\n\t" |
| 586 | "xorl %%edx, %%edx\n\t" |
| 587 | "movl $0x100000,%%eax\n\t" |
| 588 | "decl %%eax\n\t" |
| 589 | "notl %%eax\n\t" |
| 590 | "orl $(0 | 0x800), %%eax\n\t" |
| 591 | "wrmsr\n\t" |
| 592 | ::"g"(memtop1) |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 593 | ); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 594 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 595 | __asm__ volatile ( |
| 596 | "movl $0x208, %ecx\n\t" |
| 597 | "xorl %edx, %edx\n\t" |
| 598 | "movl $0,%eax\n\t" |
| 599 | "orl $(0 | 6), %eax\n\t" |
| 600 | "wrmsr\n\t" |
| 601 | |
| 602 | "movl $0x209, %ecx\n\t" |
| 603 | "xorl %edx, %edx\n\t" |
| 604 | "movl $0x100000,%eax\n\t" |
| 605 | "decl %eax\n\t" |
| 606 | "notl %eax\n\t" |
| 607 | "orl $(0 | 0x800), %eax\n\t" |
| 608 | "wrmsr\n\t" |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 609 | ); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 610 | #endif |
| 611 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 612 | /* |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 613 | * WAKE_MEM_INFO is inited in get_set_top_available_mem() |
| 614 | * in tables.c these two memcpy() not not be enabled if set |
| 615 | * the MTRR around this two lines. |
| 616 | */ |
| 617 | #if 0 |
| 618 | __asm__ volatile ( |
| 619 | "movl $0, %%esi\n\t" |
| 620 | "movl %0, %%edi\n\t" |
| 621 | "movl $0xa0000, %%ecx\n\t" |
| 622 | "shrl $2, %%ecx\n\t" |
| 623 | "rep movsd\n\t" |
| 624 | ::"g"(memtop3) |
| 625 | ); |
| 626 | |
| 627 | __asm__ volatile ( |
| 628 | "movl $0xe0000, %%esi\n\t" |
| 629 | "movl %0, %%edi\n\t" |
| 630 | "movl $0x20000, %%ecx\n\t" |
| 631 | "shrl $2, %%ecx\n\t" |
| 632 | "rep movsd\n\t" |
| 633 | ::"g"(memtop4) |
| 634 | ); |
| 635 | #endif |
| 636 | /* This can have function call, because no variable used before this. */ |
Elyes HAOUAS | aedcc10 | 2014-07-21 08:07:19 +0200 | [diff] [blame] | 637 | print_debug("Copy memory to high memory to protect s3 wakeup vector code\n"); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 638 | memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - |
| 639 | 0x100000), (unsigned char *)0, 0xa0000); |
| 640 | memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - |
| 641 | 0x100000 + 0xe0000), (unsigned char *)0xe0000, 0x20000); |
| 642 | |
| 643 | /* Restore the MTRR previously modified. */ |
| 644 | #if 0 |
| 645 | __asm__ volatile ( |
| 646 | "wbinvd\n\t" |
| 647 | "xorl %edx, %edx\n\t" |
| 648 | "xorl %eax, %eax\n\t" |
| 649 | "movl $0x204, %ecx\n\t" |
| 650 | "wrmsr\n\t" |
| 651 | "movl $0x205, %ecx\n\t" |
| 652 | "wrmsr\n\t" |
| 653 | "movl $0x206, %ecx\n\t" |
| 654 | "wrmsr\n\t" |
| 655 | "movl $0x207, %ecx\n\t" |
| 656 | "wrmsr\n\t" |
| 657 | "movl $0x208, %ecx\n\t" |
| 658 | "wrmsr\n\t" |
| 659 | "movl $0x209, %ecx\n\t" |
| 660 | "wrmsr\n\t" |
| 661 | ); |
| 662 | #endif |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 663 | } |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 664 | #endif |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 665 | } |