Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 One Laptop per Child, Association, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | /* |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 21 | * Part of this file is from cx700 port, part of is from cn700 port, |
| 22 | * and acpi_is_wakeup_early_via_VX800() is part of Rudolf's S3 patch. |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 23 | */ |
| 24 | |
| 25 | #define ASSEMBLY 1 |
| 26 | #define __ROMCC__ |
| 27 | #define RAMINIT_SYSINFO 1 |
| 28 | #define CACHE_AS_RAM_ADDRESS_DEBUG 0 |
| 29 | |
| 30 | #include <stdint.h> |
| 31 | #include <device/pci_def.h> |
| 32 | #include <device/pci_ids.h> |
| 33 | #include <arch/io.h> |
| 34 | #include <device/pnp_def.h> |
| 35 | #include <arch/romcc_io.h> |
| 36 | #include <arch/hlt.h> |
| 37 | #include "pc80/serial.c" |
| 38 | #include "arch/i386/lib/console.c" |
| 39 | #include "ram/ramtest.c" |
| 40 | #include "northbridge/via/vx800/vx800.h" |
| 41 | #include "cpu/x86/mtrr/earlymtrr.c" |
| 42 | #include "cpu/x86/bist.h" |
| 43 | #include "pc80/udelay_io.c" |
| 44 | #include "lib/delay.c" |
| 45 | #if CONFIG_USE_INIT == 0 |
| 46 | #include "lib/memcpy.c" |
| 47 | #endif |
| 48 | #include "cpu/x86/lapic/boot_cpu.c" |
| 49 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 50 | /* This file contains the board-special SI value for raminit.c. */ |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 51 | #include "driving_clk_phase_data.c" |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 52 | |
| 53 | #include "northbridge/via/vx800/raminit.h" |
| 54 | #include "northbridge/via/vx800/raminit.c" |
| 55 | #include "cpu/x86/car/copy_and_run.c" |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 56 | #include "wakeup.h" |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 57 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 58 | /* |
| 59 | * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: |
| 60 | * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. |
| 61 | */ |
| 62 | void jason_tsc_count_car(void) |
| 63 | { |
| 64 | #if 0 |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 65 | unsigned long long start; |
| 66 | asm volatile ("rdtsc" : "=A" (start)); |
| 67 | start >>= 20; |
| 68 | print_emerg("jason_tsc_count_car= "); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 69 | print_emerg_hex32((unsigned long) start); |
| 70 | print_emerg("\n"); |
| 71 | #endif |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 72 | } |
| 73 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 74 | int acpi_is_wakeup_early_via_vx800(void) |
| 75 | { |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 76 | device_t dev; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 77 | u16 tmp, result; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 78 | |
| 79 | print_debug("In acpi_is_wakeup_early_via_vx800\r\n"); |
| 80 | /* Power management controller */ |
| 81 | dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, |
| 82 | PCI_DEVICE_ID_VIA_VX855_LPC), 0); |
| 83 | |
| 84 | if (dev == PCI_DEV_INVALID) |
| 85 | die("Power management controller not found\r\n"); |
| 86 | |
| 87 | /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ |
| 88 | pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); |
| 89 | |
| 90 | /* Enable ACPI accessm RTC signal gated with PSON. */ |
| 91 | pci_write_config8(dev, 0x81, 0x84); |
| 92 | |
| 93 | tmp = inw(VX800_ACPI_IO_BASE + 0x04); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 94 | result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 95 | print_debug(" boot_mode="); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 96 | print_debug_hex16(result); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 97 | print_debug("\r\n"); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 98 | return result; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 102 | { |
| 103 | return smbus_read_byte(device, address); |
| 104 | } |
| 105 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 106 | /* All content of this function came from the cx700 port of coreboot. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 107 | static void enable_mainboard_devices(void) |
| 108 | { |
| 109 | device_t dev; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 110 | uint16_t values; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 111 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 112 | #if 0 |
| 113 | /* |
| 114 | * Add and close this switch, since some line cause error, some |
| 115 | * written at elsewhere (stage1 stage2). |
| 116 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 117 | u8 regdata; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 118 | dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, |
| 119 | PCI_DEVICE_ID_VIA_VX855_LPC), 0); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 120 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 121 | /* Disable GP3. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 122 | pci_write_config8(dev, 0x98, 0x00); |
| 123 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 124 | pci_write_config8(dev, 0x50, 0x80); /* Disable mc97. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 125 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 126 | /* |
| 127 | * Martin: Disable internal KBC configuration. |
| 128 | * |
| 129 | * Internal Config is needed to decide which key can be pressed to |
| 130 | * resume from s3. |
| 131 | */ |
| 132 | pci_write_config8(dev, 0x51, 0x2d); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 133 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 134 | /* This causes irq0 can not be triggerd, since bit 5 was set to 0. */ |
| 135 | /* pci_write_config8(dev, 0x58, 0x42); */ |
| 136 | |
| 137 | /* These writing may... TODO */ |
| 138 | regdata = pci_read_config8(dev, 0x58); |
| 139 | regdata |= 0x41; |
| 140 | pci_write_config8(dev, 0x58, regdata); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 141 | pci_write_config8(dev, 0x59, 0x80); |
| 142 | pci_write_config8(dev, 0x5b, 0x01); |
| 143 | #endif |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 144 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 145 | print_debug("In enable_mainboard_devices \r\n"); |
| 146 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 147 | /* Enable P2P Bridge Header for external PCI bus. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 148 | dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 149 | pci_write_config8(dev, 0x4f, 0x41); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 150 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 151 | /* |
| 152 | * "5324" already is the default value of the PCI IDE device, cancel |
| 153 | * this PCI write. |
| 154 | * |
| 155 | * [william 20080124]: Fix bug that can not boot Ubuntu at the |
| 156 | * beginning time. |
| 157 | */ |
| 158 | #if 0 |
| 159 | dev = 0; |
| 160 | dev = pci_locate_device(PCI_ID(0x1106, PCI_DEVICE_ID_VIA_VX855_IDE), 0); |
| 161 | values = pci_read_config16(dev, 0xBA); |
| 162 | values &= ~0xffff; |
| 163 | values |= 0x5324; |
| 164 | pci_write_config16(dev, 0xBA, values); |
| 165 | #endif |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 166 | } |
| 167 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 168 | /* |
| 169 | * Most content of this function came from the cx700 port of coreboot. |
| 170 | * Turn on the shadow of E-seg. |
| 171 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 172 | static void enable_shadow_ram(void) |
| 173 | { |
| 174 | uint8_t shadowreg; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 175 | |
| 176 | /* |
| 177 | * Changed the value from 0x2a to 0x3f. "read only" may block "write"? |
| 178 | * and maybe in C-seg "write" will be needed? |
| 179 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 180 | pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 181 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 182 | /* 0xf0000-0xfffff - ACPI tables */ |
| 183 | shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83); |
| 184 | shadowreg |= 0x30; |
| 185 | pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 186 | |
| 187 | /* 0xe0000-0xeffff - elfload? */ |
| 188 | /* |
| 189 | * In s3 resume process, wakeup.c, I use E-seg to hold the code |
| 190 | * (which can not locate in the area to be covered) that will copy |
| 191 | * 0-A-seg and F-seg from TOP-mem back to their normal location. |
| 192 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 193 | pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 194 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 195 | #if 0 |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 196 | /* Enable shadow RAM as normal DRAM */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 197 | /* 0xc0000-0xcffff - VGA BIOS */ |
| 198 | pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a); |
| 199 | pci_write_config8(PCI_DEV(0, 0, 7), 0x61, 0x00); |
| 200 | /* 0xd0000-0xdffff - ?? */ |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 201 | /* pci_write_config8(PCI_DEV(0, 0, 3), 0x81, 0xff); */ |
| 202 | /* pci_write_config8(PCI_DEV(0, 0, 7), 0x62, 0xff); */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 203 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 204 | /* Do it again for the vlink controller. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 205 | shadowreg = pci_read_config8(PCI_DEV(0, 0, 7), 0x63); |
| 206 | shadowreg |= 0x30; |
| 207 | pci_write_config8(PCI_DEV(0, 0, 7), 0x63, shadowreg); |
| 208 | #endif |
| 209 | } |
| 210 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 211 | /* |
| 212 | * Added this table 2008-11-28. |
| 213 | * This table contains the value needed to be set before begin to init DRAM. |
| 214 | * Note: REV_Bx should be checked for changes when porting a new board! |
| 215 | */ |
| 216 | static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { |
| 217 | /* VT3409 no PCI-E */ |
| 218 | 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range |
| 219 | 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 220 | // 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 221 | // Set ROMSIP value by software |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 222 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 223 | /* |
| 224 | 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3 |
| 225 | 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3 |
| 226 | 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3 |
| 227 | 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3 |
| 228 | 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl |
| 229 | 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl |
| 230 | 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit |
| 231 | 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status |
| 232 | 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset |
| 233 | 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset |
| 234 | 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status |
| 235 | 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status |
| 236 | 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group |
| 237 | 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group |
| 238 | 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group |
| 239 | 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus) |
| 240 | 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) |
| 241 | 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) |
| 242 | 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) |
| 243 | 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) |
| 244 | 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1 |
| 245 | 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2 |
| 246 | 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB |
| 247 | 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD |
| 248 | 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0) |
| 249 | 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1) |
| 250 | 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2) |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 251 | 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) |
| 252 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 253 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 254 | // CPU Host Bus Control |
| 255 | 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 256 | // 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 257 | 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW |
| 258 | 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 259 | // 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 260 | 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK |
| 261 | 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 262 | // 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 263 | 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2 |
| 264 | 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1 |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 265 | // 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL |
| 266 | // 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 267 | 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy |
| 268 | 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer |
| 269 | 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 270 | // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 |
| 271 | // 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 272 | 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2 |
| 273 | 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3 |
| 274 | 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4 |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 275 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 276 | // Set APIC and SMRAM |
| 277 | 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control |
| 278 | 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg |
| 279 | 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // End of the table |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 280 | }; |
| 281 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 282 | #define USE_VCP 1 /* 0 means "use DVP". */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 283 | #define USE_COM1 1 |
| 284 | #define USE_COM2 0 |
| 285 | |
| 286 | #define gCom1Base 0x3f8 |
| 287 | #define gCom2Base 0x2f8 |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 288 | |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 289 | void EmbedComInit(void) |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 290 | { |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 291 | u8 ByteVal; |
| 292 | u16 ComBase; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 293 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 294 | /* Enable NB multiple function control. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 295 | ByteVal = pci_read_config8(PCI_DEV(0, 0, 0), 0x4f); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 296 | ByteVal = ByteVal | 0x01; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 297 | pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, ByteVal); |
| 298 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 299 | /* VGA enable. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 300 | ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA1); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 301 | ByteVal = ByteVal | 0x80; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 302 | pci_write_config8(PCI_DEV(0, 0, 3), 0xA1, ByteVal); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 303 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 304 | ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA7); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 305 | ByteVal = ByteVal | 0x08; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 306 | pci_write_config8(PCI_DEV(0, 0, 3), 0xA7, ByteVal); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 307 | |
| 308 | /* Enable P2P IO/mem. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 309 | ByteVal = pci_read_config8(PCI_DEV(0, 1, 0), 0x4); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 310 | ByteVal = ByteVal | 0x07; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 311 | pci_write_config8(PCI_DEV(0, 1, 0), 0x4, ByteVal); |
| 312 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 313 | /* Turn on graphic chip I/O port port access. */ |
| 314 | ByteVal = inb(0x3C3); |
| 315 | ByteVal = ByteVal | 0x01; |
| 316 | outb(ByteVal, 0x3C3); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 317 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 318 | /* Turn off graphic chip register protection. */ |
| 319 | outb(0x10, 0x3C4); |
| 320 | ByteVal = inb(0x3C5); |
| 321 | ByteVal = ByteVal | 0x01; |
| 322 | outb(ByteVal, 0x3C5); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 323 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 324 | /* South module pad share enable 0x3C5.78[7]. */ |
| 325 | outb(0x78, 0x3C4); |
| 326 | ByteVal = inb(0x3C5); |
| 327 | ByteVal = ByteVal | 0x80; |
| 328 | outb(ByteVal, 0x3C5); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 329 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 330 | /* Enable UART function multiplex with DVP or VCP pad D17F0Rx46[7,6]. */ |
| 331 | ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0x46); |
| 332 | if (USE_VCP == 1) |
| 333 | ByteVal = (ByteVal & 0x3F) | 0x40; /* Multiplex with VCP. */ |
| 334 | else |
| 335 | ByteVal = (ByteVal & 0x3F) | 0xC0; /* Multiplex with DVP. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 336 | pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal); |
| 337 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 338 | /* Enable embedded COM1 and COM2 D17F0RxB0[5,4]. */ |
| 339 | ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0); |
| 340 | ByteVal = ByteVal & 0xcf; |
| 341 | /* Multiplex with VCP. */ |
| 342 | if (USE_COM1 == 1) |
| 343 | ByteVal = ByteVal | 0x10; |
| 344 | if (USE_COM2 == 1) |
| 345 | ByteVal = ByteVal | 0x20; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 346 | pci_write_config8(PCI_DEV(0, 17, 0), 0xB0, ByteVal); |
| 347 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 348 | if (USE_COM1 == 1) |
| 349 | ComBase = gCom1Base; |
| 350 | else |
| 351 | ComBase = gCom2Base; |
| 352 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 353 | //noharddrive |
| 354 | |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 355 | /* Set embedded COM1 I/O base = 0x3E8 (D17F0RB4, ByteVal = 0xFD) */ |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 356 | if (USE_COM1 == 1) { |
| 357 | ByteVal = (u8) ((gCom1Base >> 3) | 0x80); |
| 358 | pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal); |
| 359 | ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); |
| 360 | ByteVal = (ByteVal & 0xf0) | 0x04; |
| 361 | pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); |
| 362 | } |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 363 | |
Uwe Hermann | d64f403 | 2009-06-07 14:38:32 +0000 | [diff] [blame^] | 364 | /* Set embedded COM2 I/O base = 0x2E8 (D17F0RB5, ByteVal = 0xDD). */ |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 365 | if (USE_COM2 == 1) { |
| 366 | ByteVal = (u8) ((gCom2Base >> 3) | 0x80); |
| 367 | pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal); |
| 368 | ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); |
| 369 | ByteVal = (ByteVal & 0x0f) | 0x30; |
| 370 | pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); |
| 371 | } |
| 372 | /* No port 80 biger then 0x10. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 373 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 374 | /* Disable interrupt. */ |
| 375 | ByteVal = inb(ComBase + 3); |
| 376 | outb(ByteVal & 0x7F, ComBase + 3); |
| 377 | outb(0x00, ComBase + 1); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 378 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 379 | /* Set BAUD rate. */ |
| 380 | ByteVal = inb(ComBase + 3); |
| 381 | outb(ByteVal | 0x80, ComBase + 3); |
| 382 | outb(0x01, ComBase); |
| 383 | outb(0x00, ComBase + 1); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 384 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 385 | /* Set frame format. */ |
| 386 | ByteVal = inb(ComBase + 3); |
| 387 | outb(ByteVal & 0x3F, ComBase + 3); |
| 388 | outb(0x03, ComBase + 3); |
| 389 | outb(0x00, ComBase + 2); |
| 390 | outb(0x00, ComBase + 4); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 391 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 392 | /* SOutput("Embedded COM output\n"); */ |
| 393 | /* while(1); */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 394 | } |
| 395 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 396 | /* cache_as_ram.inc jumps to here. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 397 | void amd64_main(unsigned long bist) |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 398 | { |
| 399 | unsigned cpu_reset = 0; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 400 | u16 boot_mode; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 401 | u8 rambits, Data8, Data; |
| 402 | device_t device; |
| 403 | /* device_t dev; */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 404 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 405 | /* |
| 406 | * Enable multifunction for northbridge. These 4 lines (until |
| 407 | * console_init()) are the same with epia-cn port. |
| 408 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 409 | pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 410 | EmbedComInit(); |
| 411 | /* enable_vx800_serial(); */ |
| 412 | /* uart_init(); */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 413 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 414 | /* |
| 415 | * 1. D15F0 |
| 416 | * a) RxBAh = 71h |
| 417 | * b) RxBBh = 05h |
| 418 | * c) RxBEh = 71h |
| 419 | * d) RxBFh = 05h |
| 420 | * |
| 421 | * 2. D17F0 |
| 422 | * a) RxA0h = 06h |
| 423 | * b) RxA1h = 11h |
| 424 | * c) RxA2h = 27h |
| 425 | * d) RxA3h = 32h |
| 426 | * e) Rx79h = 40h |
| 427 | * f) Rx72h = 27h |
| 428 | * g) Rx73h = 32h |
| 429 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 430 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 431 | jason_tsc_count_car(); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 432 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 433 | pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA, |
| 434 | PCI_DEVICE_ID_VIA_VX855_IDE); |
| 435 | pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE, |
| 436 | PCI_DEVICE_ID_VIA_VX855_IDE); |
| 437 | pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA0, PCI_VENDOR_ID_VIA); |
| 438 | pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA2, |
| 439 | PCI_DEVICE_ID_VIA_VX855_LPC); |
| 440 | Data8 = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x79); |
| 441 | Data8 &= ~0x40; |
| 442 | Data8 |= 0x40; |
| 443 | pci_write_config8(PCI_DEV(0, 0x11, 0), 0x79, Data8); |
| 444 | pci_write_config16(PCI_DEV(0, 0x11, 0), 0x72, |
| 445 | PCI_DEVICE_ID_VIA_VX855_LPC); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 446 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 447 | /* |
| 448 | * There are two function definitions of console_init(), while the |
| 449 | * src/arch/i386/lib is the right one. |
| 450 | */ |
| 451 | console_init(); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 452 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 453 | /* Decide if this is a s3 wakeup or a normal boot. */ |
| 454 | boot_mode = acpi_is_wakeup_early_via_vx800(); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 455 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 456 | /* |
| 457 | * 2008-11-27 Add this, to transfer "cpu restart" to "cold boot". |
| 458 | * When this boot is not a S3 resume, and PCI registers had been |
| 459 | * written, then this must be a CPU restart (result of OS reboot cmd), |
| 460 | * so we need a real "cold boot". |
| 461 | */ |
| 462 | jason_tsc_count_car(); |
| 463 | if ((boot_mode != 3) |
| 464 | && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) { |
| 465 | outb(6, 0xcf9); |
| 466 | } |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 467 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 468 | /* x86 cold boot I/O cmd. */ |
| 469 | /* These 2 lines are the same with epia-cn port. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 470 | enable_smbus(); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 471 | jason_tsc_count_car(); |
| 472 | |
| 473 | /* This fix does help vx800!, but vx855 doesn't need this. */ |
| 474 | /* smbus_fixup(&ctrl); */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 475 | |
| 476 | if (bist == 0) { |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 477 | /* |
| 478 | * CAR needs MTRR until memory is ok, so disable this |
| 479 | * early_mtrr_init() call. |
| 480 | */ |
| 481 | #if 0 |
| 482 | print_debug("doing early_mtrr\r\n"); |
| 483 | early_mtrr_init(); |
| 484 | #endif |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 485 | } |
| 486 | |
| 487 | /* Halt if there was a built-in self test failure. */ |
| 488 | report_bist_failure(bist); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 489 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 490 | print_debug("Enabling mainboard devices\r\n"); |
| 491 | enable_mainboard_devices(); |
| 492 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 493 | /* |
| 494 | * Get NB chip revision from D0F4RxF6, revision will be used in |
| 495 | * via_pci_inittable. |
| 496 | */ |
| 497 | device = PCI_DEV(0, 0, 4); |
| 498 | Data = pci_read_config8(device, 0xf6); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 499 | print_debug("NB chip revision ="); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 500 | print_debug_hex8(Data); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 501 | print_debug("\r\n"); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 502 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 503 | /* Make NB ready before DRAM init. */ |
| 504 | via_pci_inittable(Data, mNbStage1InitTbl); |
| 505 | |
| 506 | /* |
| 507 | * When resume from s3, DRAM init is skipped, so need to recovery |
| 508 | * any PCI register related to DRAM init. d0f3 didn't lose its power |
| 509 | * during whole s3 time, so any register not belonging to d0f3 needs |
| 510 | * to be recovered. |
| 511 | */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 512 | #if 1 |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 513 | if (boot_mode == 3) { |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 514 | u8 i; |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 515 | u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 516 | DRAM_SYS_ATTR DramAttr; |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 517 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 518 | print_debug("This is an S3 wakeup\r\n"); |
| 519 | |
| 520 | memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR)); |
| 521 | /* |
| 522 | * Step 1: DRAM detection; DDR1 or DDR2; Get SPD Data; |
| 523 | * Rank Presence; 64 or 128bit; Unbuffered or registered; |
| 524 | * 1T or 2T. |
| 525 | */ |
| 526 | DRAMDetect(&DramAttr); |
| 527 | |
| 528 | /* |
| 529 | * Begin to get RAM size, 43,42 41 40 contains the end |
| 530 | * address of last rank in DDR2 slot. |
| 531 | */ |
| 532 | device = PCI_DEV(0, 0, 3); |
| 533 | for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 534 | rambits = pci_read_config8(device, ramregs[i]); |
| 535 | if (rambits != 0) |
| 536 | break; |
| 537 | } |
| 538 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 539 | DRAMDRDYSetting(&DramAttr); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 540 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 541 | Data = 0x80; /* This value is same with DevInit.c. */ |
| 542 | pci_write_config8(PCI_DEV(0, 0, 4), 0xa3, Data); |
| 543 | pci_write_config8(PCI_DEV(0, 17, 7), 0x60, rambits << 2); |
| 544 | Data = pci_read_config8(MEMCTRL, 0x88); |
| 545 | pci_write_config8(PCI_DEV(0, 17, 7), 0xE5, Data); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 546 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 547 | /* Just copy this function from draminit to here! */ |
| 548 | DRAMRegFinalValue(&DramAttr); |
| 549 | |
| 550 | /* Just copy this function from draminit to here! */ |
| 551 | SetUMARam(); |
| 552 | |
| 553 | print_debug("Resume from S3, RAM init was ignored\r\n"); |
| 554 | } else { |
| 555 | ddr2_ram_setup(); |
| 556 | ram_check(0, 640 * 1024); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 557 | } |
| 558 | #endif |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 559 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 560 | /* ddr2_ram_setup(); */ |
| 561 | /* This line is the same with cx700 port. */ |
| 562 | enable_shadow_ram(); |
| 563 | |
| 564 | jason_tsc_count_car(); |
| 565 | |
| 566 | /* |
| 567 | * For coreboot most time of S3 resume is the same as normal boot, |
| 568 | * so some memory area under 1M become dirty, so before this happen, |
| 569 | * I need to backup the content of mem to top-mem. |
| 570 | * |
| 571 | * I will reserve the 1M top-men in LBIO table in coreboot_table.c |
| 572 | * and recovery the content of 1M-mem in wakeup.c. |
| 573 | */ |
| 574 | #if PAYLOAD_IS_SEABIOS == 1 |
| 575 | if (boot_mode == 3) { |
| 576 | /* An idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html |
| 577 | * |
| 578 | * I want move the 1M data, I have to set some MTRRs myself. |
| 579 | * Setting MTRR before back memory save s3 resume time about |
| 580 | * 0.14 seconds. |
| 581 | * |
| 582 | * !!! Since CAR stack uses cache, and we are using cache |
| 583 | * here, we must be careful: |
| 584 | * |
| 585 | * 1. during this MTRR code, must no function call (after |
| 586 | * this MTRR, I think it should be OK to use function). |
| 587 | * 2. Before stack switch, no use variable that have value |
| 588 | * set before this. |
| 589 | * 3. Due to 2, take care of "cpu_reset", I directlly set it |
| 590 | * to ZERO. |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 591 | */ |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 592 | u32 memtop = *(u32 *) WAKE_MEM_INFO; |
| 593 | u32 memtop1 = *(u32 *) WAKE_MEM_INFO - 0x100000; |
| 594 | u32 memtop2 = *(u32 *) WAKE_MEM_INFO - 0x200000; |
| 595 | u32 memtop3 = *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000; |
| 596 | u32 memtop4 = |
| 597 | *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 + 0xe0000; |
| 598 | #if 0 |
| 599 | __asm__ volatile ( |
| 600 | "movl $0x204, %%ecx\n\t" |
| 601 | "xorl %%edx, %%edx\n\t" |
| 602 | "movl %0,%%eax\n\t" |
| 603 | "orl $(0 | 6), %%eax\n\t" |
| 604 | "wrmsr\n\t" |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 605 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 606 | "movl $0x205, %%ecx\n\t" |
| 607 | "xorl %%edx, %%edx\n\t" |
| 608 | "movl $0x100000,%%eax\n\t" |
| 609 | "decl %%eax\n\t" |
| 610 | "notl %%eax\n\t" |
| 611 | "orl $(0 | 0x800), %%eax\n\t" |
| 612 | "wrmsr\n\t" |
| 613 | ::"g"(memtop2) |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 614 | ); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 615 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 616 | __asm__ volatile ( |
| 617 | "movl $0x206, %%ecx\n\t" |
| 618 | "xorl %%edx, %%edx\n\t" |
| 619 | "movl %0,%%eax\n\t" |
| 620 | "orl $(0 | 6), %%eax\n\t" |
| 621 | "wrmsr\n\t" |
| 622 | |
| 623 | "movl $0x207, %%ecx\n\t" |
| 624 | "xorl %%edx, %%edx\n\t" |
| 625 | "movl $0x100000,%%eax\n\t" |
| 626 | "decl %%eax\n\t" |
| 627 | "notl %%eax\n\t" |
| 628 | "orl $(0 | 0x800), %%eax\n\t" |
| 629 | "wrmsr\n\t" |
| 630 | ::"g"(memtop1) |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 631 | ); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 632 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 633 | __asm__ volatile ( |
| 634 | "movl $0x208, %ecx\n\t" |
| 635 | "xorl %edx, %edx\n\t" |
| 636 | "movl $0,%eax\n\t" |
| 637 | "orl $(0 | 6), %eax\n\t" |
| 638 | "wrmsr\n\t" |
| 639 | |
| 640 | "movl $0x209, %ecx\n\t" |
| 641 | "xorl %edx, %edx\n\t" |
| 642 | "movl $0x100000,%eax\n\t" |
| 643 | "decl %eax\n\t" |
| 644 | "notl %eax\n\t" |
| 645 | "orl $(0 | 0x800), %eax\n\t" |
| 646 | "wrmsr\n\t" |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 647 | ); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 648 | #endif |
| 649 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 650 | /* |
| 651 | * WAKE_MEM_INFO is inited in get_set_top_available_mem() |
| 652 | * in tables.c these two memcpy() not not be enabled if set |
| 653 | * the MTRR around this two lines. |
| 654 | */ |
| 655 | #if 0 |
| 656 | __asm__ volatile ( |
| 657 | "movl $0, %%esi\n\t" |
| 658 | "movl %0, %%edi\n\t" |
| 659 | "movl $0xa0000, %%ecx\n\t" |
| 660 | "shrl $2, %%ecx\n\t" |
| 661 | "rep movsd\n\t" |
| 662 | ::"g"(memtop3) |
| 663 | ); |
| 664 | |
| 665 | __asm__ volatile ( |
| 666 | "movl $0xe0000, %%esi\n\t" |
| 667 | "movl %0, %%edi\n\t" |
| 668 | "movl $0x20000, %%ecx\n\t" |
| 669 | "shrl $2, %%ecx\n\t" |
| 670 | "rep movsd\n\t" |
| 671 | ::"g"(memtop4) |
| 672 | ); |
| 673 | #endif |
| 674 | /* This can have function call, because no variable used before this. */ |
| 675 | print_debug("Copy memory to high memory to protect s3 wakeup vector code \r\n"); |
| 676 | memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - |
| 677 | 0x100000), (unsigned char *)0, 0xa0000); |
| 678 | memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - |
| 679 | 0x100000 + 0xe0000), (unsigned char *)0xe0000, 0x20000); |
| 680 | |
| 681 | /* Restore the MTRR previously modified. */ |
| 682 | #if 0 |
| 683 | __asm__ volatile ( |
| 684 | "wbinvd\n\t" |
| 685 | "xorl %edx, %edx\n\t" |
| 686 | "xorl %eax, %eax\n\t" |
| 687 | "movl $0x204, %ecx\n\t" |
| 688 | "wrmsr\n\t" |
| 689 | "movl $0x205, %ecx\n\t" |
| 690 | "wrmsr\n\t" |
| 691 | "movl $0x206, %ecx\n\t" |
| 692 | "wrmsr\n\t" |
| 693 | "movl $0x207, %ecx\n\t" |
| 694 | "wrmsr\n\t" |
| 695 | "movl $0x208, %ecx\n\t" |
| 696 | "wrmsr\n\t" |
| 697 | "movl $0x209, %ecx\n\t" |
| 698 | "wrmsr\n\t" |
| 699 | ); |
| 700 | #endif |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 701 | } |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 702 | |
| 703 | #endif |
| 704 | |
| 705 | /* |
| 706 | * The following code is copied from tyan\s2735\cache_as_ram_auto.c. |
| 707 | * Only the code around CLEAR_FIRST_1M_RAM is changed. Removed all the code |
| 708 | * around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c". |
| 709 | * The CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop |
| 710 | * at somewhere, and cpu/x86/car/cache_as_ram_post.c do not cache my |
| 711 | * $XIP_ROM_BASE+SIZE area. |
| 712 | * |
| 713 | * Use #include "cpu/via/car/cache_as_ram_post.c". This version post.c have |
| 714 | * some diff with x86-version. |
| 715 | */ |
| 716 | #if 1 |
| 717 | { |
| 718 | /* |
| 719 | * Check value of esp to verify if we have enough ROM for |
| 720 | * stack in Cache as RAM. |
| 721 | */ |
| 722 | unsigned v_esp; |
| 723 | __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)); |
| 724 | #if CONFIG_USE_INIT |
| 725 | printk_debug("v_esp=%08x\r\n", v_esp); |
| 726 | #else |
| 727 | print_debug("v_esp="); |
| 728 | print_debug_hex32(v_esp); |
| 729 | print_debug("\r\n"); |
| 730 | #endif |
| 731 | } |
| 732 | #endif |
| 733 | |
| 734 | #if 1 |
| 735 | cpu_reset_x: |
| 736 | |
| 737 | /* It seems that cpu_reset is not used before this, so I just reset |
| 738 | * it, (this is because the s3 resume, setting in MTRR and copy data |
| 739 | * may destroy stack. |
| 740 | */ |
| 741 | cpu_reset = 0; |
| 742 | |
| 743 | #if CONFIG_USE_INIT |
| 744 | printk_debug("cpu_reset = %08x\r\n", cpu_reset); |
| 745 | #else |
| 746 | print_debug("cpu_reset = "); |
| 747 | print_debug_hex32(cpu_reset); |
| 748 | print_debug("\r\n"); |
| 749 | #endif |
| 750 | |
| 751 | if (cpu_reset == 0) |
| 752 | print_debug("Clearing initial memory region: "); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 753 | print_debug("No cache as ram now - "); |
| 754 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 755 | /* Store cpu_reset to ebx. */ |
| 756 | __asm__ volatile ("movl %0, %%ebx\n\t"::"a" (cpu_reset)); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 757 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 758 | /* |
| 759 | * Cancel these lines, CLEAR_FIRST_1M_RAM cause the |
| 760 | * cpu/x86/car/cache_as_ram_post.c stop at somewhere. |
| 761 | */ |
| 762 | #if 0 |
| 763 | if (cpu_reset == 0) { |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 764 | #define CLEAR_FIRST_1M_RAM 1 |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 765 | #include "cpu/via/car/cache_as_ram_post.c" |
| 766 | } else { |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 767 | #undef CLEAR_FIRST_1M_RAM |
| 768 | #include "cpu/via/car/cache_as_ram_post.c" |
| 769 | } |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 770 | #endif |
| 771 | |
| 772 | #include "cpu/via/car/cache_as_ram_post.c" |
| 773 | /* #include "cpu/x86/car/cache_as_ram_post.c" */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 774 | __asm__ volatile ( |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 775 | /* Set new esp *//* before _RAMBASE */ |
| 776 | "subl %0, %%ebp\n\t" |
| 777 | "subl %0, %%esp\n\t":: |
| 778 | "a" ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE) - _RAMBASE) |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 779 | ); |
| 780 | |
| 781 | { |
| 782 | unsigned new_cpu_reset; |
| 783 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 784 | /* Get back cpu_reset from ebx. */ |
| 785 | __asm__ volatile ("movl %%ebx, %0\n\t":"=a" (new_cpu_reset)); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 786 | |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 787 | /* We can't go back anymore, we lost old stack data in CAR. */ |
| 788 | if (new_cpu_reset == 0) |
| 789 | print_debug("Use Ram as Stack now - done\r\n"); |
| 790 | else |
| 791 | print_debug("Use Ram as Stack now - \r\n"); |
| 792 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 793 | #if CONFIG_USE_INIT |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 794 | printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 795 | #else |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 796 | print_debug("new_cpu_reset = "); |
| 797 | print_debug_hex32(new_cpu_reset); |
| 798 | print_debug("\r\n"); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 799 | #endif |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 800 | |
| 801 | jason_tsc_count_car(); |
| 802 | /* Copy and execute coreboot_ram. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 803 | copy_and_run(new_cpu_reset); |
Uwe Hermann | 0ffff34 | 2009-06-07 13:46:50 +0000 | [diff] [blame] | 804 | /* We will not return. */ |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 805 | } |
| 806 | #endif |
| 807 | |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 808 | print_debug("should not be here -\r\n"); |
Uwe Hermann | 20a98c9 | 2009-06-05 23:02:43 +0000 | [diff] [blame] | 809 | } |