Patrick Georgi | ea063cb | 2020-05-08 19:28:13 +0200 | [diff] [blame] | 1 | /* inteltool - dump all registers on an Intel CPU + chipset based system. */ |
Patrick Georgi | 7333a11 | 2020-05-08 20:48:04 +0200 | [diff] [blame] | 2 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 3 | |
| 4 | |
| 5 | #include <stdio.h> |
| 6 | #include <stdlib.h> |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 7 | #include <inttypes.h> |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 8 | #include "inteltool.h" |
| 9 | |
Vladimir Serbinenko | e4e8e09 | 2013-03-31 13:51:37 +0200 | [diff] [blame] | 10 | volatile uint8_t *mchbar; |
| 11 | |
| 12 | static void write_mchbar32 (uint32_t addr, uint32_t val) |
| 13 | { |
| 14 | * (volatile uint32_t *) (mchbar + addr) = val; |
| 15 | } |
| 16 | |
| 17 | static uint32_t read_mchbar32 (uint32_t addr) |
| 18 | { |
| 19 | return * (volatile uint32_t *) (mchbar + addr); |
| 20 | } |
| 21 | |
| 22 | static uint8_t read_mchbar8 (uint32_t addr) |
| 23 | { |
| 24 | return * (volatile uint8_t *) (mchbar + addr); |
| 25 | } |
| 26 | |
| 27 | static u16 read_500 (int channel, u16 addr, int split) |
| 28 | { |
| 29 | uint32_t val; |
| 30 | write_mchbar32 (0x500 + (channel << 10), 0); |
| 31 | while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000); |
| 32 | write_mchbar32 (0x500 + (channel << 10), 0x80000000 | (((read_mchbar8 (0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr)); |
| 33 | while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000); |
| 34 | val = read_mchbar32 (0x508 + (channel << 10)); |
| 35 | |
| 36 | return val & ((1 << split) - 1); |
| 37 | } |
| 38 | |
| 39 | static inline u16 get_lane_offset (int slot, int rank, int lane) |
| 40 | { |
| 41 | return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - 0x452 * (lane == 8); |
| 42 | } |
| 43 | |
| 44 | static inline u16 get_timing_register_addr (int lane, int tm, int slot, int rank) |
| 45 | { |
| 46 | const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c }; |
| 47 | return get_lane_offset (slot, rank, lane) + offs[(tm + 3) % 4]; |
| 48 | } |
| 49 | |
| 50 | static void write_1d0 (u32 val, u16 addr, int bits, int flag) |
| 51 | { |
| 52 | write_mchbar32 (0x1d0, 0); |
| 53 | while (read_mchbar32 (0x1d0) & 0x800000); |
| 54 | write_mchbar32 (0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits)); |
| 55 | write_mchbar32 (0x1d0, 0x40000000 | addr); |
| 56 | while (read_mchbar32 (0x1d0) & 0x800000); |
| 57 | } |
| 58 | |
| 59 | static u16 read_1d0 (u16 addr, int split) |
| 60 | { |
| 61 | u32 val; |
| 62 | write_mchbar32 (0x1d0, 0); |
| 63 | while (read_mchbar32 (0x1d0) & 0x800000); |
| 64 | write_mchbar32 (0x1d0, 0x80000000 | (((read_mchbar8 (0x246) >> 2) & 3) + 0x361 - addr)); |
| 65 | while (read_mchbar32 (0x1d0) & 0x800000); |
| 66 | val = read_mchbar32 (0x1d8); |
| 67 | write_1d0 (0, 0x33d, 0, 0); |
| 68 | write_1d0 (0, 0x33d, 0, 0); |
| 69 | return val & ((1 << split) - 1); |
| 70 | } |
| 71 | |
| 72 | static void dump_timings (void) |
| 73 | { |
| 74 | int channel, slot, rank, lane, i; |
| 75 | printf ("Timings:\n"); |
| 76 | for (channel = 0; channel < 2; channel++) |
| 77 | for (slot = 0; slot < 2; slot++) |
| 78 | for (rank = 0; rank < 2; rank++) { |
| 79 | printf ("channel %d, slot %d, rank %d\n", channel, slot, rank); |
| 80 | for (lane = 0; lane < 9; lane++) { |
| 81 | printf ("lane %d: ", lane); |
| 82 | for (i = 0; i < 4; i++) { |
| 83 | printf ("%x ", read_500 (channel, |
| 84 | get_timing_register_addr (lane, i, slot, rank), 9)); |
| 85 | } |
| 86 | printf ("\n"); |
| 87 | } |
| 88 | } |
| 89 | |
| 90 | printf ("[178] = %x\n", read_1d0 (0x178, 7)); |
| 91 | printf ("[10b] = %x\n", read_1d0 (0x10b, 6)); |
| 92 | } |
| 93 | |
| 94 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 95 | /* |
| 96 | * (G)MCH MMIO Config Space |
| 97 | */ |
Vladimir Serbinenko | fb69a69 | 2015-10-10 13:20:32 +0200 | [diff] [blame] | 98 | int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file) |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 99 | { |
| 100 | int i, size = (16 * 1024); |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 101 | uint64_t mchbar_phys; |
| 102 | struct pci_dev *nb_device6; /* "overflow device" on i865 */ |
| 103 | uint16_t pcicmd6; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 104 | |
| 105 | printf("\n============= MCHBAR ============\n\n"); |
| 106 | |
| 107 | switch (nb->device_id) { |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 108 | case PCI_DEVICE_ID_INTEL_82865: |
| 109 | /* |
| 110 | * On i865, the memory access enable/disable bit (MCHBAREN on |
| 111 | * i945/i965) is not in the MCHBAR (i945/i965) register but in |
| 112 | * the PCICMD6 register. BAR6 and PCICMD6 reside on device 6. |
| 113 | * |
| 114 | * The actual base address is in BAR6 on i865 where on |
| 115 | * i945/i965 the base address is in MCHBAR. |
| 116 | */ |
| 117 | nb_device6 = pci_get_dev(pacc, 0, 0, 0x06, 0); /* Device 6 */ |
| 118 | mchbar_phys = pci_read_long(nb_device6, 0x10); /* BAR6 */ |
| 119 | pcicmd6 = pci_read_long(nb_device6, 0x04); /* PCICMD6 */ |
| 120 | |
| 121 | /* Try to enable Memory Access Enable (MAE). */ |
| 122 | if (!(pcicmd6 & (1 << 1))) { |
| 123 | printf("Access to BAR6 is currently disabled, " |
| 124 | "attempting to enable.\n"); |
| 125 | pci_write_long(nb_device6, 0x04, pcicmd6 | (1 << 1)); |
| 126 | if (pci_read_long(nb_device6, 0x04) & (1 << 1)) |
| 127 | printf("Enabled successfully.\n"); |
| 128 | else |
| 129 | printf("Enable FAILED!\n"); |
| 130 | } |
| 131 | mchbar_phys &= 0xfffff000; /* Bits 31:12 from BAR6 */ |
| 132 | break; |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 133 | case PCI_DEVICE_ID_INTEL_82915: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 134 | case PCI_DEVICE_ID_INTEL_82945GM: |
Björn Busse | 2d33dc4 | 2010-08-01 15:33:30 +0000 | [diff] [blame] | 135 | case PCI_DEVICE_ID_INTEL_82945GSE: |
Stefan Reinauer | 3d9a12f | 2008-11-02 11:11:40 +0000 | [diff] [blame] | 136 | case PCI_DEVICE_ID_INTEL_82945P: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 137 | case PCI_DEVICE_ID_INTEL_82975X: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 138 | mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; |
| 139 | break; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 140 | case PCI_DEVICE_ID_INTEL_82965PM: |
| 141 | case PCI_DEVICE_ID_INTEL_82Q35: |
| 142 | case PCI_DEVICE_ID_INTEL_82G33: |
| 143 | case PCI_DEVICE_ID_INTEL_82Q33: |
| 144 | mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; |
| 145 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 146 | break; |
Stefan Tauner | 1a00cf0 | 2012-10-13 06:23:52 +0200 | [diff] [blame] | 147 | case PCI_DEVICE_ID_INTEL_82946: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 148 | case PCI_DEVICE_ID_INTEL_82Q965: |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 149 | case PCI_DEVICE_ID_INTEL_ATOM_DXXX: |
| 150 | case PCI_DEVICE_ID_INTEL_ATOM_NXXX: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 151 | mchbar_phys = pci_read_long(nb, 0x48); |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 152 | |
| 153 | /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 154 | * If it isn't, try to set it. This may fail, because there is |
| 155 | * some bit that locks that bit, and isn't in the public |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 156 | * datasheets. |
| 157 | */ |
| 158 | |
| 159 | if(!(mchbar_phys & 1)) |
| 160 | { |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 161 | printf("Access to the MCHBAR is currently disabled, " |
| 162 | "attempting to enable.\n"); |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 163 | mchbar_phys |= 0x1; |
| 164 | pci_write_long(nb, 0x48, mchbar_phys); |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 165 | if(pci_read_long(nb, 0x48) & 1) |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 166 | printf("Enabled successfully.\n"); |
| 167 | else |
| 168 | printf("Enable FAILED!\n"); |
| 169 | } |
| 170 | mchbar_phys &= 0xfffffffe; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 171 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 172 | break; |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 173 | case PCI_DEVICE_ID_INTEL_82443LX: |
| 174 | case PCI_DEVICE_ID_INTEL_82443BX: |
Stefan Reinauer | b2aedb1 | 2009-08-29 15:45:43 +0000 | [diff] [blame] | 175 | case PCI_DEVICE_ID_INTEL_82810: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 176 | case PCI_DEVICE_ID_INTEL_82810E_DC: |
| 177 | case PCI_DEVICE_ID_INTEL_82810_DC: |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 178 | case PCI_DEVICE_ID_INTEL_82830M: |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 179 | printf("This northbridge does not have MCHBAR.\n"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 180 | return 1; |
Damien Zammit | 9c98664 | 2015-08-17 21:04:41 +1000 | [diff] [blame] | 181 | case PCI_DEVICE_ID_INTEL_82XX4X: |
| 182 | case PCI_DEVICE_ID_INTEL_82Q45: |
| 183 | case PCI_DEVICE_ID_INTEL_82G45: |
| 184 | case PCI_DEVICE_ID_INTEL_82G41: |
| 185 | case PCI_DEVICE_ID_INTEL_82B43: |
| 186 | case PCI_DEVICE_ID_INTEL_82B43_2: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 187 | case PCI_DEVICE_ID_INTEL_82X38: |
Ruud Schramp | bb41f50 | 2011-04-04 07:53:19 +0200 | [diff] [blame] | 188 | case PCI_DEVICE_ID_INTEL_32X0: |
Anton Kochkov | da0b456 | 2010-05-30 12:33:12 +0000 | [diff] [blame] | 189 | mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; |
| 190 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 191 | break; |
| 192 | case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: |
| 193 | mchbar_phys = pci_read_long(nb, 0x48); |
| 194 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 195 | mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */ |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 196 | break; |
Felix Held | 0cc8f29 | 2014-11-05 03:18:44 +0100 | [diff] [blame] | 197 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: |
| 198 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 199 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: |
Damien Zammit | 601da48 | 2014-05-26 23:00:23 +1000 | [diff] [blame] | 200 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 201 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: |
| 202 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: |
| 203 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: |
| 204 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: |
| 205 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: |
| 206 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 207 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: |
Matt DeVillier | 5b667df | 2015-05-14 21:58:33 -0500 | [diff] [blame] | 208 | case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: |
Nico Huber | 54fe32f | 2017-10-03 16:03:07 +0200 | [diff] [blame] | 209 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: |
Benjamin Doron | c01fa5a | 2020-07-01 19:20:40 +0000 | [diff] [blame] | 210 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: |
| 211 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: |
| 212 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: |
Nico Huber | 21e7424 | 2017-04-24 15:06:09 +0200 | [diff] [blame] | 213 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: |
Christoph Pomaska | 48ac29e | 2018-01-01 01:48:21 +0100 | [diff] [blame] | 214 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: |
Maxim Polyakov | 1317689 | 2019-08-27 18:20:08 +0300 | [diff] [blame] | 215 | case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: |
Matthew Garrett | 2bf28e5 | 2018-07-23 21:09:47 -0700 | [diff] [blame] | 216 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: |
| 217 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: |
| 218 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: |
Christian Walter | 9a8c5e7 | 2019-05-06 17:50:57 +0200 | [diff] [blame] | 219 | case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3: |
Matt DeVillier | 3c78445 | 2019-06-11 23:23:46 -0500 | [diff] [blame] | 220 | case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_1: |
| 221 | case PCI_DEVICE_ID_INTEL_CORE_8TH_GEN_U_2: |
Matt DeVillier | 62e883d | 2020-08-08 11:17:31 -0500 | [diff] [blame] | 222 | case PCI_DEVICE_ID_INTEL_CORE_CML_U1: |
| 223 | case PCI_DEVICE_ID_INTEL_CORE_CML_U2: |
| 224 | case PCI_DEVICE_ID_INTEL_CORE_CML_U3: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 225 | mchbar_phys = pci_read_long(nb, 0x48); |
| 226 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 227 | mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ |
Vladimir Serbinenko | 44bc11c | 2014-08-16 19:14:02 +0200 | [diff] [blame] | 228 | size = 32768; |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 229 | break; |
Johanna Schander | 4ddbbd8 | 2020-01-06 08:52:49 +0100 | [diff] [blame] | 230 | case PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U: |
| 231 | mchbar_phys = pci_read_long(nb, 0x48); |
| 232 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 233 | mchbar_phys &= 0x0000007fffff0000UL; /* 38:16 */ |
| 234 | size = 32768; |
| 235 | break; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 236 | default: |
| 237 | printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); |
| 238 | return 1; |
| 239 | } |
| 240 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 241 | mchbar = map_physical(mchbar_phys, size); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 242 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 243 | if (mchbar == NULL) { |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 244 | if (nb->device_id == PCI_DEVICE_ID_INTEL_82865) |
| 245 | perror("Error mapping BAR6"); |
| 246 | else |
| 247 | perror("Error mapping MCHBAR"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 248 | exit(1); |
| 249 | } |
| 250 | |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 251 | if (nb->device_id == PCI_DEVICE_ID_INTEL_82865) |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 252 | printf("BAR6 = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 253 | else |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 254 | printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 255 | |
Vladimir Serbinenko | 9c4f1b8 | 2014-11-04 21:05:12 +0100 | [diff] [blame] | 256 | for (i = 0; i < size; i += 4) { |
Michael Niewöhner | 10d5221 | 2020-03-13 19:08:21 +0100 | [diff] [blame] | 257 | if (read32(mchbar + i)) |
| 258 | printf("0x%04x: 0x%08"PRIx32"\n", i, read32(mchbar+i)); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 259 | } |
| 260 | |
Vladimir Serbinenko | 44bc11c | 2014-08-16 19:14:02 +0200 | [diff] [blame] | 261 | switch (nb->device_id) |
| 262 | { |
| 263 | case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: |
Vladimir Serbinenko | e4e8e09 | 2013-03-31 13:51:37 +0200 | [diff] [blame] | 264 | printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1); |
| 265 | dump_timings (); |
Stefan Tauner | 572f074 | 2016-05-05 17:29:39 +0200 | [diff] [blame] | 266 | if (dump_spd_file != NULL) |
| 267 | printf("\nCreating a memory timings file is not supported on this chipset.\n"); |
Vladimir Serbinenko | 44bc11c | 2014-08-16 19:14:02 +0200 | [diff] [blame] | 268 | break; |
Felix Held | 0cc8f29 | 2014-11-05 03:18:44 +0100 | [diff] [blame] | 269 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: |
| 270 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: |
Felix Held | fac95e3 | 2014-11-09 00:11:28 +0100 | [diff] [blame] | 271 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3: |
| 272 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: |
| 273 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M: |
| 274 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3: |
| 275 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c: |
Vladimir Serbinenko | fb69a69 | 2015-10-10 13:20:32 +0200 | [diff] [blame] | 276 | ivybridge_dump_timings(dump_spd_file); |
Vladimir Serbinenko | 44bc11c | 2014-08-16 19:14:02 +0200 | [diff] [blame] | 277 | break; |
Stefan Tauner | 572f074 | 2016-05-05 17:29:39 +0200 | [diff] [blame] | 278 | default: |
| 279 | if (dump_spd_file != NULL) |
| 280 | printf("\nCreating a memory timings file is not supported on this chipset.\n"); |
Vladimir Serbinenko | e4e8e09 | 2013-03-31 13:51:37 +0200 | [diff] [blame] | 281 | } |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 282 | unmap_physical((void *)mchbar, size); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 283 | return 0; |
| 284 | } |