inteltool: add more hardware IDs and PCIEXBAR/PXPEPBAR read support
Add IDs of some SNB and Haswell chips; use more descriptive names.
Add PCIEXBAR and PXPEPBAR read support for SNB/IVB/Haswell.
Change-Id: I16753bf90061fc2065b813b1c2169e7b7bcc89e8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/7360
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index e2b0ab4..3aa3e4f 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -207,10 +207,14 @@
break;
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
- case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */
- case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
- case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
+ case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
+ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D:
+ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
+ case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
@@ -248,12 +252,13 @@
printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
dump_timings ();
break;
- case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A:
- case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B:
- case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C:
- case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
+ case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3:
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D:
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M:
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3:
+ case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
ivybridge_dump_timings();
break;
}