Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 2 | |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame] | 3 | #include <Porting.h> |
| 4 | #include <AGESA.h> |
Kyösti Mälkki | 2446c1e | 2020-07-09 07:13:37 +0300 | [diff] [blame] | 5 | #include <amdblocks/biosram.h> |
Kyösti Mälkki | 64df52e | 2017-09-01 06:13:08 +0300 | [diff] [blame] | 6 | #include <arch/io.h> |
Nico Huber | 3e1b3b1 | 2018-10-07 12:45:47 +0200 | [diff] [blame] | 7 | #include <cf9_reset.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 8 | #include <console/console.h> |
Kyösti Mälkki | 64df52e | 2017-09-01 06:13:08 +0300 | [diff] [blame] | 9 | #include <device/device.h> |
| 10 | #include <device/pci_def.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 11 | #include <device/pci_ops.h> |
Kyösti Mälkki | 64df52e | 2017-09-01 06:13:08 +0300 | [diff] [blame] | 12 | #include <smp/node.h> |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 13 | #include <northbridge/amd/agesa/state_machine.h> |
| 14 | #include <northbridge/amd/agesa/agesa_helper.h> |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 15 | #include <sb_cimx.h> |
| 16 | |
| 17 | void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) |
| 18 | { |
Kyösti Mälkki | 3d5e1e5 | 2019-12-03 14:06:02 +0200 | [diff] [blame] | 19 | if (!boot_cpu()) |
| 20 | return; |
| 21 | |
Kyösti Mälkki | 520717d | 2019-12-15 21:37:48 +0200 | [diff] [blame] | 22 | sb_Poweron_Init(); |
Kyösti Mälkki | 3d5e1e5 | 2019-12-03 14:06:02 +0200 | [diff] [blame] | 23 | |
Kyösti Mälkki | 64df52e | 2017-09-01 06:13:08 +0300 | [diff] [blame] | 24 | /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all |
| 25 | * would fail later in AmdInitPost(), when DRAM is already configured |
| 26 | * and C6DramLock bit has been set. |
| 27 | * |
| 28 | * As a workaround, do a hard reset to clear C6DramLock bit. |
| 29 | */ |
Kyösti Mälkki | 3d5e1e5 | 2019-12-03 14:06:02 +0200 | [diff] [blame] | 30 | |
Kyösti Mälkki | 64df52e | 2017-09-01 06:13:08 +0300 | [diff] [blame] | 31 | #ifdef __SIMPLE_DEVICE__ |
| 32 | pci_devfn_t dev = PCI_DEV(0, 0x18, 2); |
| 33 | #else |
Kyösti Mälkki | 4ad7f5b | 2018-05-22 01:15:17 +0300 | [diff] [blame] | 34 | struct device *dev = pcidev_on_root(0x18, 2); |
Kyösti Mälkki | 64df52e | 2017-09-01 06:13:08 +0300 | [diff] [blame] | 35 | #endif |
Kyösti Mälkki | 3d5e1e5 | 2019-12-03 14:06:02 +0200 | [diff] [blame] | 36 | u32 mct_cfg_lo = pci_read_config32(dev, 0x118); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 37 | if (mct_cfg_lo & (1 << 19)) { |
Kyösti Mälkki | 3d5e1e5 | 2019-12-03 14:06:02 +0200 | [diff] [blame] | 38 | printk(BIOS_CRIT, "C6DramLock is set, resetting\n"); |
| 39 | system_reset(); |
Kyösti Mälkki | 64df52e | 2017-09-01 06:13:08 +0300 | [diff] [blame] | 40 | } |
Kyösti Mälkki | 3d5e1e5 | 2019-12-03 14:06:02 +0200 | [diff] [blame] | 41 | |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 42 | } |
| 43 | |
| 44 | void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) |
| 45 | { |
| 46 | } |
| 47 | |
| 48 | void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |
| 49 | { |
Mike Banon | e7f176c | 2020-01-19 21:42:09 +0300 | [diff] [blame] | 50 | Post->MemConfig.BottomIo = (UINT16)(MIN(0xE0000000, |
| 51 | MAX(0x28000000, CONFIG_BOTTOMIO_POSITION)) >> 24) & 0xF8; |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |
| 55 | { |
| 56 | backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); |
| 57 | } |
| 58 | |
| 59 | void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) |
| 60 | { |
| 61 | OemInitResume(&Resume->S3DataBlock); |
| 62 | } |
| 63 | |
| 64 | void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) |
| 65 | { |
| 66 | } |
| 67 | |
| 68 | void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) |
| 69 | { |
| 70 | EmptyHeap(); |
| 71 | } |
| 72 | |
| 73 | void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) |
| 74 | { |
| 75 | amd_initenv(); |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) |
| 79 | { |
| 80 | OemS3LateRestore(&S3Late->S3DataBlock); |
| 81 | } |
| 82 | |
| 83 | void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) |
| 84 | { |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) |
| 88 | { |
| 89 | sb_After_Pci_Init(); |
| 90 | sb_Mid_Post_Init(); |
| 91 | |
| 92 | amd_initcpuio(); |
| 93 | } |
| 94 | |
Michał Żygowski | 506b9c1 | 2019-12-20 16:57:13 +0100 | [diff] [blame] | 95 | void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) |
| 96 | { |
| 97 | } |
| 98 | |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 99 | void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) |
| 100 | { |
| 101 | sb_Late_Post(); |
| 102 | } |
| 103 | |
| 104 | void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) |
| 105 | { |
| 106 | OemS3Save(&S3Save->S3DataBlock); |
| 107 | } |