Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Kyösti Mälkki |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include "Porting.h" |
| 17 | #include "AGESA.h" |
| 18 | |
Kyösti Mälkki | 64df52e | 2017-09-01 06:13:08 +0300 | [diff] [blame] | 19 | #include <arch/io.h> |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 20 | #include <cbmem.h> |
Kyösti Mälkki | 64df52e | 2017-09-01 06:13:08 +0300 | [diff] [blame] | 21 | #include <device/device.h> |
| 22 | #include <device/pci_def.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame^] | 23 | #include <device/pci_ops.h> |
Kyösti Mälkki | 64df52e | 2017-09-01 06:13:08 +0300 | [diff] [blame] | 24 | #include <halt.h> |
| 25 | #include <reset.h> |
| 26 | #include <smp/node.h> |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 27 | #include <northbridge/amd/agesa/state_machine.h> |
| 28 | #include <northbridge/amd/agesa/agesa_helper.h> |
| 29 | |
| 30 | #include <sb_cimx.h> |
| 31 | |
| 32 | void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) |
| 33 | { |
Kyösti Mälkki | 64df52e | 2017-09-01 06:13:08 +0300 | [diff] [blame] | 34 | /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all |
| 35 | * would fail later in AmdInitPost(), when DRAM is already configured |
| 36 | * and C6DramLock bit has been set. |
| 37 | * |
| 38 | * As a workaround, do a hard reset to clear C6DramLock bit. |
| 39 | */ |
| 40 | #ifdef __SIMPLE_DEVICE__ |
| 41 | pci_devfn_t dev = PCI_DEV(0, 0x18, 2); |
| 42 | #else |
| 43 | struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); |
| 44 | #endif |
| 45 | if (boot_cpu()) { |
| 46 | u32 mct_cfg_lo = pci_read_config32(dev, 0x118); |
| 47 | if (mct_cfg_lo & (1<<19)) { |
| 48 | printk(BIOS_CRIT, "C6DramLock is set, resetting\n"); |
| 49 | hard_reset(); |
| 50 | } |
| 51 | } |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) |
| 55 | { |
| 56 | } |
| 57 | |
| 58 | void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |
| 59 | { |
| 60 | } |
| 61 | |
| 62 | void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |
| 63 | { |
| 64 | backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); |
| 65 | } |
| 66 | |
| 67 | void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) |
| 68 | { |
| 69 | OemInitResume(&Resume->S3DataBlock); |
| 70 | } |
| 71 | |
| 72 | void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) |
| 73 | { |
| 74 | } |
| 75 | |
| 76 | void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) |
| 77 | { |
| 78 | EmptyHeap(); |
| 79 | } |
| 80 | |
| 81 | void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) |
| 82 | { |
| 83 | amd_initenv(); |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) |
| 87 | { |
| 88 | OemS3LateRestore(&S3Late->S3DataBlock); |
| 89 | } |
| 90 | |
| 91 | void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) |
| 92 | { |
Kyösti Mälkki | 28c4d2f | 2016-11-25 11:21:02 +0200 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) |
| 96 | { |
| 97 | sb_After_Pci_Init(); |
| 98 | sb_Mid_Post_Init(); |
| 99 | |
| 100 | amd_initcpuio(); |
| 101 | } |
| 102 | |
| 103 | void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) |
| 104 | { |
| 105 | sb_Late_Post(); |
| 106 | } |
| 107 | |
| 108 | void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) |
| 109 | { |
| 110 | OemS3Save(&S3Save->S3DataBlock); |
| 111 | } |