blob: 1659834604ca75ca08ae174247c02081a02d285d [file] [log] [blame]
Nico Huber0ccfa682017-04-20 15:36:46 +02001# SPDX-License-Identifier: GPL-2.0-only
2
3chip soc/intel/skylake
4
Nico Huber0ccfa682017-04-20 15:36:46 +02005 register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS"
6 register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S"
7 register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S"
8 register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
Nico Huber0ccfa682017-04-20 15:36:46 +02009 register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S"
10
11 # VR Settings Configuration for 2 Domains
12 #+----------------+-------+-------+
13 #| Domain/Setting | VCC | VCCGT |
14 #+----------------+-------+-------+
15 #| Psi1Threshold | 20A | 20A |
16 #| Psi2Threshold | 5A | 5A |
17 #| Psi3Threshold | 1A | 1A |
18 #| Psi3Enable | 1 | 1 |
19 #| Psi4Enable | 1 | 1 |
20 #| ImonSlope | 0 | 0 |
21 #| ImonOffset | 0 | 0 |
22 #| IccMax | 55A | 35A |
23 #| VrVoltageLimit | 1.52V | 1.52V |
24 #| AcLoadline | 2.1 | 3.1 |
25 #| DcLoadline | 2.1 | 3.1 |
26 #+----------------+-------+-------+
27 register "domain_vr_config[VR_IA_CORE]" = "{
28 .vr_config_enable = 1,
29 .psi1threshold = VR_CFG_AMP(20),
30 .psi2threshold = VR_CFG_AMP(5),
31 .psi3threshold = VR_CFG_AMP(1),
32 .psi3enable = 1,
33 .psi4enable = 1,
34 .imon_slope = 0x0,
35 .imon_offset = 0x0,
36 .icc_max = VR_CFG_AMP(55),
37 .voltage_limit = 1520,
38 .ac_loadline = 210,
39 .dc_loadline = 210,
40 }"
41
42 register "domain_vr_config[VR_GT_UNSLICED]" = "{
43 .vr_config_enable = 1,
44 .psi1threshold = VR_CFG_AMP(20),
45 .psi2threshold = VR_CFG_AMP(5),
46 .psi3threshold = VR_CFG_AMP(1),
47 .psi3enable = 1,
48 .psi4enable = 1,
49 .imon_slope = 0x0,
50 .imon_offset = 0x0,
51 .icc_max = VR_CFG_AMP(35),
52 .voltage_limit = 1520,
53 .ac_loadline = 310,
54 .dc_loadline = 310,
55 }"
56
57 # Vendor set Psys Pmax to 30W
58 register "power_limits_config" = "{
59 .psys_pmax = 30,
60 }"
61
62 # TODO
63 # Send an extra VR mailbox command for the PS4 exit issue
64 register "SendVrMbxCmd" = "2"
65
Arthur Heymans69cd7292022-11-07 13:52:11 +010066 device cpu_cluster 0 on end
Nico Huber0ccfa682017-04-20 15:36:46 +020067
68 device domain 0 on
69 device pci 00.0 on end # Host Bridge
70 device pci 02.0 on end # Integrated Graphics Device
71 device pci 08.0 on end # Gaussian Mixture Model
72 device pci 14.0 on # USB xHCI
Felix Singereb1a2bd2023-10-23 08:30:02 +020073 register "usb2_ports" = "{
74 [0] = USB2_PORT_LONG(OC0),
75 [1] = USB2_PORT_LONG(OC0),
76 [2] = USB2_PORT_LONG(OC1),
77 [3] = USB2_PORT_LONG(OC1),
78 [4] = USB2_PORT_LONG(OC2), /* Debug */
79 }"
Nico Huber0ccfa682017-04-20 15:36:46 +020080 end
Nico Huber0ccfa682017-04-20 15:36:46 +020081 device pci 14.2 on end # Thermal Subsystem
Nico Huber0ccfa682017-04-20 15:36:46 +020082 device pci 16.0 on end # Management Engine Interface 1
Nico Huber0ccfa682017-04-20 15:36:46 +020083 device pci 17.0 on # SATA
Felix Singereb1a2bd2023-10-23 08:30:02 +020084 register "SataSalpSupport" = "1"
85 register "SataPortsEnable" = "{
86 [0] = 1,
87 [1] = 1,
88 [2] = 1,
89 }"
Nico Huber0ccfa682017-04-20 15:36:46 +020090 end
Nico Huber0ccfa682017-04-20 15:36:46 +020091 device pci 1d.0 on # PCI Express Port 9 (COMe 0)
92 register "PcieRpEnable[8]" = "1"
93 end
94 device pci 1d.1 on # PCI Express Port 10 (COMe 1)
95 register "PcieRpEnable[9]" = "1"
96 end
97 device pci 1d.2 on # PCI Express Port 11 (COMe 2)
98 register "PcieRpEnable[10]" = "1"
99 end
Nico Huber0ccfa682017-04-20 15:36:46 +0200100 device pci 1f.0 on # LPC Interface
101 register "serirq_mode" = "SERIRQ_CONTINUOUS"
102
103 # EC/kempld at 0xa80/0xa81
104 register "gen1_dec" = "0x00000a81"
105
106 chip drivers/pc80/tpm
107 device pnp 0c31.0 on end
108 end
109 chip ec/kontron/kempld
110 register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }"
111 device generic 0.0 on end # UART #0
112 end
113 end
114 device pci 1f.1 on end # P2SB
115 device pci 1f.2 on end # Power Management Controller
Nico Huber0ccfa682017-04-20 15:36:46 +0200116 device pci 1f.4 on # SMBus
117 chip drivers/i2c/nct7802y
118 device i2c 0x2e on end
119 end
120 end
121 device pci 1f.5 on end # PCH SPI
122 device pci 1f.6 on end # GbE
123 end
124end