Nico Huber | 0ccfa68 | 2017-04-20 15:36:46 +0200 | [diff] [blame^] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | chip soc/intel/skylake |
| 4 | |
| 5 | register "speed_shift_enable" = "1" |
| 6 | |
| 7 | register "common_soc_config" = "{ |
| 8 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 9 | }" |
| 10 | |
| 11 | register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" |
| 12 | register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" |
| 13 | register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" |
| 14 | register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" |
| 15 | register "PmConfigPciClockRun" = "1" |
| 16 | register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" |
| 17 | |
| 18 | # VR Settings Configuration for 2 Domains |
| 19 | #+----------------+-------+-------+ |
| 20 | #| Domain/Setting | VCC | VCCGT | |
| 21 | #+----------------+-------+-------+ |
| 22 | #| Psi1Threshold | 20A | 20A | |
| 23 | #| Psi2Threshold | 5A | 5A | |
| 24 | #| Psi3Threshold | 1A | 1A | |
| 25 | #| Psi3Enable | 1 | 1 | |
| 26 | #| Psi4Enable | 1 | 1 | |
| 27 | #| ImonSlope | 0 | 0 | |
| 28 | #| ImonOffset | 0 | 0 | |
| 29 | #| IccMax | 55A | 35A | |
| 30 | #| VrVoltageLimit | 1.52V | 1.52V | |
| 31 | #| AcLoadline | 2.1 | 3.1 | |
| 32 | #| DcLoadline | 2.1 | 3.1 | |
| 33 | #+----------------+-------+-------+ |
| 34 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 35 | .vr_config_enable = 1, |
| 36 | .psi1threshold = VR_CFG_AMP(20), |
| 37 | .psi2threshold = VR_CFG_AMP(5), |
| 38 | .psi3threshold = VR_CFG_AMP(1), |
| 39 | .psi3enable = 1, |
| 40 | .psi4enable = 1, |
| 41 | .imon_slope = 0x0, |
| 42 | .imon_offset = 0x0, |
| 43 | .icc_max = VR_CFG_AMP(55), |
| 44 | .voltage_limit = 1520, |
| 45 | .ac_loadline = 210, |
| 46 | .dc_loadline = 210, |
| 47 | }" |
| 48 | |
| 49 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 50 | .vr_config_enable = 1, |
| 51 | .psi1threshold = VR_CFG_AMP(20), |
| 52 | .psi2threshold = VR_CFG_AMP(5), |
| 53 | .psi3threshold = VR_CFG_AMP(1), |
| 54 | .psi3enable = 1, |
| 55 | .psi4enable = 1, |
| 56 | .imon_slope = 0x0, |
| 57 | .imon_offset = 0x0, |
| 58 | .icc_max = VR_CFG_AMP(35), |
| 59 | .voltage_limit = 1520, |
| 60 | .ac_loadline = 310, |
| 61 | .dc_loadline = 310, |
| 62 | }" |
| 63 | |
| 64 | # Vendor set Psys Pmax to 30W |
| 65 | register "power_limits_config" = "{ |
| 66 | .psys_pmax = 30, |
| 67 | }" |
| 68 | |
| 69 | # TODO |
| 70 | # Send an extra VR mailbox command for the PS4 exit issue |
| 71 | register "SendVrMbxCmd" = "2" |
| 72 | |
| 73 | device cpu_cluster 0 on |
| 74 | device lapic 0 on end |
| 75 | end |
| 76 | |
| 77 | device domain 0 on |
| 78 | device pci 00.0 on end # Host Bridge |
| 79 | device pci 02.0 on end # Integrated Graphics Device |
| 80 | device pci 08.0 on end # Gaussian Mixture Model |
| 81 | device pci 14.0 on # USB xHCI |
| 82 | register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" |
| 83 | register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" |
| 84 | register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" |
| 85 | register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" |
| 86 | register "usb2_ports[4]" = "USB2_PORT_LONG(OC2)" # Debug |
| 87 | end |
| 88 | device pci 14.1 off end # USB xDCI (OTG) |
| 89 | device pci 14.2 on end # Thermal Subsystem |
| 90 | device pci 15.0 off end # I2C #0 |
| 91 | device pci 15.1 off end # I2C #1 |
| 92 | device pci 15.2 off end # I2C #2 |
| 93 | device pci 15.3 off end # I2C #3 |
| 94 | device pci 16.0 on end # Management Engine Interface 1 |
| 95 | device pci 16.1 off end # Management Engine Interface 2 |
| 96 | device pci 16.2 off end # Management Engine IDE-R |
| 97 | device pci 16.3 off end # Management Engine KT Redirection |
| 98 | device pci 16.4 off end # Management Engine Interface 3 |
| 99 | device pci 17.0 on # SATA |
| 100 | register "SataMode" = "KBLFSP_SATA_MODE_AHCI" |
| 101 | register "SataSalpSupport" = "1" |
| 102 | register "SataPortsEnable[0]" = "1" |
| 103 | register "SataPortsEnable[1]" = "1" |
| 104 | register "SataPortsEnable[2]" = "1" |
| 105 | # SataPortsDevSlp not supported |
| 106 | end |
| 107 | device pci 19.0 off end # UART #2 |
| 108 | device pci 1c.4 off end # PCI Express Port 5 |
| 109 | device pci 1c.5 off end # PCI Express Port 6 |
| 110 | device pci 1c.6 off end # PCI Express Port 7 |
| 111 | device pci 1c.7 off end # PCI Express Port 8 |
| 112 | device pci 1d.0 on # PCI Express Port 9 (COMe 0) |
| 113 | register "PcieRpEnable[8]" = "1" |
| 114 | end |
| 115 | device pci 1d.1 on # PCI Express Port 10 (COMe 1) |
| 116 | register "PcieRpEnable[9]" = "1" |
| 117 | end |
| 118 | device pci 1d.2 on # PCI Express Port 11 (COMe 2) |
| 119 | register "PcieRpEnable[10]" = "1" |
| 120 | end |
| 121 | device pci 1e.0 off end # UART #0 |
| 122 | device pci 1e.1 off end # UART #1 |
| 123 | device pci 1e.2 off end # GSPI #0 |
| 124 | device pci 1e.3 off end # GSPI #1 |
| 125 | device pci 1f.0 on # LPC Interface |
| 126 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 127 | |
| 128 | # EC/kempld at 0xa80/0xa81 |
| 129 | register "gen1_dec" = "0x00000a81" |
| 130 | |
| 131 | chip drivers/pc80/tpm |
| 132 | device pnp 0c31.0 on end |
| 133 | end |
| 134 | chip ec/kontron/kempld |
| 135 | register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }" |
| 136 | device generic 0.0 on end # UART #0 |
| 137 | end |
| 138 | end |
| 139 | device pci 1f.1 on end # P2SB |
| 140 | device pci 1f.2 on end # Power Management Controller |
| 141 | device pci 1f.3 off end # Intel HDA |
| 142 | device pci 1f.4 on # SMBus |
| 143 | chip drivers/i2c/nct7802y |
| 144 | device i2c 0x2e on end |
| 145 | end |
| 146 | end |
| 147 | device pci 1f.5 on end # PCH SPI |
| 148 | device pci 1f.6 on end # GbE |
| 149 | end |
| 150 | end |