blob: 54441612fabfa8dc32c685317e96188df3ea35f6 [file] [log] [blame]
Anton Kochkov7c634ae2011-06-20 23:14:22 +04001/*
2 * This file is part of msrtool.
3 *
4 * Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Anton Kochkov7c634ae2011-06-20 23:14:22 +040014 */
15
16#include "msrtool.h"
17
Anton Kochkov59b36f12012-07-21 07:29:48 +040018int intel_pentium4_later_probe(const struct targetdef *target, const struct cpuid_t *id) {
Lubomir Rintel199a23c2017-01-22 22:19:24 +010019 return ((VENDOR_INTEL == id->vendor) &&
20 (0xf == id->family) && (
Anton Kochkovffbbecc2012-07-04 07:31:37 +040021 (0x3 == id->model) ||
22 (0x4 == id->model)
23 ));
Anton Kochkov7c634ae2011-06-20 23:14:22 +040024}
25
26const struct msrdef intel_pentium4_later_msrs[] = {
27 {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
28 { BITS_EOT }
29 }},
30 {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
31 { BITS_EOT }
32 }},
33 {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_LINE_SIZE", "", {
34 { BITS_EOT }
35 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +020036 {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
37 { BITS_EOT }
38 }},
Anton Kochkov7c634ae2011-06-20 23:14:22 +040039 {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
40 { BITS_EOT }
41 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +020042 {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
43 { BITS_EOT }
44 }},
Anton Kochkov7c634ae2011-06-20 23:14:22 +040045 {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_HARD_POWERON", "", {
46 { BITS_EOT }
47 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +020048 {0x2b, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_SOFT_POWERON", "", {
Anton Kochkov7c634ae2011-06-20 23:14:22 +040049 { BITS_EOT }
50 }},
51 {0x2c, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_FREQUENCY_ID", "", {
52 { BITS_EOT }
53 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +020054 {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
55 { BITS_EOT }
56 }},
57 {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", "", {
58 { BITS_EOT }
59 }},
60 {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
61 { BITS_EOT }
62 }},
63 {0x9b, MSRTYPE_RDWR, MSR2(0,0), "IA32_SMM_MONITOR_CTL", "", {
64 { BITS_EOT }
65 }},
66 {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
67 { BITS_EOT }
68 }},
69 {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
70 { BITS_EOT }
71 }},
72 {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
73 { BITS_EOT }
74 }},
75 {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
76 { BITS_EOT }
77 }},
78 {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
79 { BITS_EOT }
80 }},
81 {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
82 { BITS_EOT }
83 }},
84 {0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", {
85 { BITS_EOT }
86 }},
87 {0x180, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RAX", "", {
88 { BITS_EOT }
89 }},
90 {0x181, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBX", "", {
91 { BITS_EOT }
92 }},
93 {0x182, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RCX", "", {
94 { BITS_EOT }
95 }},
96 {0x183, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDX", "", {
97 { BITS_EOT }
98 }},
99 {0x184, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSI", "", {
100 { BITS_EOT }
101 }},
102 {0x185, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDI", "", {
103 { BITS_EOT }
104 }},
105 {0x186, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBP", "", {
106 { BITS_EOT }
107 }},
108 {0x187, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSP", "", {
109 { BITS_EOT }
110 }},
111 {0x188, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RFLAGS", "", {
112 { BITS_EOT }
113 }},
114 {0x189, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RIP", "", {
115 { BITS_EOT }
116 }},
117 {0x18a, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_MISC", "", {
118 { BITS_EOT }
119 }},
120 {0x18b, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RESERVED1", "", {
121 { BITS_EOT }
122 }},
123 {0x18c, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RESERVED2", "", {
124 { BITS_EOT }
125 }},
126 {0x18d, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RESERVED3", "", {
127 { BITS_EOT }
128 }},
129 {0x18e, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RESERVED4", "", {
130 { BITS_EOT }
131 }},
132 {0x18f, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RESERVED5", "", {
133 { BITS_EOT }
134 }},
135 {0x190, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R8", "", {
136 { BITS_EOT }
137 }},
138 {0x191, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R9", "", {
139 { BITS_EOT }
140 }},
141 {0x192, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R10", "", {
142 { BITS_EOT }
143 }},
144 {0x193, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R11", "", {
145 { BITS_EOT }
146 }},
147 {0x194, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R12", "", {
148 { BITS_EOT }
149 }},
150 {0x195, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R13", "", {
151 { BITS_EOT }
152 }},
153 {0x196, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R14", "", {
154 { BITS_EOT }
155 }},
156 {0x197, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R15", "", {
157 { BITS_EOT }
158 }},
159 {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
160 { BITS_EOT }
161 }},
162 {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", {
163 { BITS_EOT }
164 }},
165 {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
166 { BITS_EOT }
167 }},
168 {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
169 { BITS_EOT }
170 }},
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400171 {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
172 { BITS_EOT }
173 }},
174 {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", {
175 { BITS_EOT }
176 }},
177 {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
178 { BITS_EOT }
179 }},
180 {0x1a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PLATFORM_BRV", "", {
181 { BITS_EOT }
182 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200183 {0x1d7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", {
184 { BITS_EOT }
185 }},
186 {0x1d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", {
187 { BITS_EOT }
188 }},
189 {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DEBUGCTLA", "", {
190 { BITS_EOT }
191 }},
192 {0x1da, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH", "", {
193 { BITS_EOT }
194 }},
195 {0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0", "", {
196 { BITS_EOT }
197 }},
198 {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2", "", {
199 { BITS_EOT }
200 }},
201 {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3", "", {
202 { BITS_EOT }
203 }},
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400204 {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
205 { BITS_EOT }
206 }},
207 {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
208 { BITS_EOT }
209 }},
210 {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
211 { BITS_EOT }
212 }},
213 {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
214 { BITS_EOT }
215 }},
216 {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
217 { BITS_EOT }
218 }},
219 {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
220 { BITS_EOT }
221 }},
222 {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
223 { BITS_EOT }
224 }},
225 {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
226 { BITS_EOT }
227 }},
228 {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
229 { BITS_EOT }
230 }},
231 {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
232 { BITS_EOT }
233 }},
234 {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
235 { BITS_EOT }
236 }},
237 {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
238 { BITS_EOT }
239 }},
240 {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
241 { BITS_EOT }
242 }},
243 {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
244 { BITS_EOT }
245 }},
246 {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
247 { BITS_EOT }
248 }},
249 {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
250 { BITS_EOT }
251 }},
252 {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
253 { BITS_EOT }
254 }},
255 {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
256 { BITS_EOT }
257 }},
258 {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
259 { BITS_EOT }
260 }},
261 {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
262 { BITS_EOT }
263 }},
264 {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
265 { BITS_EOT }
266 }},
267 {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
268 { BITS_EOT }
269 }},
270 {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
271 { BITS_EOT }
272 }},
273 {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
274 { BITS_EOT }
275 }},
276 {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
277 { BITS_EOT }
278 }},
279 {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
280 { BITS_EOT }
281 }},
282 {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
283 { BITS_EOT }
284 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200285 {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", {
286 { BITS_EOT }
287 }},
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400288 {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
289 { BITS_EOT }
290 }},
291 {0x300, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER0", "", {
292 { BITS_EOT }
293 }},
294 {0x301, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER1", "", {
295 { BITS_EOT }
296 }},
297 {0x302, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER2", "", {
298 { BITS_EOT }
299 }},
300 {0x303, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER3", "", {
301 { BITS_EOT }
302 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200303 {0x304, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER0", "", {
304 { BITS_EOT }
305 }},
306 {0x305, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER1", "", {
307 { BITS_EOT }
308 }},
309 {0x306, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER2", "", {
310 { BITS_EOT }
311 }},
312 {0x307, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER3", "", {
313 { BITS_EOT }
314 }},
315 {0x308, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER0", "", {
316 { BITS_EOT }
317 }},
318 {0x309, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER1", "", {
319 { BITS_EOT }
320 }},
321 {0x30a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER2", "", {
322 { BITS_EOT }
323 }},
324 {0x30b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER3", "", {
325 { BITS_EOT }
326 }},
327 {0x30c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER0", "", {
328 { BITS_EOT }
329 }},
330 {0x30d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER1", "", {
331 { BITS_EOT }
332 }},
333 {0x30e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER2", "", {
334 { BITS_EOT }
335 }},
336 {0x30f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER3", "", {
337 { BITS_EOT }
338 }},
339 {0x310, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER4", "", {
340 { BITS_EOT }
341 }},
342 {0x311, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER5", "", {
343 { BITS_EOT }
344 }},
345 {0x360, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR0", "", {
346 { BITS_EOT }
347 }},
348 {0x361, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR1", "", {
349 { BITS_EOT }
350 }},
351 {0x362, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR2", "", {
352 { BITS_EOT }
353 }},
354 {0x363, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR3", "", {
355 { BITS_EOT }
356 }},
357 {0x364, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR0", "", {
358 { BITS_EOT }
359 }},
360 {0x365, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR1", "", {
361 { BITS_EOT }
362 }},
363 {0x366, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR2", "", {
364 { BITS_EOT }
365 }},
366 {0x367, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR3", "", {
367 { BITS_EOT }
368 }},
369 {0x368, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR0", "", {
370 { BITS_EOT }
371 }},
372 {0x369, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR1", "", {
373 { BITS_EOT }
374 }},
375 {0x36a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR2", "", {
376 { BITS_EOT }
377 }},
378 {0x36b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR3", "", {
379 { BITS_EOT }
380 }},
381 {0x36c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR0", "", {
382 { BITS_EOT }
383 }},
384 {0x36d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR1", "", {
385 { BITS_EOT }
386 }},
387 {0x36e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR2", "", {
388 { BITS_EOT }
389 }},
390 {0x36f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR3", "", {
391 { BITS_EOT }
392 }},
393 {0x370, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR4", "", {
394 { BITS_EOT }
395 }},
396 {0x371, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR5", "", {
397 { BITS_EOT }
398 }},
399 {0x3a0, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR0", "", {
400 { BITS_EOT }
401 }},
402 {0x3a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR1", "", {
403 { BITS_EOT }
404 }},
405 {0x3a2, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR0", "", {
406 { BITS_EOT }
407 }},
408 {0x3a3, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR1", "", {
409 { BITS_EOT }
410 }},
411 {0x3a4, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR0", "", {
412 { BITS_EOT }
413 }},
414 {0x3a5, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR1", "", {
415 { BITS_EOT }
416 }},
417 {0x3a6, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR0", "", {
418 { BITS_EOT }
419 }},
420 {0x3a7, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR1", "", {
421 { BITS_EOT }
422 }},
423 {0x3a8, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR0", "", {
424 { BITS_EOT }
425 }},
426 {0x3a9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR1", "", {
427 { BITS_EOT }
428 }},
429 {0x3aa, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR0", "", {
430 { BITS_EOT }
431 }},
432 {0x3ab, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR1", "", {
433 { BITS_EOT }
434 }},
435 {0x3ac, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR0", "", {
436 { BITS_EOT }
437 }},
438 {0x3ad, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR1", "", {
439 { BITS_EOT }
440 }},
441 {0x3ae, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR0", "", {
442 { BITS_EOT }
443 }},
444 {0x3af, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR1", "", {
445 { BITS_EOT }
446 }},
447 {0x3b0, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR0", "", {
448 { BITS_EOT }
449 }},
450 {0x3b1, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR1", "", {
451 { BITS_EOT }
452 }},
453 {0x3b2, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR0", "", {
454 { BITS_EOT }
455 }},
456 {0x3b3, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR1", "", {
457 { BITS_EOT }
458 }},
459 {0x3b4, MSRTYPE_RDWR, MSR2(0,0), "MSR_IS_ESCR0", "", {
460 { BITS_EOT }
461 }},
462 {0x3b5, MSRTYPE_RDWR, MSR2(0,0), "MSR_IS_ESCR1", "", {
463 { BITS_EOT }
464 }},
465 {0x3b6, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR0", "", {
466 { BITS_EOT }
467 }},
468 {0x3b7, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR1", "", {
469 { BITS_EOT }
470 }},
471 {0x3b8, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR0", "", {
472 { BITS_EOT }
473 }},
474 {0x3b9, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR1", "", {
475 { BITS_EOT }
476 }},
477 {0x3ba, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR0", "", {
478 { BITS_EOT }
479 }},
480 /* MSR_IQ_ESCR1 MSR is not available on later processors.
481 It is only available on processor family 0FH, models 01H-02H */
482 //{0x3bb, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR1", "", {
483 // { BITS_EOT }
484 //}},
485 {0x3bc, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR0", "", {
486 { BITS_EOT }
487 }},
488 {0x3bd, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR1", "", {
489 { BITS_EOT }
490 }},
491 {0x3be, MSRTYPE_RDWR, MSR2(0,0), "MSR_SSU_ESCR0", "", {
492 { BITS_EOT }
493 }},
494 {0x3c0, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR0", "", {
495 { BITS_EOT }
496 }},
497 {0x3c1, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR1", "", {
498 { BITS_EOT }
499 }},
500 {0x3c2, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR0", "", {
501 { BITS_EOT }
502 }},
503 {0x3c3, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR1", "", {
504 { BITS_EOT }
505 }},
506 {0x3c4, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR0", "", {
507 { BITS_EOT }
508 }},
509 {0x3c5, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR1", "", {
510 { BITS_EOT }
511 }},
512 {0x3c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR0", "", {
513 { BITS_EOT }
514 }},
515 {0x3c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR0", "", {
516 { BITS_EOT }
517 }},
518 {0x3ca, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR0", "", {
519 { BITS_EOT }
520 }},
521 {0x3cb, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR1", "", {
522 { BITS_EOT }
523 }},
524 {0x3cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR2", "", {
525 { BITS_EOT }
526 }},
527 {0x3cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR3", "", {
528 { BITS_EOT }
529 }},
530 {0x3e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR4", "", {
531 { BITS_EOT }
532 }},
533 {0x3e1, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR5", "", {
534 { BITS_EOT }
535 }},
536 {0x3f0, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_PRECISE_EVENT", "", {
537 { BITS_EOT }
538 }},
539 {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_ENABLE", "", {
540 { BITS_EOT }
541 }},
542 {0x3f2, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_MATRIX_VERT", "", {
543 { BITS_EOT }
544 }},
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400545 {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
546 { BITS_EOT }
547 }},
548 {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
549 { BITS_EOT }
550 }},
551 {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
552 { BITS_EOT }
553 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200554 /* The IA32_MC0_MISC MSR is either not implemented or does
555 not contain additional information if the MISCV flag in
556 the IA32_MC0_STATUS register is clear. When not implemented
557 in the processor, all reads and writes to this MSR will
558 cause a generalprotection exception. */
559 //{0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {
560 // { BITS_EOT }
561 //}},
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400562 {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
563 { BITS_EOT }
564 }},
565 {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
566 { BITS_EOT }
567 }},
568 {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
569 { BITS_EOT }
570 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200571 /* The IA32_MC1_MISC MSR is either not implemented or does
572 not contain additional information if the MISCV flag in
573 the IA32_MC1_STATUS register is clear. When not implemented
574 in the processor, all reads and writes to this MSR will
575 cause a generalprotection exception.*/
576 //{0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", {
577 // { BITS_EOT }
578 //}},
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400579 {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
580 { BITS_EOT }
581 }},
582 {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
583 { BITS_EOT }
584 }},
585 {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
586 { BITS_EOT }
587 }},
588 {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
589 { BITS_EOT }
590 }},
591 {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
592 { BITS_EOT }
593 }},
594 {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
595 { BITS_EOT }
596 }},
597 {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
598 { BITS_EOT }
599 }},
600 {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
601 { BITS_EOT }
602 }},
603 {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
604 { BITS_EOT }
605 }},
606 {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
607 { BITS_EOT }
608 }},
609 {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
610 { BITS_EOT }
611 }},
612 {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
613 { BITS_EOT }
614 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200615 {0x481, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_PINBASED_CTLS", "", {
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400616 { BITS_EOT }
617 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200618 {0x482, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS", "", {
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400619 { BITS_EOT }
620 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200621 {0x483, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_EXIT_CTLS", "", {
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400622 { BITS_EOT }
623 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200624 {0x484, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", "", {
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400625 { BITS_EOT }
626 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200627 {0x485, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_MISC", "", {
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400628 { BITS_EOT }
629 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200630 {0x487, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED1", "", {
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400631 { BITS_EOT }
632 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200633 {0x489, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED1", "", {
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400634 { BITS_EOT }
635 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200636 {0x48b, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", "", {
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400637 { BITS_EOT }
638 }},
639 {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", {
640 { BITS_EOT }
641 }},
Elyes HAOUAS7ab98fb2016-07-22 17:46:52 +0200642 {0x680, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", {
643 { BITS_EOT }
644 }},
645 {0x682, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", {
646 { BITS_EOT }
647 }},
648 {0x684, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_FROM_IP", "", {
649 { BITS_EOT }
650 }},
651 {0x686, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_FROM_IP", "", {
652 { BITS_EOT }
653 }},
654 {0x688, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_8_FROM_IP", "", {
655 { BITS_EOT }
656 }},
657 {0x68a, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_10_FROM_IP", "", {
658 { BITS_EOT }
659 }},
660 {0x68c, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_12_FROM_IP", "", {
661 { BITS_EOT }
662 }},
663 {0x68e, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_14_FROM_IP", "", {
664 { BITS_EOT }
665 }},
666 {0x6c0, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_IP", "", {
667 { BITS_EOT }
668 }},
669 {0x6c2, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_IP", "", {
670 { BITS_EOT }
671 }},
672 {0x6c4, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_TO_IP", "", {
673 { BITS_EOT }
674 }},
675 {0x6c6, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_TO_IP", "", {
676 { BITS_EOT }
677 }},
678 {0x6c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_8_TO_IP", "", {
679 { BITS_EOT }
680 }},
681 {0x6ca, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_10_TO_IP", "", {
682 { BITS_EOT }
683 }},
684 {0x6cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_12_TO_IP", "", {
685 { BITS_EOT }
686 }},
687 {0x6ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_14_TO_IP", "", {
688 { BITS_EOT }
689 }},
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400690 { MSR_EOT }
691};