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review.coreboot.org / coreboot / 7c634ae8c18d1e311b5b96f09b5e6af23e57eaf7 / . / util / msrtool / intel_pentium4_later.c
blob: 6bb6ebea436919ffc44efca8b28e617f112fa21f [file] [log] [blame]
Anton Kochkov7c634ae2011-06-20 23:14:22 +0400[diff] [blame^]1/*
2 * This file is part of msrtool.
3 *
4 * Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include "msrtool.h"
21
22int intel_pentium4_later_probe(const struct targetdef *target) {
23 struct cpuid_t *id = cpuid();
24 return ((0xf == id->family)&((0x3 == id->model)|(0x4 == id->model)));
25}
26
27const struct msrdef intel_pentium4_later_msrs[] = {
28 {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
29 { BITS_EOT }
30 }},
31 {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
32 { BITS_EOT }
33 }},
34 {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_LINE_SIZE", "", {
35 { BITS_EOT }
36 }},
37 {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
38 { BITS_EOT }
39 }},
40 {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_HARD_POWERON", "", {
41 { BITS_EOT }
42 }},
43 {0x2b, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_SOFT_POWRON", "", {
44 { BITS_EOT }
45 }},
46 {0x2c, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_FREQUENCY_ID", "", {
47 { BITS_EOT }
48 }},
49 {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
50 { BITS_EOT }
51 }},
52 {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", {
53 { BITS_EOT }
54 }},
55 {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
56 { BITS_EOT }
57 }},
58 {0x1a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PLATFORM_BRV", "", {
59 { BITS_EOT }
60 }},
61 {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
62 { BITS_EOT }
63 }},
64 {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
65 { BITS_EOT }
66 }},
67 {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
68 { BITS_EOT }
69 }},
70 {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
71 { BITS_EOT }
72 }},
73 {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
74 { BITS_EOT }
75 }},
76 {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
77 { BITS_EOT }
78 }},
79 {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
80 { BITS_EOT }
81 }},
82 {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
83 { BITS_EOT }
84 }},
85 {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
86 { BITS_EOT }
87 }},
88 {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
89 { BITS_EOT }
90 }},
91 {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
92 { BITS_EOT }
93 }},
94 {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
95 { BITS_EOT }
96 }},
97 {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
98 { BITS_EOT }
99 }},
100 {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
101 { BITS_EOT }
102 }},
103 {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
104 { BITS_EOT }
105 }},
106 {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
107 { BITS_EOT }
108 }},
109 {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
110 { BITS_EOT }
111 }},
112 {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
113 { BITS_EOT }
114 }},
115 {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
116 { BITS_EOT }
117 }},
118 {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
119 { BITS_EOT }
120 }},
121 {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
122 { BITS_EOT }
123 }},
124 {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
125 { BITS_EOT }
126 }},
127 {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
128 { BITS_EOT }
129 }},
130 {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
131 { BITS_EOT }
132 }},
133 {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
134 { BITS_EOT }
135 }},
136 {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
137 { BITS_EOT }
138 }},
139 {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
140 { BITS_EOT }
141 }},
142 {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
143 { BITS_EOT }
144 }},
145 {0x300, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER0", "", {
146 { BITS_EOT }
147 }},
148 {0x301, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER1", "", {
149 { BITS_EOT }
150 }},
151 {0x302, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER2", "", {
152 { BITS_EOT }
153 }},
154 {0x303, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER3", "", {
155 { BITS_EOT }
156 }},
157 {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
158 { BITS_EOT }
159 }},
160 {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
161 { BITS_EOT }
162 }},
163 {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
164 { BITS_EOT }
165 }},
166 {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {
167 { BITS_EOT }
168 }},
169 {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
170 { BITS_EOT }
171 }},
172 {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
173 { BITS_EOT }
174 }},
175 {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
176 { BITS_EOT }
177 }},
178 {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", {
179 { BITS_EOT }
180 }},
181 {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
182 { BITS_EOT }
183 }},
184 {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
185 { BITS_EOT }
186 }},
187 {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
188 { BITS_EOT }
189 }},
190 {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
191 { BITS_EOT }
192 }},
193 {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
194 { BITS_EOT }
195 }},
196 {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
197 { BITS_EOT }
198 }},
199 {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
200 { BITS_EOT }
201 }},
202 {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
203 { BITS_EOT }
204 }},
205 {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
206 { BITS_EOT }
207 }},
208 {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
209 { BITS_EOT }
210 }},
211 {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
212 { BITS_EOT }
213 }},
214 {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
215 { BITS_EOT }
216 }},
217 {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
218 { BITS_EOT }
219 }},
220 {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
221 { BITS_EOT }
222 }},
223 {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
224 { BITS_EOT }
225 }},
226 {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
227 { BITS_EOT }
228 }},
229 {0x9b, MSRTYPE_RDWR, MSR2(0,0), "IA32_SMM_MONITOR_CTL", "", {
230 { BITS_EOT }
231 }},
232 {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
233 { BITS_EOT }
234 }},
235 {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
236 { BITS_EOT }
237 }},
238 {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
239 { BITS_EOT }
240 }},
241 {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
242 { BITS_EOT }
243 }},
244 {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
245 { BITS_EOT }
246 }},
247 {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
248 { BITS_EOT }
249 }},
250 {0x180, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RAX", "", {
251 { BITS_EOT }
252 }},
253 {0x181, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBX", "", {
254 { BITS_EOT }
255 }},
256 {0x182, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RCX", "", {
257 { BITS_EOT }
258 }},
259 {0x183, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDX", "", {
260 { BITS_EOT }
261 }},
262 {0x184, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSI", "", {
263 { BITS_EOT }
264 }},
265 {0x185, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDI", "", {
266 { BITS_EOT }
267 }},
268 {0x186, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBP", "", {
269 { BITS_EOT }
270 }},
271 {0x187, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSP", "", {
272 { BITS_EOT }
273 }},
274 {0x188, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RFLAGS", "", {
275 { BITS_EOT }
276 }},
277 {0x189, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RIP", "", {
278 { BITS_EOT }
279 }},
280 {0x18a, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_MISC", "", {
281 { BITS_EOT }
282 }},
283 {0x190, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R8", "", {
284 { BITS_EOT }
285 }},
286 {0x191, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R9", "", {
287 { BITS_EOT }
288 }},
289 {0x192, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R10", "", {
290 { BITS_EOT }
291 }},
292 {0x193, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R11", "", {
293 { BITS_EOT }
294 }},
295 {0x194, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R12", "", {
296 { BITS_EOT }
297 }},
298 {0x195, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R13", "", {
299 { BITS_EOT }
300 }},
301 {0x196, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R14", "", {
302 { BITS_EOT }
303 }},
304 {0x197, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R15", "", {
305 { BITS_EOT }
306 }},
307 {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
308 { BITS_EOT }
309 }},
310 {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", {
311 { BITS_EOT }
312 }},
313 {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
314 { BITS_EOT }
315 }},
316 {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
317 { BITS_EOT }
318 }},
319 {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
320 { BITS_EOT }
321 }},
322 {0x1d7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", {
323 { BITS_EOT }
324 }},
325 {0x1d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", {
326 { BITS_EOT }
327 }},
328 {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DEBUGCTLA", "", {
329 { BITS_EOT }
330 }},
331 {0x1da, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", {
332 { BITS_EOT }
333 }},
334 {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", {
335 { BITS_EOT }
336 }},
337 {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", {
338 { BITS_EOT }
339 }},
340 { MSR_EOT }
341};
342