Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <commonlib/helpers.h> |
| 5 | #include <delay.h> |
| 6 | #include <device/mmio.h> |
| 7 | #include <soc/clock.h> |
| 8 | #include <timer.h> |
| 9 | #include <types.h> |
| 10 | |
| 11 | /* Clock Branch Operations */ |
| 12 | static bool clock_is_off(u32 *cbcr_addr) |
| 13 | { |
| 14 | return (read32(cbcr_addr) & CLK_CTL_OFF_BMSK); |
| 15 | } |
| 16 | |
| 17 | enum cb_err clock_enable_vote(void *cbcr_addr, void *vote_addr, |
| 18 | uint32_t vote_bit) |
| 19 | { |
| 20 | int count = 100; |
| 21 | |
| 22 | setbits32(vote_addr, BIT(vote_bit)); |
| 23 | |
| 24 | /* Ensure clock is enabled */ |
| 25 | while (count-- > 0) { |
| 26 | if (!clock_is_off(cbcr_addr)) |
| 27 | return CB_SUCCESS; |
| 28 | udelay(1); |
| 29 | } |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 30 | printk(BIOS_ERR, "Failed to enable clock, register val: 0x%x\n", |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 31 | read32(cbcr_addr)); |
| 32 | return CB_ERR; |
| 33 | } |
| 34 | |
| 35 | enum cb_err clock_enable(void *cbcr_addr) |
| 36 | { |
| 37 | int count = 100; |
| 38 | |
| 39 | /* Set clock enable bit */ |
| 40 | setbits32(cbcr_addr, BIT(CLK_CTL_EN_SHFT)); |
| 41 | |
| 42 | /* Ensure clock is enabled */ |
| 43 | while (count-- > 0) { |
| 44 | if (!clock_is_off(cbcr_addr)) |
| 45 | return CB_SUCCESS; |
| 46 | udelay(1); |
| 47 | } |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 48 | printk(BIOS_ERR, "Failed to enable clock, register val: 0x%x\n", |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 49 | read32(cbcr_addr)); |
| 50 | return CB_ERR; |
| 51 | } |
| 52 | |
| 53 | /* Clock Block Reset Operations */ |
| 54 | void clock_reset_bcr(void *bcr_addr, bool assert) |
| 55 | { |
| 56 | if (assert) |
| 57 | setbits32(bcr_addr, BIT(CLK_CTL_BCR_BLK_SHFT)); |
| 58 | else |
| 59 | clrbits32(bcr_addr, BIT(CLK_CTL_BCR_BLK_SHFT)); |
| 60 | } |
| 61 | |
| 62 | /* Clock GDSC Operations */ |
| 63 | enum cb_err enable_and_poll_gdsc_status(void *gdscr_addr) |
| 64 | { |
| 65 | if (read32(gdscr_addr) & CLK_CTL_OFF_BMSK) |
| 66 | return CB_SUCCESS; |
| 67 | |
| 68 | clrbits32(gdscr_addr, BIT(GDSC_ENABLE_BIT)); |
| 69 | |
| 70 | /* Ensure gdsc is enabled */ |
| 71 | if (!wait_us(100, (read32(gdscr_addr) & CLK_CTL_OFF_BMSK))) |
| 72 | return CB_ERR; |
| 73 | |
| 74 | return CB_SUCCESS; |
| 75 | } |
| 76 | |
| 77 | /* Clock Root clock Generator with MND Operations */ |
| 78 | static void clock_configure_mnd(struct clock_rcg *clk, uint32_t m, uint32_t n, |
| 79 | uint32_t d_2) |
| 80 | { |
| 81 | struct clock_rcg_mnd *mnd = (struct clock_rcg_mnd *)clk; |
| 82 | |
| 83 | setbits32(&clk->rcg_cfg, |
| 84 | RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); |
| 85 | |
| 86 | write32(&mnd->m, m & CLK_CTL_RCG_MND_BMSK); |
| 87 | write32(&mnd->n, ~(n-m) & CLK_CTL_RCG_MND_BMSK); |
| 88 | write32(&mnd->d_2, ~(d_2) & CLK_CTL_RCG_MND_BMSK); |
| 89 | } |
| 90 | |
| 91 | /* Clock Root clock Generator Operations */ |
| 92 | enum cb_err clock_configure(struct clock_rcg *clk, |
| 93 | struct clock_freq_config *clk_cfg, uint32_t hz, |
| 94 | uint32_t num_perfs) |
| 95 | { |
| 96 | uint32_t reg_val, idx; |
| 97 | |
| 98 | for (idx = 0; idx < num_perfs; idx++) |
| 99 | if (hz <= clk_cfg[idx].hz) |
| 100 | break; |
| 101 | |
| 102 | reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | |
| 103 | (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); |
| 104 | |
| 105 | /* Set clock config */ |
| 106 | write32(&clk->rcg_cfg, reg_val); |
| 107 | |
| 108 | if (clk_cfg[idx].m != 0) |
| 109 | clock_configure_mnd(clk, clk_cfg[idx].m, clk_cfg[idx].n, |
| 110 | clk_cfg[idx].d_2); |
| 111 | |
| 112 | /* Commit config to RCG */ |
| 113 | setbits32(&clk->rcg_cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT)); |
| 114 | |
| 115 | return CB_SUCCESS; |
| 116 | } |
| 117 | |
| 118 | /* Clock Root clock Generator with DFS Operations */ |
| 119 | void clock_configure_dfsr_table(int qup, struct clock_freq_config *clk_cfg, |
| 120 | uint32_t num_perfs) |
| 121 | { |
| 122 | struct qupv3_clock *qup_clk; |
| 123 | unsigned int idx, s = qup % QUP_WRAP1_S0; |
| 124 | uint32_t reg_val; |
| 125 | |
| 126 | qup_clk = qup < QUP_WRAP1_S0 ? |
| 127 | &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; |
| 128 | |
| 129 | clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr, |
| 130 | BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT), |
| 131 | BIT(CLK_CTL_CMD_DFSR_SHFT)); |
| 132 | |
| 133 | for (idx = 0; idx < num_perfs; idx++) { |
| 134 | reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | |
| 135 | (clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT); |
| 136 | |
| 137 | write32(&qup_clk->dfsr_clk.perf_dfsr[idx], reg_val); |
| 138 | |
| 139 | if (clk_cfg[idx].m == 0) |
| 140 | continue; |
| 141 | |
| 142 | setbits32(&qup_clk->dfsr_clk.perf_dfsr[idx], |
| 143 | RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); |
| 144 | |
| 145 | reg_val = clk_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; |
| 146 | write32(&qup_clk->dfsr_clk.perf_m_dfsr[idx], reg_val); |
| 147 | |
| 148 | reg_val = ~(clk_cfg[idx].n - clk_cfg[idx].m) |
| 149 | & CLK_CTL_RCG_MND_BMSK; |
| 150 | write32(&qup_clk->dfsr_clk.perf_n_dfsr[idx], reg_val); |
| 151 | |
| 152 | reg_val = ~(clk_cfg[idx].d_2) & CLK_CTL_RCG_MND_BMSK; |
| 153 | write32(&qup_clk->dfsr_clk.perf_d_dfsr[idx], reg_val); |
| 154 | } |
| 155 | } |
| 156 | |
| 157 | /* General Purpose PLL configuration and enable Operations */ |
| 158 | enum cb_err clock_configure_enable_gpll(struct alpha_pll_reg_val_config *cfg, |
| 159 | bool enable, int br_enable) |
| 160 | { |
| 161 | if (cfg->l_val) |
| 162 | write32(cfg->reg_l, cfg->l_val); |
| 163 | |
| 164 | if (cfg->cal_l_val) |
| 165 | write32(cfg->reg_cal_l, cfg->cal_l_val); |
| 166 | |
| 167 | if (cfg->alpha_val) |
| 168 | write32(cfg->reg_alpha, cfg->alpha_val); |
| 169 | |
| 170 | if (cfg->user_ctl_val) |
| 171 | write32(cfg->reg_user_ctl, cfg->user_ctl_val); |
| 172 | |
| 173 | if (cfg->user_ctl_hi_val) |
| 174 | write32(cfg->reg_user_ctl_hi, cfg->user_ctl_hi_val); |
| 175 | |
| 176 | if (cfg->user_ctl_hi1_val) |
| 177 | write32(cfg->reg_user_ctl_hi1, cfg->user_ctl_hi1_val); |
| 178 | |
| 179 | if (cfg->config_ctl_val) |
| 180 | write32(cfg->reg_config_ctl, cfg->config_ctl_val); |
| 181 | |
| 182 | if (cfg->config_ctl_hi_val) |
| 183 | write32(cfg->reg_config_ctl_hi, cfg->config_ctl_hi_val); |
| 184 | |
| 185 | if (cfg->config_ctl_hi1_val) |
| 186 | write32(cfg->reg_config_ctl_hi1, cfg->config_ctl_hi1_val); |
| 187 | |
| 188 | if (cfg->fsm_enable) |
| 189 | setbits32(cfg->reg_mode, BIT(PLL_FSM_EN_SHFT)); |
| 190 | |
| 191 | if (enable) { |
| 192 | setbits32(cfg->reg_opmode, BIT(PLL_STANDBY_MODE)); |
| 193 | |
| 194 | /* |
| 195 | * H/W requires a 1us delay between placing PLL in STANDBY and |
| 196 | * de-asserting the reset. |
| 197 | */ |
| 198 | udelay(1); |
| 199 | setbits32(cfg->reg_mode, BIT(PLL_RESET_N_SHFT)); |
| 200 | |
| 201 | /* |
| 202 | * H/W requires a 10us delay between de-asserting the reset and |
| 203 | * enabling the PLL branch bit. |
| 204 | */ |
| 205 | udelay(10); |
| 206 | setbits32(cfg->reg_apcs_pll_br_en, BIT(br_enable)); |
| 207 | |
| 208 | /* Wait for Lock Detection */ |
| 209 | if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 210 | printk(BIOS_ERR, "PLL did not lock!\n"); |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 211 | return CB_ERR; |
| 212 | } |
| 213 | } |
| 214 | |
| 215 | return CB_SUCCESS; |
| 216 | } |
| 217 | |
| 218 | enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg) |
| 219 | { |
| 220 | setbits32(cfg->reg_mode, BIT(PLL_BYPASSNL_SHFT)); |
| 221 | |
| 222 | /* |
| 223 | * H/W requires a 5us delay between disabling the bypass and |
| 224 | * de-asserting the reset. |
| 225 | */ |
| 226 | udelay(5); |
| 227 | setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); |
| 228 | |
| 229 | if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 230 | printk(BIOS_ERR, "CPU PLL did not lock!\n"); |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 231 | return CB_ERR; |
| 232 | } |
| 233 | |
| 234 | setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT)); |
| 235 | |
| 236 | return CB_SUCCESS; |
| 237 | } |
| 238 | |
Taniya Das | 3fe6c03 | 2021-02-11 15:58:29 +0530 | [diff] [blame] | 239 | enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg) |
| 240 | { |
| 241 | setbits32(cfg->reg_mode, BIT(PLL_BYPASSNL_SHFT)); |
| 242 | |
| 243 | /* |
| 244 | * H/W requires a 1us delay between disabling the bypass and |
| 245 | * de-asserting the reset. |
| 246 | */ |
| 247 | udelay(1); |
| 248 | setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); |
| 249 | setbits32(cfg->reg_opmode, PLL_RUN_MODE); |
| 250 | |
| 251 | if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 252 | printk(BIOS_ERR, "CPU PLL did not lock!\n"); |
Taniya Das | 3fe6c03 | 2021-02-11 15:58:29 +0530 | [diff] [blame] | 253 | return CB_ERR; |
| 254 | } |
| 255 | |
| 256 | setbits32(cfg->reg_user_ctl, PLL_USERCTL_BMSK); |
| 257 | setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT)); |
| 258 | |
| 259 | return CB_SUCCESS; |
| 260 | } |
| 261 | |
Taniya Das | d37aeb1 | 2021-06-23 09:08:57 +0530 | [diff] [blame] | 262 | /* Bring subsystem out of RESET */ |
| 263 | void clock_reset_subsystem(u32 *misc, u32 shft) |
| 264 | { |
| 265 | clrbits32(misc, BIT(shft)); |
| 266 | } |