Angel Pons | b5a2a52 | 2020-04-05 13:21:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 2 | |
Felix Held | 907cc5a | 2021-12-17 18:51:21 +0100 | [diff] [blame] | 3 | #include <soc/amd/stoneyridge/chip.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 4 | #include <amdblocks/agesawrapper.h> |
Chris Wang | 50c1160 | 2018-11-05 12:09:24 +0800 | [diff] [blame] | 5 | #include <gpio.h> |
| 6 | #include <console/console.h> |
| 7 | #include <soc/pci_devs.h> |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 8 | |
Marshall Dawson | 3f6c400 | 2017-09-25 10:11:50 -0600 | [diff] [blame] | 9 | #define DIMMS_PER_CHANNEL 1 |
| 10 | #if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH |
| 11 | #error "Too many DIMM sockets defined for the mainboard" |
| 12 | #endif |
| 13 | |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 14 | static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { |
| 15 | DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), |
Marshall Dawson | 3f6c400 | 2017-09-25 10:11:50 -0600 | [diff] [blame] | 16 | NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL), |
| 17 | NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 18 | MOTHER_BOARD_LAYERS(LAYERS_6), |
| 19 | MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, |
| 20 | 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |
| 21 | CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), |
| 22 | ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), |
| 23 | CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, |
| 24 | 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |
| 25 | PSO_END |
| 26 | }; |
Martin Roth | 3f68911 | 2018-12-17 13:33:10 -0700 | [diff] [blame] | 27 | /* Liara-specific 2T memory configuration */ |
Peichao Wang | 28086f0 | 2019-08-27 16:51:04 +0800 | [diff] [blame] | 28 | static const PSO_ENTRY DDR4_2T_MemoryConfiguration[] = { |
chris wang | 76118a7 | 2018-10-18 18:52:58 +0800 | [diff] [blame] | 29 | DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), |
| 30 | NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL), |
| 31 | NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), |
| 32 | MOTHER_BOARD_LAYERS(LAYERS_6), |
| 33 | MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, |
| 34 | 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |
| 35 | CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), |
| 36 | ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), |
| 37 | CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, |
| 38 | 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |
| 39 | TBLDRV_CONFIG_TO_OVERRIDE(DIMMS_PER_CHANNEL, ANY_SPEED, VOLT_ANY_, |
| 40 | ANY_), |
| 41 | TBLDRV_CONFIG_ENTRY_SLOWACCMODE(1), |
| 42 | PSO_END |
| 43 | }; |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 44 | |
| 45 | void OemPostParams(AMD_POST_PARAMS *PostParams) |
| 46 | { |
Peichao Wang | 28086f0 | 2019-08-27 16:51:04 +0800 | [diff] [blame] | 47 | if (CONFIG(BOARD_GOOGLE_LIARA) || CONFIG(BOARD_GOOGLE_TREEYA)) |
chris wang | 76118a7 | 2018-10-18 18:52:58 +0800 | [diff] [blame] | 48 | PostParams->MemConfig.PlatformMemoryConfiguration = |
Peichao Wang | 28086f0 | 2019-08-27 16:51:04 +0800 | [diff] [blame] | 49 | (PSO_ENTRY *)DDR4_2T_MemoryConfiguration; |
chris wang | 76118a7 | 2018-10-18 18:52:58 +0800 | [diff] [blame] | 50 | else |
| 51 | PostParams->MemConfig.PlatformMemoryConfiguration = |
| 52 | (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; |
Richard Spiegel | 9b3da9f | 2018-02-16 14:33:59 -0700 | [diff] [blame] | 53 | /* |
| 54 | * Bank interleaving is enabled by default in AGESA. However, from AMD's |
| 55 | * explanation, bank interleaving is really chip select interleave, |
| 56 | * requiring 2 chip select arriving to the DIMM (rank interleaving). As |
| 57 | * both kahlee and grunt are hardware limited to a single chip select |
| 58 | * arriving at the DIMM, interleave will not work. This causes AGESA to |
| 59 | * throw a warning. To avoid the warning, interleaving needs to be |
| 60 | * disabled. |
| 61 | */ |
| 62 | PostParams->MemConfig.EnableBankIntlv = FALSE; |
Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame] | 63 | } |
Richard Spiegel | 5d3707b | 2018-07-27 12:44:22 -0700 | [diff] [blame] | 64 | |
| 65 | void set_board_env_params(GNB_ENV_CONFIGURATION *params) |
| 66 | { |
Chris Wang | 50c1160 | 2018-11-05 12:09:24 +0800 | [diff] [blame] | 67 | const struct soc_amd_stoneyridge_config *cfg; |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 68 | const struct device *dev = pcidev_path_on_root(GNB_DEVFN); |
Chris Wang | 50c1160 | 2018-11-05 12:09:24 +0800 | [diff] [blame] | 69 | if (!dev || !dev->chip_info) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame^] | 70 | printk(BIOS_WARNING, "Cannot find SoC devicetree config\n"); |
Chris Wang | 50c1160 | 2018-11-05 12:09:24 +0800 | [diff] [blame] | 71 | return; |
| 72 | } |
| 73 | cfg = dev->chip_info; |
| 74 | if (cfg->lvds_poseq_blon_to_varybl && cfg->lvds_poseq_varybl_to_blon) { |
| 75 | /* |
| 76 | * GPIO 133 - Backlight enable (active low) |
| 77 | * Pass control of the backlight to the video BIOS |
| 78 | */ |
| 79 | gpio_set(GPIO_133, 0); |
| 80 | printk(BIOS_INFO, "Change panel init timing\n"); |
| 81 | params->LvdsPowerOnSeqVaryBlToBlon = |
| 82 | cfg->lvds_poseq_varybl_to_blon; |
| 83 | params->LvdsPowerOnSeqBlonToVaryBl = |
| 84 | cfg->lvds_poseq_blon_to_varybl; |
| 85 | printk(BIOS_INFO, "LvdsPowerOnSeqVaryBlToBlon: %dms\n", |
| 86 | (params->LvdsPowerOnSeqVaryBlToBlon)*4); |
| 87 | printk(BIOS_INFO, "LvdsPowerOnSeqBlonToVaryBl: %dms\n", |
| 88 | (params->LvdsPowerOnSeqBlonToVaryBl)*4); |
| 89 | } |
Richard Spiegel | 5d3707b | 2018-07-27 12:44:22 -0700 | [diff] [blame] | 90 | params->EDPv1_4VSMode = EDP_VS_HIGH_VDIFF_MODE; |
| 91 | } |