| Marc Jones | 2d79f16 | 2017-05-22 21:35:16 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <agesawrapper.h> |
| 17 | #include <PlatformMemoryConfiguration.h> |
| 18 | |
| 19 | #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE |
| 20 | |
| 21 | static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { |
| 22 | DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), |
| 23 | NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), |
| 24 | NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), |
| 25 | MOTHER_BOARD_LAYERS(LAYERS_6), |
| 26 | MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, |
| 27 | 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |
| 28 | CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), |
| 29 | ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), |
| 30 | CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, |
| 31 | 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), |
| 32 | PSO_END |
| 33 | }; |
| 34 | |
| 35 | void OemPostParams(AMD_POST_PARAMS *PostParams) |
| 36 | { |
| 37 | PostParams->MemConfig.PlatformMemoryConfiguration = |
| 38 | (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; |
| 39 | } |