Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2 | |
Elyes Haouas | 4114fdc | 2022-10-02 13:48:07 +0200 | [diff] [blame] | 3 | #include <cf9_reset.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | 7fbed22 | 2019-07-11 08:14:07 +0300 | [diff] [blame] | 5 | #include <delay.h> |
Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 6 | #include <device/device.h> |
Elyes Haouas | 4114fdc | 2022-10-02 13:48:07 +0200 | [diff] [blame] | 7 | #include <device/dram/ddr2.h> |
| 8 | #include <device/mmio.h> |
| 9 | #include <device/pci_ops.h> |
| 10 | #include <device/pci_type.h> |
| 11 | #include <device/smbus_host.h> |
Julius Werner | 7a8a4ab | 2015-05-22 16:26:40 -0700 | [diff] [blame] | 12 | #include <lib.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 13 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 14 | #include <spd.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 15 | #include <string.h> |
Elyes Haouas | 4114fdc | 2022-10-02 13:48:07 +0200 | [diff] [blame] | 16 | #include <timestamp.h> |
| 17 | #include <types.h> |
| 18 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 19 | #include "raminit.h" |
| 20 | #include "i945.h" |
Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 21 | #include "chip.h" |
Rudolf Marek | c436953 | 2010-12-13 19:59:13 +0000 | [diff] [blame] | 22 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 23 | /* Debugging macros. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 24 | #if CONFIG(DEBUG_RAM_SETUP) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 25 | #define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 26 | #else |
| 27 | #define PRINTK_DEBUG(x...) |
| 28 | #endif |
| 29 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 30 | #define RAM_INITIALIZATION_COMPLETE (1 << 19) |
| 31 | |
| 32 | #define RAM_COMMAND_SELF_REFRESH (0x0 << 16) |
| 33 | #define RAM_COMMAND_NOP (0x1 << 16) |
| 34 | #define RAM_COMMAND_PRECHARGE (0x2 << 16) |
| 35 | #define RAM_COMMAND_MRS (0x3 << 16) |
| 36 | #define RAM_COMMAND_EMRS (0x4 << 16) |
| 37 | #define RAM_COMMAND_CBR (0x6 << 16) |
| 38 | #define RAM_COMMAND_NORMAL (0x7 << 16) |
| 39 | |
| 40 | #define RAM_EMRS_1 (0x0 << 21) |
| 41 | #define RAM_EMRS_2 (0x1 << 21) |
| 42 | #define RAM_EMRS_3 (0x2 << 21) |
| 43 | |
Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 44 | #define DEFAULT_PCI_MMIO_SIZE 768 |
Sven Schnelle | 541269b | 2011-02-21 09:39:17 +0000 | [diff] [blame] | 45 | static int get_dimm_spd_address(struct sys_info *sysinfo, int device) |
| 46 | { |
| 47 | if (sysinfo->spd_addresses) |
| 48 | return sysinfo->spd_addresses[device]; |
| 49 | else |
Angel Pons | e97a66d | 2021-04-03 00:15:16 +0200 | [diff] [blame] | 50 | return 0x50 + device; |
Sven Schnelle | 541269b | 2011-02-21 09:39:17 +0000 | [diff] [blame] | 51 | |
| 52 | } |
| 53 | |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 54 | static __attribute__((noinline)) void do_ram_command(u32 command) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 55 | { |
| 56 | u32 reg32; |
| 57 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 58 | reg32 = mchbar_read32(DCC); |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 59 | reg32 &= ~((3 << 21) | (1 << 20) | (1 << 19) | (7 << 16)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 60 | reg32 |= command; |
| 61 | |
| 62 | /* Also set Init Complete */ |
| 63 | if (command == RAM_COMMAND_NORMAL) |
| 64 | reg32 |= RAM_INITIALIZATION_COMPLETE; |
| 65 | |
| 66 | PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32); |
| 67 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 68 | mchbar_write32(DCC, reg32); /* This is the actual magic */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 69 | |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 70 | PRINTK_DEBUG("...done\n"); |
Stefan Reinauer | d058ad1 | 2010-08-26 12:43:58 +0000 | [diff] [blame] | 71 | |
| 72 | udelay(1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 73 | } |
| 74 | |
Elyes HAOUAS | 964055d | 2022-01-14 18:56:49 +0100 | [diff] [blame] | 75 | static void ram_read32(uintptr_t offset) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 76 | { |
Elyes Haouas | e8bb6d2 | 2022-10-04 14:16:09 +0200 | [diff] [blame^] | 77 | PRINTK_DEBUG(" RAM read: %" PRIxPTR "\n", offset); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 78 | |
Elyes Haouas | 712c70b | 2022-02-25 10:05:22 +0100 | [diff] [blame] | 79 | read32p(offset); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 80 | } |
| 81 | |
Stefan Reinauer | 3c0bfaf | 2010-12-27 11:34:57 +0000 | [diff] [blame] | 82 | void sdram_dump_mchbar_registers(void) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 83 | { |
| 84 | int i; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 85 | printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 86 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 87 | for (i = 0; i < 0xfff; i += 4) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 88 | if (mchbar_read32(i) == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 89 | continue; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 90 | printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, mchbar_read32(i)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 91 | } |
| 92 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 93 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 94 | static int memclk(void) |
| 95 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 96 | int offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; |
Elyes HAOUAS | c9848a8 | 2016-10-09 20:24:20 +0200 | [diff] [blame] | 97 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 98 | switch (((mchbar_read32(CLKCFG) >> 4) & 7) - offset) { |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 99 | case 1: return 400; |
| 100 | case 2: return 533; |
| 101 | case 3: return 667; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 102 | default: |
Elyes HAOUAS | 3cd4327 | 2020-03-05 22:01:17 +0100 | [diff] [blame] | 103 | printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 104 | ((mchbar_read32(CLKCFG) >> 4) & 7) - offset); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 105 | } |
| 106 | return -1; |
| 107 | } |
| 108 | |
Peter Stuge | 76d9143 | 2010-10-01 10:02:33 +0000 | [diff] [blame] | 109 | static u16 fsbclk(void) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 110 | { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 111 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 112 | switch (mchbar_read32(CLKCFG) & 7) { |
Elyes HAOUAS | c9848a8 | 2016-10-09 20:24:20 +0200 | [diff] [blame] | 113 | case 0: return 400; |
| 114 | case 1: return 533; |
| 115 | case 3: return 667; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 116 | default: |
Elyes HAOUAS | 3cd4327 | 2020-03-05 22:01:17 +0100 | [diff] [blame] | 117 | printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 118 | mchbar_read32(CLKCFG) & 7); |
Elyes HAOUAS | c9848a8 | 2016-10-09 20:24:20 +0200 | [diff] [blame] | 119 | } |
| 120 | return 0xffff; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 121 | } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 122 | switch (mchbar_read32(CLKCFG) & 7) { |
Elyes HAOUAS | c9848a8 | 2016-10-09 20:24:20 +0200 | [diff] [blame] | 123 | case 0: return 1066; |
| 124 | case 1: return 533; |
| 125 | case 2: return 800; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 126 | default: |
Elyes HAOUAS | 3cd4327 | 2020-03-05 22:01:17 +0100 | [diff] [blame] | 127 | printk(BIOS_DEBUG, "%s: unknown register value %x\n", __func__, |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 128 | mchbar_read32(CLKCFG) & 7); |
Elyes HAOUAS | c9848a8 | 2016-10-09 20:24:20 +0200 | [diff] [blame] | 129 | } |
| 130 | return 0xffff; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 131 | } |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 132 | } |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 133 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 134 | static int sdram_capabilities_max_supported_memory_frequency(void) |
| 135 | { |
| 136 | u32 reg32; |
| 137 | |
Patrick Georgi | 77d6683 | 2010-10-01 08:02:45 +0000 | [diff] [blame] | 138 | #if CONFIG_MAXIMUM_SUPPORTED_FREQUENCY |
| 139 | return CONFIG_MAXIMUM_SUPPORTED_FREQUENCY; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 140 | #endif |
| 141 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 142 | reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 143 | reg32 &= (7 << 0); |
| 144 | |
| 145 | switch (reg32) { |
| 146 | case 4: return 400; |
| 147 | case 3: return 533; |
| 148 | case 2: return 667; |
| 149 | } |
| 150 | /* Newer revisions of this chipset rather support faster memory clocks, |
| 151 | * so if it's a reserved value, return the fastest memory clock that we |
| 152 | * know of and can handle |
| 153 | */ |
| 154 | return 667; |
| 155 | } |
| 156 | |
| 157 | /** |
| 158 | * @brief determine whether chipset is capable of dual channel interleaved mode |
| 159 | * |
| 160 | * @return 1 if interleaving is supported, 0 otherwise |
| 161 | */ |
| 162 | static int sdram_capabilities_interleave(void) |
| 163 | { |
| 164 | u32 reg32; |
| 165 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 166 | reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 167 | reg32 >>= 25; |
| 168 | reg32 &= 1; |
| 169 | |
| 170 | return (!reg32); |
| 171 | } |
| 172 | |
| 173 | /** |
| 174 | * @brief determine whether chipset is capable of two memory channels |
| 175 | * |
| 176 | * @return 1 if dual channel operation is supported, 0 otherwise |
| 177 | */ |
| 178 | static int sdram_capabilities_dual_channel(void) |
| 179 | { |
| 180 | u32 reg32; |
| 181 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 182 | reg32 = pci_read_config32(HOST_BRIDGE, 0xe4); /* CAPID0 + 4 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 183 | reg32 >>= 24; |
| 184 | reg32 &= 1; |
| 185 | |
| 186 | return (!reg32); |
| 187 | } |
| 188 | |
| 189 | static int sdram_capabilities_enhanced_addressing_xor(void) |
| 190 | { |
| 191 | u8 reg8; |
| 192 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 193 | reg8 = pci_read_config8(HOST_BRIDGE, 0xe5); /* CAPID0 + 5 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 194 | reg8 &= (1 << 7); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 195 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 196 | return (!reg8); |
| 197 | } |
| 198 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 199 | #define GFX_FREQUENCY_CAP_166MHZ 0x04 |
| 200 | #define GFX_FREQUENCY_CAP_200MHZ 0x03 |
| 201 | #define GFX_FREQUENCY_CAP_250MHZ 0x02 |
| 202 | #define GFX_FREQUENCY_CAP_ALL 0x00 |
| 203 | |
| 204 | static int sdram_capabilities_core_frequencies(void) |
| 205 | { |
| 206 | u8 reg8; |
| 207 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 208 | reg8 = pci_read_config8(HOST_BRIDGE, 0xe5); /* CAPID0 + 5 */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 209 | reg8 &= (1 << 3) | (1 << 2) | (1 << 1); |
| 210 | reg8 >>= 1; |
| 211 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 212 | return reg8; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 213 | } |
| 214 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 215 | static void sdram_detect_errors(struct sys_info *sysinfo) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 216 | { |
| 217 | u8 reg8; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 218 | u8 do_reset = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 219 | |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 220 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 221 | |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 222 | if (reg8 & ((1 << 7) | (1 << 2))) { |
| 223 | if (reg8 & (1 << 2)) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 224 | printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); |
Stefan Reinauer | f98ad3a | 2010-03-05 18:25:19 +0000 | [diff] [blame] | 225 | /* Write back clears bit 2 */ |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 226 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); |
Stefan Reinauer | f98ad3a | 2010-03-05 18:25:19 +0000 | [diff] [blame] | 227 | do_reset = 1; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 228 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 229 | } |
| 230 | |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 231 | if (reg8 & (1 << 7)) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 232 | printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 233 | reg8 &= ~(1 << 7); |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 234 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 235 | do_reset = 1; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 236 | } |
| 237 | |
| 238 | /* Set SLP_S3# Assertion Stretch Enable */ |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 239 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 240 | reg8 |= (1 << 3); |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 241 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 242 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 243 | if (do_reset) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 244 | printk(BIOS_DEBUG, "Reset required.\n"); |
Elyes HAOUAS | 420d7e0 | 2019-04-21 18:39:34 +0200 | [diff] [blame] | 245 | full_reset(); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 246 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 247 | } |
| 248 | |
| 249 | /* Set DRAM initialization bit in ICH7 */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 250 | pci_or_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, 1 << 7); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 251 | |
Peter Stuge | 751508a | 2012-01-27 22:17:09 +0100 | [diff] [blame] | 252 | /* clear self refresh status if check is disabled or not a resume */ |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 253 | if (!CONFIG(CHECK_SLFRCS_ON_RESUME) || sysinfo->boot_path != BOOT_PATH_RESUME) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 254 | mchbar_setbits8(SLFRCS, 3); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 255 | } else { |
| 256 | /* Validate self refresh config */ |
| 257 | if (((sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) || |
| 258 | (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) && |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 259 | !(mchbar_read8(SLFRCS) & (1 << 0))) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 260 | do_reset = 1; |
| 261 | } |
| 262 | if (((sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) || |
| 263 | (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) && |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 264 | !(mchbar_read8(SLFRCS) & (1 << 1))) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 265 | do_reset = 1; |
| 266 | } |
| 267 | } |
| 268 | |
| 269 | if (do_reset) { |
| 270 | printk(BIOS_DEBUG, "Reset required.\n"); |
Elyes HAOUAS | 420d7e0 | 2019-04-21 18:39:34 +0200 | [diff] [blame] | 271 | full_reset(); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 272 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 273 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 274 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 275 | struct timings { |
| 276 | u32 min_tCLK_cas[8]; |
| 277 | u32 min_tRAS; |
| 278 | u32 min_tRP; |
| 279 | u32 min_tRCD; |
| 280 | u32 min_tWR; |
| 281 | u32 min_tRFC; |
| 282 | u32 max_tRR; |
| 283 | u8 cas_mask; |
| 284 | }; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 285 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 286 | /** |
| 287 | * @brief loop over dimms and save maximal timings |
| 288 | */ |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 289 | static void gather_common_timing(struct sys_info *sysinfo, struct timings *saved_timings) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 290 | { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 291 | |
| 292 | int i, j; |
| 293 | u8 raw_spd[SPD_SIZE_MAX_DDR2]; |
| 294 | u8 dimm_mask = 0; |
| 295 | |
| 296 | memset(saved_timings, 0, sizeof(*saved_timings)); |
| 297 | saved_timings->max_tRR = UINT32_MAX; |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 298 | saved_timings->cas_mask = SPD_CAS_LATENCY_DDR2_3 | SPD_CAS_LATENCY_DDR2_4 |
| 299 | | SPD_CAS_LATENCY_DDR2_5; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 300 | |
| 301 | /** |
| 302 | * i945 supports two DIMMs, in two configurations: |
| 303 | * |
Uwe Hermann | d773fd3 | 2010-11-20 20:23:08 +0000 | [diff] [blame] | 304 | * - single channel with two DIMMs |
| 305 | * - dual channel with one DIMM per channel |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 306 | * |
Uwe Hermann | d773fd3 | 2010-11-20 20:23:08 +0000 | [diff] [blame] | 307 | * In practice dual channel mainboards have their SPD at 0x50/0x52 |
| 308 | * whereas single channel configurations have their SPD at 0x50/0x51. |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 309 | * |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 310 | * The capability register knows a lot about the channel configuration |
Uwe Hermann | d773fd3 | 2010-11-20 20:23:08 +0000 | [diff] [blame] | 311 | * but for now we stick with the information we gather via SPD. |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 312 | */ |
| 313 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 314 | printk(BIOS_DEBUG, "This mainboard supports "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 315 | if (sdram_capabilities_dual_channel()) { |
| 316 | sysinfo->dual_channel = 1; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 317 | printk(BIOS_DEBUG, "Dual Channel Operation.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 318 | } else { |
| 319 | sysinfo->dual_channel = 0; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 320 | printk(BIOS_DEBUG, "only Single Channel Operation.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 321 | } |
| 322 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 323 | for (i = 0; i < (2 * DIMM_SOCKETS); i++) { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 324 | int device = get_dimm_spd_address(sysinfo, i), bytes_read; |
Arthur Heymans | fc31e44 | 2018-02-12 15:12:34 +0100 | [diff] [blame] | 325 | struct dimm_attr_ddr2_st dimm_info; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 326 | |
| 327 | /* Initialize the socket information with a sane value */ |
| 328 | sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; |
| 329 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 330 | /* Dual Channel not supported, but Channel 1? Bail out */ |
| 331 | if (!sdram_capabilities_dual_channel() && (i >> 1)) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 332 | continue; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 333 | |
Kyösti Mälkki | bd65985 | 2020-01-05 20:00:18 +0200 | [diff] [blame] | 334 | if (smbus_read_byte(device, SPD_MEMORY_TYPE) != |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 335 | SPD_MEMORY_TYPE_SDRAM_DDR2) { |
| 336 | printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: N/A\n", |
| 337 | (i >> 1), (i & 1)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 338 | continue; |
| 339 | } |
| 340 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 341 | /* |
| 342 | * spd_decode_ddr2() needs a 128-byte sized array but |
| 343 | * only the first 64 bytes contain data needed for raminit. |
| 344 | */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 345 | |
Kyösti Mälkki | c01a505 | 2019-01-30 09:39:23 +0200 | [diff] [blame] | 346 | bytes_read = i2c_eeprom_read(device, 0, 64, raw_spd); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 347 | printk(BIOS_DEBUG, "Reading SPD using i2c block operation.\n"); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 348 | if (CONFIG(DEBUG_RAM_SETUP) && bytes_read > 0) |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 349 | hexdump(raw_spd, bytes_read); |
Arthur Heymans | 5661945 | 2017-09-21 09:12:42 +0200 | [diff] [blame] | 350 | if (bytes_read != 64) { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 351 | /* Try again with SMBUS byte read */ |
| 352 | printk(BIOS_DEBUG, "i2c block operation failed," |
Paul Menzel | 105e368 | 2017-09-21 08:11:05 +0200 | [diff] [blame] | 353 | " trying smbus byte operation.\n"); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 354 | for (j = 0; j < 64; j++) |
Kyösti Mälkki | bd65985 | 2020-01-05 20:00:18 +0200 | [diff] [blame] | 355 | raw_spd[j] = smbus_read_byte(device, j); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 356 | if (CONFIG(DEBUG_RAM_SETUP)) |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 357 | hexdump(raw_spd, 64); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 358 | } |
Arthur Heymans | 5661945 | 2017-09-21 09:12:42 +0200 | [diff] [blame] | 359 | |
| 360 | if (spd_decode_ddr2(&dimm_info, raw_spd) != SPD_STATUS_OK) { |
| 361 | printk(BIOS_WARNING, "Encountered problems with SPD, " |
| 362 | "skipping this DIMM.\n"); |
| 363 | continue; |
| 364 | } |
| 365 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 366 | if (CONFIG(DEBUG_RAM_SETUP)) |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 367 | dram_print_spd_ddr2(&dimm_info); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 368 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 369 | if (dimm_info.flags.is_ecc) |
| 370 | die("\nError: ECC memory not supported by this chipset\n"); |
| 371 | |
| 372 | if (spd_dimm_is_registered_ddr2(dimm_info.dimm_type)) |
| 373 | die("\nError: Registered memory not supported by this chipset\n"); |
| 374 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 375 | printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 376 | /** |
| 377 | * There are 5 different possible populations for a DIMM socket: |
| 378 | * 0. x16 double ranked (X16DS) |
| 379 | * 1. x8 double ranked (X8DS) |
| 380 | * 2. x16 single ranked (X16SS) |
| 381 | * 3. x8 double stacked (X8DDS) |
| 382 | * 4. Unpopulated |
| 383 | */ |
| 384 | switch (dimm_info.width) { |
| 385 | case 8: |
| 386 | switch (dimm_info.ranks) { |
| 387 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 388 | printk(BIOS_DEBUG, "x8DDS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 389 | sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS; |
| 390 | break; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 391 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 392 | printk(BIOS_DEBUG, "x8DS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 393 | sysinfo->dimm[i] = SYSINFO_DIMM_X8DS; |
| 394 | break; |
| 395 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 396 | printk(BIOS_DEBUG, "Unsupported.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 397 | } |
| 398 | break; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 399 | case 16: |
| 400 | switch (dimm_info.ranks) { |
| 401 | case 2: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 402 | printk(BIOS_DEBUG, "x16DS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 403 | sysinfo->dimm[i] = SYSINFO_DIMM_X16DS; |
| 404 | break; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 405 | case 1: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 406 | printk(BIOS_DEBUG, "x16SS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 407 | sysinfo->dimm[i] = SYSINFO_DIMM_X16SS; |
| 408 | break; |
| 409 | default: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 410 | printk(BIOS_DEBUG, "Unsupported.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 411 | } |
| 412 | break; |
| 413 | default: |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 414 | die("Unsupported DDR-II memory width.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 415 | } |
| 416 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 417 | /* Is the current DIMM a stacked DIMM? */ |
| 418 | if (dimm_info.flags.stacked) |
| 419 | sysinfo->package = SYSINFO_PACKAGE_STACKED; |
| 420 | |
| 421 | if (!dimm_info.flags.bl8) |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 422 | die("Only DDR-II RAM with burst length 8 is supported.\n"); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 423 | |
| 424 | if (dimm_info.ranksize_mb < 128) |
| 425 | die("DDR-II rank size smaller than 128MB is not supported.\n"); |
| 426 | |
| 427 | sysinfo->banksize[i * 2] = dimm_info.ranksize_mb / 32; |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 428 | printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 429 | if (dimm_info.ranks == 2) { |
| 430 | sysinfo->banksize[(i * 2) + 1] = |
| 431 | dimm_info.ranksize_mb / 32; |
| 432 | printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", |
| 433 | i, sysinfo->banksize[(i * 2) + 1] * 32); |
| 434 | } |
| 435 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 436 | sysinfo->rows[i] = dimm_info.row_bits; |
| 437 | sysinfo->cols[i] = dimm_info.col_bits; |
| 438 | sysinfo->banks[i] = dimm_info.banks; |
| 439 | |
| 440 | /* int min_tRAS, min_tRP, min_tRCD, min_tWR, min_tRFC; */ |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 441 | saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, dimm_info.tRAS); |
| 442 | saved_timings->min_tRP = MAX(saved_timings->min_tRP, dimm_info.tRP); |
| 443 | saved_timings->min_tRCD = MAX(saved_timings->min_tRCD, dimm_info.tRCD); |
| 444 | saved_timings->min_tWR = MAX(saved_timings->min_tWR, dimm_info.tWR); |
| 445 | saved_timings->min_tRFC = MAX(saved_timings->min_tRFC, dimm_info.tRFC); |
| 446 | saved_timings->max_tRR = MIN(saved_timings->max_tRR, dimm_info.tRR); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 447 | saved_timings->cas_mask &= dimm_info.cas_supported; |
| 448 | for (j = 0; j < 8; j++) { |
| 449 | if (!(saved_timings->cas_mask & (1 << j))) |
| 450 | saved_timings->min_tCLK_cas[j] = 0; |
| 451 | else |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 452 | saved_timings->min_tCLK_cas[j] = MAX(dimm_info.cycle_time[j], |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 453 | saved_timings->min_tCLK_cas[j]); |
| 454 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 455 | dimm_mask |= (1 << i); |
| 456 | } |
Elyes HAOUAS | 9749a85 | 2018-05-09 19:06:46 +0200 | [diff] [blame] | 457 | if (!dimm_mask) |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 458 | die("No memory installed.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 459 | |
Elyes HAOUAS | 9749a85 | 2018-05-09 19:06:46 +0200 | [diff] [blame] | 460 | if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 461 | /* FIXME: Possibly does not boot in this case */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 462 | printk(BIOS_INFO, "Channel 0 has no memory populated.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 463 | } |
| 464 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 465 | static void choose_tclk(struct sys_info *sysinfo, struct timings *saved_timings) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 466 | { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 467 | u32 ctrl_min_tclk; |
| 468 | int try_cas; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 469 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 470 | ctrl_min_tclk = 2 * 256 * 1000 / sdram_capabilities_max_supported_memory_frequency(); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 471 | normalize_tck(&ctrl_min_tclk); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 472 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 473 | try_cas = spd_get_msbs(saved_timings->cas_mask); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 474 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 475 | while (saved_timings->cas_mask & (1 << try_cas) && try_cas > 0) { |
| 476 | sysinfo->cas = try_cas; |
| 477 | sysinfo->tclk = saved_timings->min_tCLK_cas[try_cas]; |
| 478 | if (sysinfo->tclk >= ctrl_min_tclk && |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 479 | saved_timings->min_tCLK_cas[try_cas] != |
| 480 | saved_timings->min_tCLK_cas[try_cas - 1]) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 481 | break; |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 482 | try_cas--; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 483 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 484 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 485 | normalize_tck(&sysinfo->tclk); |
| 486 | |
| 487 | if ((sysinfo->cas < 3) || (sysinfo->tclk == 0)) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 488 | die("Could not find common memory frequency and CAS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 489 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 490 | /* |
| 491 | * The loop can still results in a timing too fast for the |
| 492 | * memory controller. |
| 493 | */ |
| 494 | if (sysinfo->tclk < ctrl_min_tclk) |
| 495 | sysinfo->tclk = ctrl_min_tclk; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 496 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 497 | switch (sysinfo->tclk) { |
| 498 | case TCK_200MHZ: |
| 499 | sysinfo->memory_frequency = 400; |
| 500 | break; |
| 501 | case TCK_266MHZ: |
| 502 | sysinfo->memory_frequency = 533; |
| 503 | break; |
| 504 | case TCK_333MHZ: |
| 505 | sysinfo->memory_frequency = 667; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 506 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 507 | } |
| 508 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 509 | printk(BIOS_DEBUG, |
| 510 | "Memory will be driven at %dMT with CAS=%d clocks\n", |
| 511 | sysinfo->memory_frequency, sysinfo->cas); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 512 | } |
| 513 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 514 | static void derive_timings(struct sys_info *sysinfo, struct timings *saved_timings) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 515 | { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 516 | sysinfo->tras = DIV_ROUND_UP(saved_timings->min_tRAS, sysinfo->tclk); |
| 517 | if (sysinfo->tras > 0x18) |
| 518 | die("DDR-II Module does not support this frequency (tRAS error)\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 519 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 520 | sysinfo->trp = DIV_ROUND_UP(saved_timings->min_tRP, sysinfo->tclk); |
| 521 | if (sysinfo->trp > 6) |
| 522 | die("DDR-II Module does not support this frequency (tRP error)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 523 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 524 | sysinfo->trcd = DIV_ROUND_UP(saved_timings->min_tRCD, sysinfo->tclk); |
| 525 | if (sysinfo->trcd > 6) |
| 526 | die("DDR-II Module does not support this frequency (tRCD error)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 527 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 528 | sysinfo->twr = DIV_ROUND_UP(saved_timings->min_tWR, sysinfo->tclk); |
| 529 | if (sysinfo->twr > 5) |
| 530 | die("DDR-II Module does not support this frequency (tWR error)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 531 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 532 | sysinfo->trfc = DIV_ROUND_UP(saved_timings->min_tRFC, sysinfo->tclk); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 533 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 534 | printk(BIOS_DEBUG, "tRAS = %d cycles\n", sysinfo->tras); |
| 535 | printk(BIOS_DEBUG, "tRP = %d cycles\n", sysinfo->trp); |
| 536 | printk(BIOS_DEBUG, "tRCD = %d cycles\n", sysinfo->trcd); |
| 537 | printk(BIOS_DEBUG, "tWR = %d cycles\n", sysinfo->twr); |
| 538 | printk(BIOS_DEBUG, "tRFC = %d cycles\n", sysinfo->trfc); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 539 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 540 | /* Refresh is slower than 15.6us, use 15.6us */ |
| 541 | /* tRR is decoded in units of 1/256us */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 542 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 543 | #define T_RR_7_8US 2000000 |
| 544 | #define T_RR_15_6US 4000000 |
| 545 | #define REFRESH_7_8US 1 |
| 546 | #define REFRESH_15_6US 0 |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 547 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 548 | if (saved_timings->max_tRR < T_RR_7_8US) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 549 | die("DDR-II module has unsupported refresh value\n"); |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 550 | else if (saved_timings->max_tRR < T_RR_15_6US) |
| 551 | sysinfo->refresh = REFRESH_7_8US; |
| 552 | else |
| 553 | sysinfo->refresh = REFRESH_15_6US; |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 554 | printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh ? "7.8us" : "15.6us"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 555 | } |
| 556 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 557 | /** |
| 558 | * @brief Get generic DIMM parameters. |
| 559 | * @param sysinfo Central memory controller information structure |
| 560 | * |
| 561 | * This function gathers several pieces of information for each system DIMM: |
| 562 | * o DIMM width (x8 / x16) |
| 563 | * o DIMM rank (single ranked / dual ranked) |
| 564 | * |
| 565 | * Also, some non-supported scenarios are detected. |
| 566 | */ |
| 567 | |
| 568 | static void sdram_get_dram_configuration(struct sys_info *sysinfo) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 569 | { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 570 | struct timings saved_timings; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 571 | |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 572 | gather_common_timing(sysinfo, &saved_timings); |
| 573 | choose_tclk(sysinfo, &saved_timings); |
| 574 | derive_timings(sysinfo, &saved_timings); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 575 | } |
| 576 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 577 | static void sdram_program_dram_width(struct sys_info *sysinfo) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 578 | { |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 579 | u16 c0dramw = 0, c1dramw = 0; |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 580 | int i, idx; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 581 | |
| 582 | if (sysinfo->dual_channel) |
| 583 | idx = 2; |
| 584 | else |
| 585 | idx = 1; |
| 586 | |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 587 | for (i = 0; i < DIMM_SOCKETS; i++) { /* Channel 0 */ |
| 588 | switch (sysinfo->dimm[i]) { |
| 589 | case SYSINFO_DIMM_X16DS: |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 590 | c0dramw |= (0x0000) << 4 * (i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 591 | break; |
| 592 | case SYSINFO_DIMM_X8DS: |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 593 | c0dramw |= (0x0001) << 4 * (i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 594 | break; |
| 595 | case SYSINFO_DIMM_X16SS: |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 596 | c0dramw |= (0x0000) << 4 * (i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 597 | break; |
| 598 | case SYSINFO_DIMM_X8DDS: |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 599 | c0dramw |= (0x0005) << 4 * (i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 600 | break; |
| 601 | case SYSINFO_DIMM_NOT_POPULATED: |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 602 | c0dramw |= (0x0000) << 4 * (i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 603 | break; |
| 604 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 605 | } |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 606 | for (i = DIMM_SOCKETS; i < idx * DIMM_SOCKETS; i++) { /* Channel 1 */ |
| 607 | switch (sysinfo->dimm[i]) { |
| 608 | case SYSINFO_DIMM_X16DS: |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 609 | c1dramw |= (0x0000) << 4 * (i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 610 | break; |
| 611 | case SYSINFO_DIMM_X8DS: |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 612 | c1dramw |= (0x0010) << 4 * (i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 613 | break; |
| 614 | case SYSINFO_DIMM_X16SS: |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 615 | c1dramw |= (0x0000) << 4 * (i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 616 | break; |
| 617 | case SYSINFO_DIMM_X8DDS: |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 618 | c1dramw |= (0x0050) << 4 * (i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 619 | break; |
| 620 | case SYSINFO_DIMM_NOT_POPULATED: |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 621 | c1dramw |= (0x0000) << 4 * (i % 2); |
Elyes HAOUAS | a4fc7be | 2018-06-30 10:39:24 +0200 | [diff] [blame] | 622 | break; |
| 623 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 624 | } |
| 625 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 626 | mchbar_write16(C0DRAMW, c0dramw); |
| 627 | mchbar_write16(C1DRAMW, c1dramw); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 628 | } |
| 629 | |
| 630 | static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table) |
| 631 | { |
| 632 | int i; |
| 633 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 634 | for (i = 0; i < 16; i++) |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 635 | mchbar_write32(offset + (i * 4), slew_rate_table[i]); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 636 | } |
| 637 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 638 | static const u32 dq2030[] = { |
| 639 | 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e, |
| 640 | 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d, |
| 641 | 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f, |
| 642 | 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531 |
| 643 | }; |
| 644 | |
| 645 | static const u32 dq2330[] = { |
| 646 | 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e, |
| 647 | 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d, |
| 648 | 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f, |
| 649 | 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531 |
| 650 | }; |
| 651 | |
| 652 | static const u32 cmd2710[] = { |
| 653 | 0x07060605, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b, |
| 654 | 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, |
| 655 | 0x1110100f, 0x0f0d0b09, 0x19171411, 0x1f1f1d1b, |
| 656 | 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f |
| 657 | }; |
| 658 | |
| 659 | static const u32 cmd3210[] = { |
| 660 | 0x0f0d0b0a, 0x17151311, 0x1f1d1b19, 0x1f1f1f1f, |
| 661 | 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, |
| 662 | 0x18171615, 0x1f1f1c1a, 0x1f1f1f1f, 0x1f1f1f1f, |
| 663 | 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f, 0x1f1f1f1f |
| 664 | }; |
| 665 | |
| 666 | static const u32 clk2030[] = { |
| 667 | 0x0e0d0d0c, 0x100f0f0e, 0x100f0e0d, 0x15131211, |
| 668 | 0x1d1b1917, 0x2523211f, 0x2a282927, 0x32302e2c, |
| 669 | 0x17161514, 0x1b1a1918, 0x1f1e1d1c, 0x23222120, |
| 670 | 0x27262524, 0x2d2b2928, 0x3533312f, 0x3d3b3937 |
| 671 | }; |
| 672 | |
| 673 | static const u32 ctl3215[] = { |
| 674 | 0x01010000, 0x03020101, 0x07060504, 0x0b0a0908, |
| 675 | 0x100f0e0d, 0x14131211, 0x18171615, 0x1c1b1a19, |
| 676 | 0x05040403, 0x07060605, 0x0a090807, 0x0f0d0c0b, |
| 677 | 0x14131211, 0x18171615, 0x1c1b1a19, 0x201f1e1d |
| 678 | }; |
| 679 | |
| 680 | static const u32 ctl3220[] = { |
| 681 | 0x05040403, 0x07060505, 0x0e0c0a08, 0x1a171411, |
| 682 | 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e, |
| 683 | 0x09080807, 0x0b0a0a09, 0x0f0d0c0b, 0x1b171311, |
| 684 | 0x2825221f, 0x35322f2b, 0x3e3e3b38, 0x3e3e3e3e |
| 685 | }; |
| 686 | |
| 687 | static const u32 nc[] = { |
| 688 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 689 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 690 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 691 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 |
| 692 | }; |
| 693 | |
| 694 | enum { |
| 695 | DQ2030, |
| 696 | DQ2330, |
| 697 | CMD2710, |
| 698 | CMD3210, |
| 699 | CLK2030, |
| 700 | CTL3215, |
| 701 | CTL3220, |
| 702 | NC, |
| 703 | }; |
| 704 | |
| 705 | static const u8 dual_channel_slew_group_lookup[] = { |
| 706 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 707 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 708 | DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 709 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710, |
| 710 | DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, |
| 711 | |
| 712 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 713 | DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, |
| 714 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 715 | DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710, |
| 716 | DQ2030, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, |
| 717 | |
| 718 | DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 719 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 720 | DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 721 | DQ2030, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD2710, |
| 722 | DQ2030, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, |
| 723 | |
| 724 | DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 725 | DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, |
| 726 | DQ2030, CMD2710, CTL3215, CTL3215, CLK2030, CLK2030, DQ2030, CMD3210, |
| 727 | DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, DQ2030, CMD2710, |
| 728 | DQ2030, CMD2710, CTL3215, NC, CLK2030, NC, NC, NC, |
| 729 | |
| 730 | NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 731 | NC, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, |
| 732 | NC, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 733 | NC, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD2710 |
| 734 | }; |
| 735 | |
| 736 | static const u8 single_channel_slew_group_lookup[] = { |
| 737 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 738 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 739 | DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, |
| 740 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 741 | DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, |
| 742 | |
| 743 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 744 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, |
| 745 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 746 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, |
| 747 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, |
| 748 | |
| 749 | DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, |
| 750 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 751 | DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, DQ2330, CMD3210, |
| 752 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 753 | DQ2330, CMD3210, NC, CTL3215, NC, CLK2030, NC, NC, |
| 754 | |
| 755 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 756 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, |
| 757 | DQ2330, CMD3210, CTL3215, CTL3215, CLK2030, CLK2030, DQ2330, CMD3210, |
| 758 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, DQ2330, CMD3210, |
| 759 | DQ2330, CMD3210, CTL3215, NC, CLK2030, NC, NC, NC, |
| 760 | |
| 761 | DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 762 | DQ2330, NC, CTL3215, NC, CLK2030, NC, DQ2030, CMD3210, |
| 763 | DQ2330, NC, NC, CTL3215, NC, CLK2030, DQ2030, CMD3210, |
| 764 | DQ2330, NC, CTL3215, NC, CLK2030, CLK2030, DQ2030, CMD3210 |
| 765 | }; |
| 766 | |
| 767 | static const u32 *slew_group_lookup(int dual_channel, int index) |
| 768 | { |
| 769 | const u8 *slew_group; |
| 770 | /* Dual Channel needs different tables. */ |
| 771 | if (dual_channel) |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 772 | slew_group = dual_channel_slew_group_lookup; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 773 | else |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 774 | slew_group = single_channel_slew_group_lookup; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 775 | |
| 776 | switch (slew_group[index]) { |
| 777 | case DQ2030: return dq2030; |
| 778 | case DQ2330: return dq2330; |
| 779 | case CMD2710: return cmd2710; |
| 780 | case CMD3210: return cmd3210; |
| 781 | case CLK2030: return clk2030; |
| 782 | case CTL3215: return ctl3215; |
| 783 | case CTL3220: return ctl3220; |
| 784 | case NC: return nc; |
| 785 | } |
| 786 | |
| 787 | return nc; |
| 788 | } |
| 789 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 790 | #if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 791 | /* Strength multiplier tables */ |
| 792 | static const u8 dual_channel_strength_multiplier[] = { |
| 793 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 794 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 795 | 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, |
| 796 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, |
| 797 | 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, |
| 798 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 799 | 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, |
| 800 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 801 | 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, |
| 802 | 0x44, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, |
| 803 | 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, |
| 804 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 805 | 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, |
| 806 | 0x44, 0x11, 0x11, 0x11, 0x44, 0x44, 0x44, 0x22, |
| 807 | 0x44, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, |
| 808 | 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 809 | 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, |
| 810 | 0x44, 0x22, 0x11, 0x11, 0x44, 0x44, 0x44, 0x11, |
| 811 | 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x44, 0x22, |
| 812 | 0x44, 0x22, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, |
| 813 | 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, |
| 814 | 0x00, 0x00, 0x11, 0x00, 0x44, 0x00, 0x44, 0x11, |
| 815 | 0x00, 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x11, |
| 816 | 0x00, 0x00, 0x11, 0x00, 0x44, 0x44, 0x44, 0x22 |
| 817 | }; |
| 818 | |
| 819 | static const u8 single_channel_strength_multiplier[] = { |
| 820 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 821 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 822 | 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, |
| 823 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 824 | 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, |
| 825 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 826 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, |
| 827 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 828 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, |
| 829 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, |
| 830 | 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, |
| 831 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 832 | 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, |
| 833 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 834 | 0x33, 0x11, 0x00, 0x11, 0x00, 0x44, 0x00, 0x00, |
| 835 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 836 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, |
| 837 | 0x33, 0x11, 0x11, 0x11, 0x44, 0x44, 0x33, 0x11, |
| 838 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, |
| 839 | 0x33, 0x11, 0x11, 0x00, 0x44, 0x00, 0x00, 0x00, |
| 840 | 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, |
| 841 | 0x33, 0x00, 0x11, 0x00, 0x44, 0x00, 0x33, 0x11, |
| 842 | 0x33, 0x00, 0x00, 0x11, 0x00, 0x44, 0x33, 0x11, |
| 843 | 0x33, 0x00, 0x11, 0x00, 0x44, 0x44, 0x33, 0x11 |
| 844 | }; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 845 | #elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 846 | static const u8 dual_channel_strength_multiplier[] = { |
| 847 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 848 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 849 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 850 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, |
| 851 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 852 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 853 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 854 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 855 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, |
| 856 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 857 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 858 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 859 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 860 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, |
| 861 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 862 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 863 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 864 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 865 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33, |
| 866 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 867 | 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 868 | 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 869 | 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x22, |
| 870 | 0x44, 0x00, 0x00, 0x00, 0x44, 0x44, 0x44, 0x33 |
| 871 | }; |
| 872 | |
| 873 | static const u8 single_channel_strength_multiplier[] = { |
| 874 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 875 | 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 876 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 877 | 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 878 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 879 | 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 880 | 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 881 | 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 882 | 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 883 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 884 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 885 | 0x44, 0x44, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 886 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 887 | 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 888 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 889 | 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 890 | 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 891 | 0x44, 0x55, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 892 | 0x44, 0x88, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 893 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 894 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 895 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 896 | 0x44, 0x22, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00, |
| 897 | 0x44, 0x33, 0x00, 0x00, 0x44, 0x44, 0x44, 0x00 |
| 898 | }; |
| 899 | #endif |
| 900 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 901 | static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo) |
| 902 | { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 903 | const u8 *strength_multiplier; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 904 | int idx, dual_channel; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 905 | |
| 906 | /* Set Strength Multipliers */ |
| 907 | |
| 908 | /* Dual Channel needs different tables. */ |
| 909 | if (sdram_capabilities_dual_channel()) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 910 | printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 911 | strength_multiplier = dual_channel_strength_multiplier; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 912 | dual_channel = 1; |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 913 | idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[2]; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 914 | } else { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 915 | printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 916 | strength_multiplier = single_channel_strength_multiplier; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 917 | dual_channel = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 918 | idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1]; |
| 919 | } |
| 920 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 921 | printk(BIOS_DEBUG, "Table Index: %d\n", idx); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 922 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 923 | mchbar_write8(G1SC, strength_multiplier[idx * 8 + 0]); |
| 924 | mchbar_write8(G2SC, strength_multiplier[idx * 8 + 1]); |
| 925 | mchbar_write8(G3SC, strength_multiplier[idx * 8 + 2]); |
| 926 | mchbar_write8(G4SC, strength_multiplier[idx * 8 + 3]); |
| 927 | mchbar_write8(G5SC, strength_multiplier[idx * 8 + 4]); |
| 928 | mchbar_write8(G6SC, strength_multiplier[idx * 8 + 5]); |
| 929 | mchbar_write8(G7SC, strength_multiplier[idx * 8 + 6]); |
| 930 | mchbar_write8(G8SC, strength_multiplier[idx * 8 + 7]); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 931 | |
| 932 | /* Channel 0 */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 933 | sdram_write_slew_rates(G1SRPUT, slew_group_lookup(dual_channel, idx * 8 + 0)); |
| 934 | sdram_write_slew_rates(G2SRPUT, slew_group_lookup(dual_channel, idx * 8 + 1)); |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 935 | if ((slew_group_lookup(dual_channel, idx * 8 + 2) != nc) && |
| 936 | (sysinfo->package == SYSINFO_PACKAGE_STACKED)) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 937 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 938 | sdram_write_slew_rates(G3SRPUT, ctl3220); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 939 | else |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 940 | sdram_write_slew_rates(G3SRPUT, slew_group_lookup(dual_channel, idx * 8 + 2)); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 941 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 942 | sdram_write_slew_rates(G4SRPUT, slew_group_lookup(dual_channel, idx * 8 + 3)); |
| 943 | sdram_write_slew_rates(G5SRPUT, slew_group_lookup(dual_channel, idx * 8 + 4)); |
| 944 | sdram_write_slew_rates(G6SRPUT, slew_group_lookup(dual_channel, idx * 8 + 5)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 945 | |
| 946 | /* Channel 1 */ |
| 947 | if (sysinfo->dual_channel) { |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 948 | sdram_write_slew_rates(G7SRPUT, slew_group_lookup(dual_channel, idx * 8 + 6)); |
| 949 | sdram_write_slew_rates(G8SRPUT, slew_group_lookup(dual_channel, idx * 8 + 7)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 950 | } else { |
| 951 | sdram_write_slew_rates(G7SRPUT, nc); |
| 952 | sdram_write_slew_rates(G8SRPUT, nc); |
| 953 | } |
| 954 | } |
| 955 | |
| 956 | static void sdram_enable_rcomp(void) |
| 957 | { |
| 958 | u32 reg32; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 959 | /* Enable Global Periodic RCOMP */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 960 | udelay(300); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 961 | reg32 = mchbar_read32(GBRCOMPCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 962 | reg32 &= ~(1 << 23); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 963 | mchbar_write32(GBRCOMPCTL, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 964 | } |
| 965 | |
| 966 | static void sdram_program_dll_timings(struct sys_info *sysinfo) |
| 967 | { |
Elyes HAOUAS | 44a3066 | 2017-02-23 13:14:44 +0100 | [diff] [blame] | 968 | u32 channeldll = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 969 | int i; |
| 970 | |
Elyes HAOUAS | 3842498 | 2016-08-21 12:01:04 +0200 | [diff] [blame] | 971 | printk(BIOS_DEBUG, "Programming DLL Timings...\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 972 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 973 | mchbar_clrbits16(DQSMT, 3 << 12 | 1 << 10 | 0xf << 0); |
| 974 | mchbar_setbits16(DQSMT, 1 << 13 | 0xc << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 975 | |
| 976 | /* We drive both channels with the same speed */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 977 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { |
Elyes HAOUAS | 39bfc6c | 2016-10-31 10:49:33 +0100 | [diff] [blame] | 978 | switch (sysinfo->memory_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 979 | case 400: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 980 | channeldll = 0x26262626; |
| 981 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 982 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 983 | channeldll = 0x22222222; |
| 984 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 985 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 986 | channeldll = 0x11111111; |
| 987 | break; |
Elyes HAOUAS | 39bfc6c | 2016-10-31 10:49:33 +0100 | [diff] [blame] | 988 | } |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 989 | } else if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Elyes HAOUAS | 39bfc6c | 2016-10-31 10:49:33 +0100 | [diff] [blame] | 990 | switch (sysinfo->memory_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 991 | case 400: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 992 | channeldll = 0x33333333; |
| 993 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 994 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 995 | channeldll = 0x24242424; |
| 996 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 997 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 998 | channeldll = 0x25252525; |
| 999 | break; |
Elyes HAOUAS | 39bfc6c | 2016-10-31 10:49:33 +0100 | [diff] [blame] | 1000 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1001 | } |
| 1002 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1003 | for (i = 0; i < 4; i++) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1004 | mchbar_write32(C0R0B00DQST + (i * 0x10) + 0, channeldll); |
| 1005 | mchbar_write32(C0R0B00DQST + (i * 0x10) + 4, channeldll); |
| 1006 | mchbar_write32(C1R0B00DQST + (i * 0x10) + 0, channeldll); |
| 1007 | mchbar_write32(C1R0B00DQST + (i * 0x10) + 4, channeldll); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1008 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1009 | mchbar_write8(C0R0B00DQST + (i * 0x10) + 8, channeldll & 0xff); |
| 1010 | mchbar_write8(C1R0B00DQST + (i * 0x10) + 8, channeldll & 0xff); |
Paul Menzel | bce7e33 | 2017-02-22 18:46:27 +0100 | [diff] [blame] | 1011 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1012 | } |
| 1013 | } |
| 1014 | |
| 1015 | static void sdram_force_rcomp(void) |
| 1016 | { |
| 1017 | u32 reg32; |
| 1018 | u8 reg8; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1019 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1020 | reg32 = mchbar_read32(ODTC); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1021 | reg32 |= (1 << 28); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1022 | mchbar_write32(ODTC, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1023 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1024 | reg32 = mchbar_read32(SMSRCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1025 | reg32 |= (1 << 0); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1026 | mchbar_write32(SMSRCTL, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1027 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1028 | /* Start initial RCOMP */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1029 | reg32 = mchbar_read32(GBRCOMPCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1030 | reg32 |= (1 << 8); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1031 | mchbar_write32(GBRCOMPCTL, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1032 | |
| 1033 | reg8 = i945_silicon_revision(); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1034 | if ((reg8 == 0 && (mchbar_read32(DCC) & (3 << 0)) == 0) || (reg8 == 1)) { |
| 1035 | reg32 = mchbar_read32(GBRCOMPCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1036 | reg32 |= (3 << 5); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1037 | mchbar_write32(GBRCOMPCTL, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1038 | } |
| 1039 | } |
| 1040 | |
| 1041 | static void sdram_initialize_system_memory_io(struct sys_info *sysinfo) |
| 1042 | { |
| 1043 | u8 reg8; |
| 1044 | u32 reg32; |
| 1045 | |
Elyes HAOUAS | 3842498 | 2016-08-21 12:01:04 +0200 | [diff] [blame] | 1046 | printk(BIOS_DEBUG, "Initializing System Memory IO...\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1047 | /* Enable Data Half Clock Pushout */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1048 | reg8 = mchbar_read8(C0HCTC); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1049 | reg8 &= ~0x1f; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1050 | reg8 |= (1 << 0); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1051 | mchbar_write8(C0HCTC, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1052 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1053 | reg8 = mchbar_read8(C1HCTC); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1054 | reg8 &= ~0x1f; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1055 | reg8 |= (1 << 0); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1056 | mchbar_write8(C1HCTC, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1057 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1058 | mchbar_clrbits16(WDLLBYPMODE, 1 << 9 | 1 << 6 | 1 << 4 | 1 << 3 | 1 << 1); |
| 1059 | mchbar_setbits16(WDLLBYPMODE, 1 << 8 | 1 << 7 | 1 << 5 | 1 << 2 | 1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1060 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1061 | mchbar_write8(C0WDLLCMC, 0); |
| 1062 | mchbar_write8(C1WDLLCMC, 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1063 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1064 | /* Program RCOMP Settings */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1065 | sdram_program_dram_width(sysinfo); |
| 1066 | |
| 1067 | sdram_rcomp_buffer_strength_and_slew(sysinfo); |
| 1068 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1069 | /* Indicate that RCOMP programming is done */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1070 | reg32 = mchbar_read32(GBRCOMPCTL); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1071 | reg32 &= ~((1 << 29) | (1 << 26) | (3 << 21) | (3 << 2)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1072 | reg32 |= (3 << 27) | (3 << 0); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1073 | mchbar_write32(GBRCOMPCTL, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1074 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1075 | mchbar_setbits32(GBRCOMPCTL, 1 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1076 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1077 | /* Program DLL Timings */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1078 | sdram_program_dll_timings(sysinfo); |
| 1079 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1080 | /* Force RCOMP cycle */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1081 | sdram_force_rcomp(); |
| 1082 | } |
| 1083 | |
| 1084 | static void sdram_enable_system_memory_io(struct sys_info *sysinfo) |
| 1085 | { |
| 1086 | u32 reg32; |
| 1087 | |
Elyes HAOUAS | 3842498 | 2016-08-21 12:01:04 +0200 | [diff] [blame] | 1088 | printk(BIOS_DEBUG, "Enabling System Memory IO...\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1089 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1090 | reg32 = mchbar_read32(RCVENMT); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1091 | reg32 &= ~(0x3f << 6); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1092 | mchbar_write32(RCVENMT, reg32); /* [11:6] = 0 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1093 | |
| 1094 | reg32 |= (1 << 11) | (1 << 9); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1095 | mchbar_write32(RCVENMT, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1096 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1097 | reg32 = mchbar_read32(DRTST); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1098 | reg32 |= (1 << 3) | (1 << 2); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1099 | mchbar_write32(DRTST, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1100 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1101 | reg32 = mchbar_read32(DRTST); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1102 | reg32 |= (1 << 6) | (1 << 4); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1103 | mchbar_write32(DRTST, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1104 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1105 | asm volatile ("nop; nop;" ::: "memory"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1106 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1107 | reg32 = mchbar_read32(DRTST); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1108 | |
| 1109 | /* Is channel 0 populated? */ |
| 1110 | if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1111 | sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1112 | reg32 |= (1 << 7) | (1 << 5); |
| 1113 | else |
| 1114 | reg32 |= (1 << 31); |
| 1115 | |
| 1116 | /* Is channel 1 populated? */ |
| 1117 | if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1118 | sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1119 | reg32 |= (1 << 9) | (1 << 8); |
| 1120 | else |
| 1121 | reg32 |= (1 << 30); |
| 1122 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1123 | mchbar_write32(DRTST, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1124 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1125 | /* Activate DRAM Channel IO Buffers */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1126 | if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1127 | sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1128 | reg32 = mchbar_read32(C0DRC1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1129 | reg32 |= (1 << 8); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1130 | mchbar_write32(C0DRC1, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1131 | } |
| 1132 | if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1133 | sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1134 | reg32 = mchbar_read32(C1DRC1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1135 | reg32 |= (1 << 8); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1136 | mchbar_write32(C1DRC1, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1137 | } |
| 1138 | } |
| 1139 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1140 | static int sdram_program_row_boundaries(struct sys_info *sysinfo) |
| 1141 | { |
| 1142 | int i; |
Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 1143 | int cum0, cum1, tolud, tom, pci_mmio_size; |
| 1144 | const struct device *dev; |
| 1145 | const struct northbridge_intel_i945_config *cfg = NULL; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1146 | |
Paul Menzel | 84283bc | 2014-07-17 08:16:04 +0200 | [diff] [blame] | 1147 | printk(BIOS_DEBUG, "Setting RAM size...\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1148 | |
| 1149 | cum0 = 0; |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 1150 | for (i = 0; i < 2 * DIMM_SOCKETS; i++) { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1151 | cum0 += sysinfo->banksize[i]; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1152 | mchbar_write8(C0DRB0 + i, cum0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1153 | } |
| 1154 | |
| 1155 | /* Assume we continue in Channel 1 where we stopped in Channel 0 */ |
| 1156 | cum1 = cum0; |
| 1157 | |
| 1158 | /* Exception: Interleaved starts from the beginning */ |
| 1159 | if (sysinfo->interleaved) |
| 1160 | cum1 = 0; |
| 1161 | |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 1162 | for (i = 0; i < 2 * DIMM_SOCKETS; i++) { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1163 | cum1 += sysinfo->banksize[i + 4]; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1164 | mchbar_write8(C1DRB0 + i, cum1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1165 | } |
| 1166 | |
| 1167 | /* Set TOLUD Top Of Low Usable DRAM */ |
| 1168 | if (sysinfo->interleaved) |
| 1169 | tolud = (cum0 + cum1) << 1; |
| 1170 | else |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1171 | tolud = (cum1 ? cum1 : cum0) << 1; |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 1172 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1173 | /* The TOM register has a different format */ |
| 1174 | tom = tolud >> 3; |
| 1175 | |
| 1176 | /* Limit the value of TOLUD to leave some space for PCI memory. */ |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 1177 | dev = pcidev_on_root(0, 0); |
Arthur Heymans | 885c289 | 2016-10-03 17:16:48 +0200 | [diff] [blame] | 1178 | if (dev) |
| 1179 | cfg = dev->chip_info; |
| 1180 | |
| 1181 | /* Don't use pci mmio sizes smaller than 768M */ |
| 1182 | if (!cfg || cfg->pci_mmio_size <= DEFAULT_PCI_MMIO_SIZE) |
| 1183 | pci_mmio_size = DEFAULT_PCI_MMIO_SIZE; |
| 1184 | else |
| 1185 | pci_mmio_size = cfg->pci_mmio_size; |
| 1186 | |
| 1187 | tolud = MIN(((4096 - pci_mmio_size) / 128) << 3, tolud); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1188 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1189 | pci_write_config8(HOST_BRIDGE, TOLUD, tolud); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1190 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1191 | printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", mchbar_read32(C0DRB0)); |
| 1192 | printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", mchbar_read32(C1DRB0)); |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1193 | printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(HOST_BRIDGE, TOLUD)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1194 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1195 | pci_write_config16(HOST_BRIDGE, TOM, tom); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1196 | |
| 1197 | return 0; |
| 1198 | } |
| 1199 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1200 | static int sdram_set_row_attributes(struct sys_info *sysinfo) |
| 1201 | { |
Arthur Heymans | 0ab4904 | 2017-02-06 22:40:14 +0100 | [diff] [blame] | 1202 | int i; |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1203 | u16 dra0 = 0, dra1 = 0, dra = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1204 | |
Elyes HAOUAS | 3842498 | 2016-08-21 12:01:04 +0200 | [diff] [blame] | 1205 | printk(BIOS_DEBUG, "Setting row attributes...\n"); |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1206 | for (i = 0; i < 2 * DIMM_SOCKETS; i++) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1207 | u8 columnsrows; |
| 1208 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1209 | if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1210 | continue; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1211 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1212 | columnsrows = (sysinfo->rows[i] & 0x0f) | (sysinfo->cols[i] & 0xf) << 4; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1213 | |
| 1214 | switch (columnsrows) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1215 | case 0x9d: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1216 | dra = 2; |
| 1217 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1218 | case 0xad: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1219 | dra = 3; |
| 1220 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1221 | case 0xbd: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1222 | dra = 4; |
| 1223 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1224 | case 0xae: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1225 | dra = 3; |
| 1226 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1227 | case 0xbe: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1228 | dra = 4; |
| 1229 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1230 | default: |
| 1231 | die("Unsupported Rows/Columns. (DRA)"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1232 | } |
| 1233 | |
| 1234 | /* Double Sided DIMMs? */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1235 | if (sysinfo->banksize[(2 * i) + 1] != 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1236 | dra = (dra << 4) | dra; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1237 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1238 | if (i < DIMM_SOCKETS) |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 1239 | dra0 |= (dra << (i * 8)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1240 | else |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 1241 | dra1 |= (dra << ((i - DIMM_SOCKETS) * 8)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1242 | } |
| 1243 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1244 | mchbar_write16(C0DRA0, dra0); |
| 1245 | mchbar_write16(C1DRA0, dra1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1246 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1247 | printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0); |
| 1248 | printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1249 | |
| 1250 | return 0; |
| 1251 | } |
| 1252 | |
| 1253 | static void sdram_set_bank_architecture(struct sys_info *sysinfo) |
| 1254 | { |
| 1255 | u32 off32; |
| 1256 | int i; |
| 1257 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1258 | mchbar_clrbits16(C1BNKARC, 0xff); |
| 1259 | mchbar_clrbits16(C0BNKARC, 0xff); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1260 | |
| 1261 | off32 = C0BNKARC; |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1262 | for (i = 0; i < 2 * DIMM_SOCKETS; i++) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1263 | /* Switch to second channel */ |
| 1264 | if (i == DIMM_SOCKETS) |
| 1265 | off32 = C1BNKARC; |
| 1266 | |
| 1267 | if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) |
| 1268 | continue; |
| 1269 | |
| 1270 | if (sysinfo->banks[i] != 8) |
| 1271 | continue; |
| 1272 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1273 | printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1274 | |
| 1275 | if (i & 1) |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1276 | mchbar_setbits16(off32, 5 << 4); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1277 | else |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1278 | mchbar_setbits16(off32, 5 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1279 | } |
| 1280 | } |
| 1281 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1282 | static void sdram_program_refresh_rate(struct sys_info *sysinfo) |
| 1283 | { |
| 1284 | u32 reg32; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1285 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1286 | if (sysinfo->refresh == REFRESH_7_8US) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1287 | reg32 = (2 << 8); /* Refresh enabled at 7.8us */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1288 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1289 | reg32 = (1 << 8); /* Refresh enabled at 15.6us */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1290 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1291 | mchbar_clrbits32(C0DRC0, 7 << 8); |
| 1292 | mchbar_setbits32(C0DRC0, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1293 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1294 | mchbar_clrbits32(C1DRC0, 7 << 8); |
| 1295 | mchbar_setbits32(C1DRC0, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1296 | } |
| 1297 | |
| 1298 | static void sdram_program_cke_tristate(struct sys_info *sysinfo) |
| 1299 | { |
| 1300 | u32 reg32; |
| 1301 | int i; |
| 1302 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1303 | reg32 = mchbar_read32(C0DRC1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1304 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1305 | for (i = 0; i < 4; i++) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1306 | if (sysinfo->banksize[i] == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1307 | reg32 |= (1 << (16 + i)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1308 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1309 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1310 | reg32 |= (1 << 12); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1311 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1312 | reg32 |= (1 << 11); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1313 | mchbar_write32(C0DRC1, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1314 | |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1315 | /* Do we have to do this if we're in Single Channel Mode? */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1316 | reg32 = mchbar_read32(C1DRC1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1317 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1318 | for (i = 4; i < 8; i++) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1319 | if (sysinfo->banksize[i] == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1320 | reg32 |= (1 << (12 + i)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1321 | } |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1322 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1323 | reg32 |= (1 << 12); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1324 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1325 | reg32 |= (1 << 11); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1326 | mchbar_write32(C1DRC1, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1327 | } |
| 1328 | |
| 1329 | static void sdram_program_odt_tristate(struct sys_info *sysinfo) |
| 1330 | { |
| 1331 | u32 reg32; |
| 1332 | int i; |
| 1333 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1334 | reg32 = mchbar_read32(C0DRC2); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1335 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1336 | for (i = 0; i < 4; i++) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1337 | if (sysinfo->banksize[i] == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1338 | reg32 |= (1 << (24 + i)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1339 | } |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1340 | mchbar_write32(C0DRC2, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1341 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1342 | reg32 = mchbar_read32(C1DRC2); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1343 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1344 | for (i = 4; i < 8; i++) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1345 | if (sysinfo->banksize[i] == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1346 | reg32 |= (1 << (20 + i)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1347 | } |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1348 | mchbar_write32(C1DRC2, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1349 | } |
| 1350 | |
| 1351 | static void sdram_set_timing_and_control(struct sys_info *sysinfo) |
| 1352 | { |
Arthur Heymans | 2502723 | 2017-02-12 23:34:39 +0100 | [diff] [blame] | 1353 | u32 reg32, tRD_min; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1354 | u32 tWTR; |
| 1355 | u32 temp_drt; |
| 1356 | int i, page_size; |
| 1357 | |
Edward O'Callaghan | 2f237c1 | 2014-05-25 06:24:39 +1000 | [diff] [blame] | 1358 | static const u8 cas_table[] = { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1359 | 2, 1, 0, 3 |
| 1360 | }; |
| 1361 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1362 | reg32 = mchbar_read32(C0DRC0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1363 | reg32 |= (1 << 2); /* Burst Length 8 */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1364 | reg32 &= ~((1 << 13) | (1 << 12)); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1365 | mchbar_write32(C0DRC0, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1366 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1367 | reg32 = mchbar_read32(C1DRC0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1368 | reg32 |= (1 << 2); /* Burst Length 8 */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1369 | reg32 &= ~((1 << 13) | (1 << 12)); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1370 | mchbar_write32(C1DRC0, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1371 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1372 | if (!sysinfo->dual_channel && sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1373 | reg32 = mchbar_read32(C0DRC0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1374 | reg32 |= (1 << 15); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1375 | mchbar_write32(C0DRC0, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1376 | } |
| 1377 | |
| 1378 | sdram_program_refresh_rate(sysinfo); |
| 1379 | |
| 1380 | sdram_program_cke_tristate(sysinfo); |
| 1381 | |
| 1382 | sdram_program_odt_tristate(sysinfo); |
| 1383 | |
| 1384 | /* Calculate DRT0 */ |
| 1385 | |
| 1386 | temp_drt = 0; |
| 1387 | |
| 1388 | /* B2B Write Precharge (same bank) = CL-1 + BL/2 + tWR */ |
| 1389 | reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + sysinfo->twr; |
| 1390 | temp_drt |= (reg32 << 28); |
| 1391 | |
| 1392 | /* Write Auto Precharge (same bank) = CL-1 + BL/2 + tWR + tRP */ |
| 1393 | reg32 += sysinfo->trp; |
| 1394 | temp_drt |= (reg32 << 4); |
| 1395 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1396 | if (sysinfo->memory_frequency == 667) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1397 | tWTR = 3; /* 667MHz */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1398 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1399 | tWTR = 2; /* 400 and 533 */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1400 | |
| 1401 | /* B2B Write to Read Command Spacing */ |
| 1402 | reg32 = (sysinfo->cas - 1) + (BURSTLENGTH / 2) + tWTR; |
| 1403 | temp_drt |= (reg32 << 24); |
| 1404 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1405 | /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1406 | temp_drt |= ((1 << 22) | (3 << 20) | (1 << 18) | (0 << 16)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1407 | |
Arthur Heymans | 2502723 | 2017-02-12 23:34:39 +0100 | [diff] [blame] | 1408 | /* |
| 1409 | * tRD is the delay the memory controller is waiting on the FSB, |
| 1410 | * in mclk domain. |
| 1411 | * This parameter is important for stability and performance. |
| 1412 | * Those values might not be optimal but seem stable. |
| 1413 | */ |
| 1414 | tRD_min = sysinfo->cas; |
Arthur Heymans | e189761 | 2016-10-15 23:29:18 +0200 | [diff] [blame] | 1415 | switch (sysinfo->fsb_frequency) { |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1416 | case 533: |
Arthur Heymans | e189761 | 2016-10-15 23:29:18 +0200 | [diff] [blame] | 1417 | break; |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1418 | case 667: |
| 1419 | tRD_min += 1; |
Arthur Heymans | e189761 | 2016-10-15 23:29:18 +0200 | [diff] [blame] | 1420 | break; |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1421 | case 800: |
| 1422 | tRD_min += 2; |
| 1423 | break; |
| 1424 | case 1066: |
| 1425 | tRD_min += 3; |
Arthur Heymans | e189761 | 2016-10-15 23:29:18 +0200 | [diff] [blame] | 1426 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1427 | } |
Arthur Heymans | e189761 | 2016-10-15 23:29:18 +0200 | [diff] [blame] | 1428 | |
Arthur Heymans | 2502723 | 2017-02-12 23:34:39 +0100 | [diff] [blame] | 1429 | temp_drt |= (tRD_min << 11); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1430 | |
| 1431 | /* Read Auto Precharge to Activate */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1432 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1433 | temp_drt |= (8 << 0); |
| 1434 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1435 | mchbar_write32(C0DRT0, temp_drt); |
| 1436 | mchbar_write32(C1DRT0, temp_drt); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1437 | |
| 1438 | /* Calculate DRT1 */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1439 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1440 | temp_drt = mchbar_read32(C0DRT1) & 0x00020088; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1441 | |
| 1442 | /* DRAM RASB Precharge */ |
| 1443 | temp_drt |= (sysinfo->trp - 2) << 0; |
| 1444 | |
| 1445 | /* DRAM RASB to CASB Delay */ |
| 1446 | temp_drt |= (sysinfo->trcd - 2) << 4; |
| 1447 | |
| 1448 | /* CASB Latency */ |
| 1449 | temp_drt |= (cas_table[sysinfo->cas - 3]) << 8; |
| 1450 | |
| 1451 | /* Refresh Cycle Time */ |
| 1452 | temp_drt |= (sysinfo->trfc) << 10; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1453 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1454 | /* Pre-All to Activate Delay */ |
| 1455 | temp_drt |= (0 << 16); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1456 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1457 | /* Precharge to Precharge Delay stays at 1 clock */ |
| 1458 | temp_drt |= (0 << 18); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1459 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1460 | /* Activate to Precharge Delay */ |
| 1461 | temp_drt |= (sysinfo->tras << 19); |
| 1462 | |
| 1463 | /* Read to Precharge (tRTP) */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1464 | if (sysinfo->memory_frequency == 667) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1465 | temp_drt |= (1 << 28); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1466 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1467 | temp_drt |= (0 << 28); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1468 | |
| 1469 | /* Determine page size */ |
| 1470 | reg32 = 0; |
| 1471 | page_size = 1; /* Default: 1k pagesize */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1472 | for (i = 0; i < 2*DIMM_SOCKETS; i++) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1473 | if (sysinfo->dimm[i] == SYSINFO_DIMM_X16DS || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1474 | sysinfo->dimm[i] == SYSINFO_DIMM_X16SS) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1475 | page_size = 2; /* 2k pagesize */ |
| 1476 | } |
| 1477 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1478 | if (sysinfo->memory_frequency == 533 && page_size == 2) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1479 | reg32 = 1; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1480 | if (sysinfo->memory_frequency == 667) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1481 | reg32 = page_size; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1482 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1483 | temp_drt |= (reg32 << 30); |
| 1484 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1485 | mchbar_write32(C0DRT1, temp_drt); |
| 1486 | mchbar_write32(C1DRT1, temp_drt); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1487 | |
| 1488 | /* Program DRT2 */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1489 | reg32 = mchbar_read32(C0DRT2); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1490 | reg32 &= ~(1 << 8); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1491 | mchbar_write32(C0DRT2, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1492 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1493 | reg32 = mchbar_read32(C1DRT2); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1494 | reg32 &= ~(1 << 8); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1495 | mchbar_write32(C1DRT2, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1496 | |
| 1497 | /* Calculate DRT3 */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1498 | temp_drt = mchbar_read32(C0DRT3) & ~0x07ffffff; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1499 | |
| 1500 | /* Get old tRFC value */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1501 | reg32 = mchbar_read32(C0DRT1) >> 10; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1502 | reg32 &= 0x3f; |
| 1503 | |
| 1504 | /* 788nS - tRFC */ |
| 1505 | switch (sysinfo->memory_frequency) { |
| 1506 | case 400: /* 5nS */ |
| 1507 | reg32 = ((78800 / 500) - reg32) & 0x1ff; |
| 1508 | reg32 |= (0x8c << 16) | (0x0c << 10); /* 1 us */ |
| 1509 | break; |
| 1510 | case 533: /* 3.75nS */ |
| 1511 | reg32 = ((78800 / 375) - reg32) & 0x1ff; |
| 1512 | reg32 |= (0xba << 16) | (0x10 << 10); /* 1 us */ |
| 1513 | break; |
| 1514 | case 667: /* 3nS */ |
| 1515 | reg32 = ((78800 / 300) - reg32) & 0x1ff; |
| 1516 | reg32 |= (0xe9 << 16) | (0x14 << 10); /* 1 us */ |
| 1517 | break; |
| 1518 | } |
| 1519 | |
| 1520 | temp_drt |= reg32; |
| 1521 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1522 | mchbar_write32(C0DRT3, temp_drt); |
| 1523 | mchbar_write32(C1DRT3, temp_drt); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1524 | } |
| 1525 | |
| 1526 | static void sdram_set_channel_mode(struct sys_info *sysinfo) |
| 1527 | { |
| 1528 | u32 reg32; |
| 1529 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1530 | printk(BIOS_DEBUG, "Setting mode of operation for memory channels..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1531 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1532 | if (sdram_capabilities_interleave() && |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1533 | ((sysinfo->banksize[0] + sysinfo->banksize[1] + |
| 1534 | sysinfo->banksize[2] + sysinfo->banksize[3]) == |
| 1535 | (sysinfo->banksize[4] + sysinfo->banksize[5] + |
| 1536 | sysinfo->banksize[6] + sysinfo->banksize[7]))) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1537 | /* Both channels equipped with DIMMs of the same size */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1538 | sysinfo->interleaved = 1; |
| 1539 | } else { |
| 1540 | sysinfo->interleaved = 0; |
| 1541 | } |
| 1542 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1543 | reg32 = mchbar_read32(DCC); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1544 | reg32 &= ~(7 << 0); |
| 1545 | |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 1546 | if (sysinfo->interleaved) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1547 | /* Dual Channel Interleaved */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1548 | printk(BIOS_DEBUG, "Dual Channel Interleaved.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1549 | reg32 |= (1 << 1); |
| 1550 | } else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED && |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1551 | sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1552 | /* Channel 1 only */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1553 | printk(BIOS_DEBUG, "Single Channel 1 only.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1554 | reg32 |= (1 << 2); |
Elyes HAOUAS | 75da1fb | 2017-02-16 18:59:13 +0100 | [diff] [blame] | 1555 | } else if (sdram_capabilities_dual_channel() && |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1556 | (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || |
| 1557 | sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) { |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 1558 | /* Dual Channel Asymmetric */ |
| 1559 | printk(BIOS_DEBUG, "Dual Channel Asymmetric.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1560 | reg32 |= (1 << 0); |
| 1561 | } else { |
| 1562 | /* All bits 0 means Single Channel 0 operation */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1563 | printk(BIOS_DEBUG, "Single Channel 0 only.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1564 | } |
| 1565 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1566 | /* Now disable channel XORing */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1567 | reg32 |= (1 << 10); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1568 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1569 | mchbar_write32(DCC, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1570 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1571 | PRINTK_DEBUG("DCC = 0x%08x\n", mchbar_read32(DCC)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1572 | } |
| 1573 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1574 | static void sdram_program_pll_settings(struct sys_info *sysinfo) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1575 | { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1576 | mchbar_write32(PLLMON, 0x80800000); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1577 | |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1578 | sysinfo->fsb_frequency = fsbclk(); |
Peter Stuge | 76d9143 | 2010-10-01 10:02:33 +0000 | [diff] [blame] | 1579 | if (sysinfo->fsb_frequency == 0xffff) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1580 | die("Unsupported FSB speed"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1581 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1582 | /* Program CPCTL according to FSB speed */ |
| 1583 | /* Only write the lower byte */ |
| 1584 | switch (sysinfo->fsb_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1585 | case 400: |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1586 | mchbar_write8(CPCTL, 0x90); |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1587 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1588 | case 533: |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1589 | mchbar_write8(CPCTL, 0x95); |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1590 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1591 | case 667: |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1592 | mchbar_write8(CPCTL, 0x8d); |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1593 | break; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1594 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1595 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1596 | mchbar_clrbits16(CPCTL, 1 << 11); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1597 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1598 | mchbar_read16(CPCTL); /* Read back register to activate settings */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1599 | } |
| 1600 | |
| 1601 | static void sdram_program_graphics_frequency(struct sys_info *sysinfo) |
| 1602 | { |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1603 | u8 reg8; |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1604 | u8 freq, second_vco, voltage; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1605 | |
| 1606 | #define CRCLK_166MHz 0x00 |
| 1607 | #define CRCLK_200MHz 0x01 |
| 1608 | #define CRCLK_250MHz 0x03 |
| 1609 | #define CRCLK_400MHz 0x05 |
| 1610 | |
| 1611 | #define CDCLK_200MHz 0x00 |
| 1612 | #define CDCLK_320MHz 0x40 |
| 1613 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1614 | #define VOLTAGE_1_05 0x00 |
| 1615 | #define VOLTAGE_1_50 0x01 |
| 1616 | |
Paul Menzel | daf9e50 | 2014-07-15 23:49:16 +0200 | [diff] [blame] | 1617 | printk(BIOS_DEBUG, "Setting Graphics Frequency...\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1618 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1619 | printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1620 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1621 | voltage = VOLTAGE_1_05; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1622 | if (mchbar_read32(DFT_STRAP1) & (1 << 20)) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1623 | voltage = VOLTAGE_1_50; |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 1624 | printk(BIOS_DEBUG, "Voltage: %s ", (voltage == VOLTAGE_1_05) ? "1.05V" : "1.5V"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1625 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1626 | /* Gate graphics hardware for frequency change */ |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 1627 | reg8 = (1 << 3) | (1 << 1); /* disable crclk, gate cdclk */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1628 | pci_write_config8(IGD_DEV, GCFC + 1, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1629 | |
| 1630 | /* Get graphics frequency capabilities */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1631 | reg8 = sdram_capabilities_core_frequencies(); |
| 1632 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1633 | freq = CRCLK_250MHz; |
| 1634 | switch (reg8) { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1635 | case GFX_FREQUENCY_CAP_ALL: |
| 1636 | if (voltage == VOLTAGE_1_05) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1637 | freq = CRCLK_250MHz; |
| 1638 | else |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1639 | freq = CRCLK_400MHz; /* 1.5V requires 400MHz */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1640 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1641 | case GFX_FREQUENCY_CAP_250MHZ: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1642 | freq = CRCLK_250MHz; |
| 1643 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1644 | case GFX_FREQUENCY_CAP_200MHZ: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1645 | freq = CRCLK_200MHz; |
| 1646 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1647 | case GFX_FREQUENCY_CAP_166MHZ: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1648 | freq = CRCLK_166MHz; |
| 1649 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1650 | } |
| 1651 | |
| 1652 | if (freq != CRCLK_400MHz) { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1653 | /* What chipset are we? Force 166MHz for GMS */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1654 | reg8 = (pci_read_config8(HOST_BRIDGE, 0xe7) & 0x70) >> 4; |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1655 | if (reg8 == 2) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1656 | freq = CRCLK_166MHz; |
| 1657 | } |
| 1658 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1659 | printk(BIOS_DEBUG, "Render: "); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1660 | switch (freq) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1661 | case CRCLK_166MHz: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1662 | printk(BIOS_DEBUG, "166MHz"); |
| 1663 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1664 | case CRCLK_200MHz: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1665 | printk(BIOS_DEBUG, "200MHz"); |
| 1666 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1667 | case CRCLK_250MHz: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1668 | printk(BIOS_DEBUG, "250MHz"); |
| 1669 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1670 | case CRCLK_400MHz: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1671 | printk(BIOS_DEBUG, "400MHz"); |
| 1672 | break; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1673 | } |
| 1674 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1675 | if (i945_silicon_revision() == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1676 | sysinfo->mvco4x = 1; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1677 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1678 | sysinfo->mvco4x = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1679 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1680 | second_vco = 0; |
| 1681 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1682 | if (voltage == VOLTAGE_1_50) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1683 | second_vco = 1; |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 1684 | } else if ((i945_silicon_revision() > 0) && (freq == CRCLK_250MHz)) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1685 | u16 mem = sysinfo->memory_frequency; |
| 1686 | u16 fsb = sysinfo->fsb_frequency; |
| 1687 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1688 | if ((fsb == 667 && mem == 533) || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1689 | (fsb == 533 && mem == 533) || |
| 1690 | (fsb == 533 && mem == 400)) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1691 | second_vco = 1; |
| 1692 | } |
| 1693 | |
| 1694 | if (fsb == 667 && mem == 533) |
| 1695 | sysinfo->mvco4x = 1; |
| 1696 | } |
| 1697 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1698 | if (second_vco) |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1699 | sysinfo->clkcfg_bit7 = 1; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1700 | else |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1701 | sysinfo->clkcfg_bit7 = 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1702 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1703 | /* Graphics Core Render Clock */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1704 | pci_update_config16(IGD_DEV, GCFC, ~((7 << 0) | (1 << 13)), freq); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1705 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1706 | /* Graphics Core Display Clock */ |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1707 | reg8 = pci_read_config8(IGD_DEV, GCFC); |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 1708 | reg8 &= ~((1 << 7) | (7 << 4)); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1709 | |
| 1710 | if (voltage == VOLTAGE_1_05) { |
| 1711 | reg8 |= CDCLK_200MHz; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1712 | printk(BIOS_DEBUG, " Display: 200MHz\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1713 | } else { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1714 | reg8 |= CDCLK_320MHz; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1715 | printk(BIOS_DEBUG, " Display: 320MHz\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1716 | } |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1717 | pci_write_config8(IGD_DEV, GCFC, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1718 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1719 | reg8 = pci_read_config8(IGD_DEV, GCFC + 1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1720 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 1721 | reg8 |= (1 << 3) | (1 << 1); |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1722 | pci_write_config8(IGD_DEV, GCFC + 1, reg8); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1723 | |
| 1724 | reg8 |= 0x0f; |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1725 | pci_write_config8(IGD_DEV, GCFC + 1, reg8); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1726 | |
| 1727 | /* Ungate core render and display clocks */ |
| 1728 | reg8 &= 0xf0; |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 1729 | pci_write_config8(IGD_DEV, GCFC + 1, reg8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1730 | } |
| 1731 | |
| 1732 | static void sdram_program_memory_frequency(struct sys_info *sysinfo) |
| 1733 | { |
| 1734 | u32 clkcfg; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1735 | u8 offset = CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1736 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1737 | printk(BIOS_DEBUG, "Setting Memory Frequency... "); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1738 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1739 | clkcfg = mchbar_read32(CLKCFG); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1740 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 1741 | printk(BIOS_DEBUG, "CLKCFG = 0x%08x, ", clkcfg); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1742 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1743 | clkcfg &= ~((1 << 12) | (1 << 7) | (7 << 4)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1744 | |
| 1745 | if (sysinfo->mvco4x) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1746 | printk(BIOS_DEBUG, "MVCO 4x, "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1747 | clkcfg &= ~(1 << 12); |
| 1748 | } |
| 1749 | |
| 1750 | if (sysinfo->clkcfg_bit7) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1751 | printk(BIOS_DEBUG, "second VCO, "); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1752 | clkcfg |= (1 << 7); |
| 1753 | } |
| 1754 | |
| 1755 | switch (sysinfo->memory_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1756 | case 400: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1757 | clkcfg |= ((1 + offset) << 4); |
| 1758 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1759 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1760 | clkcfg |= ((2 + offset) << 4); |
| 1761 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1762 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1763 | clkcfg |= ((3 + offset) << 4); |
| 1764 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1765 | default: |
| 1766 | die("Target Memory Frequency Error"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1767 | } |
| 1768 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1769 | if (mchbar_read32(CLKCFG) == clkcfg) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1770 | printk(BIOS_DEBUG, "ok (unchanged)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1771 | return; |
| 1772 | } |
| 1773 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1774 | mchbar_write32(CLKCFG, clkcfg); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1775 | |
Petr Cvek | e75bb01 | 2022-06-16 17:13:22 +0200 | [diff] [blame] | 1776 | /* |
| 1777 | * Make sure the following code is in the cache before we execute it. |
| 1778 | * TODO: Experiments (i945GM) without any cache_code/delay_update |
| 1779 | * _seem_ to work even when XIP is disabled. Also on Pentium 4 |
| 1780 | * the code is not cached at all by default. |
| 1781 | */ |
| 1782 | asm volatile ( |
| 1783 | " jmp cache_code\n" |
| 1784 | "vco_update:\n" |
| 1785 | : /* No outputs */ |
| 1786 | : /* No inputs */ |
| 1787 | : "memory" |
| 1788 | ); |
| 1789 | |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 1790 | pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, (u8)~(1 << 7)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1791 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1792 | clkcfg &= ~(1 << 10); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1793 | mchbar_write32(CLKCFG, clkcfg); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1794 | clkcfg |= (1 << 10); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1795 | mchbar_write32(CLKCFG, clkcfg); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1796 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1797 | asm volatile ( |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1798 | " movl $0x100, %%ecx\n" |
| 1799 | "delay_update:\n" |
| 1800 | " nop\n" |
| 1801 | " nop\n" |
| 1802 | " nop\n" |
| 1803 | " nop\n" |
| 1804 | " loop delay_update\n" |
| 1805 | : /* No outputs */ |
| 1806 | : /* No inputs */ |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1807 | : "%ecx", "memory" |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1808 | ); |
| 1809 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1810 | clkcfg &= ~(1 << 10); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1811 | mchbar_write32(CLKCFG, clkcfg); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1812 | |
Petr Cvek | e75bb01 | 2022-06-16 17:13:22 +0200 | [diff] [blame] | 1813 | asm volatile ( |
| 1814 | " jmp out\n" |
| 1815 | "cache_code:\n" |
| 1816 | " jmp vco_update\n" |
| 1817 | "out:\n" |
| 1818 | : /* No outputs */ |
| 1819 | : /* No inputs */ |
| 1820 | : "memory" |
| 1821 | ); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1822 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1823 | printk(BIOS_DEBUG, "CLKCFG = 0x%08x, ", mchbar_read32(CLKCFG)); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1824 | printk(BIOS_DEBUG, "ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1825 | } |
| 1826 | |
| 1827 | static void sdram_program_clock_crossing(void) |
| 1828 | { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1829 | int idx = 0; |
| 1830 | |
| 1831 | /** |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1832 | * We add the indices according to our clocks from CLKCFG. |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1833 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1834 | #if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1835 | static const u32 data_clock_crossing[] = { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1836 | 0x00100401, 0x00000000, /* DDR400 FSB400 */ |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1837 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1838 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1839 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1840 | 0x08040120, 0x00000000, /* DDR400 FSB533 */ |
| 1841 | 0x00100401, 0x00000000, /* DDR533 FSB533 */ |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 1842 | 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1843 | |
| 1844 | 0x04020120, 0x00000010, /* DDR400 FSB667 */ |
| 1845 | 0x10040280, 0x00000040, /* DDR533 FSB667 */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1846 | 0x00100401, 0x00000000, /* DDR667 FSB667 */ |
| 1847 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1848 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1849 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1850 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1851 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1852 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1853 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1854 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1855 | }; |
| 1856 | |
| 1857 | static const u32 command_clock_crossing[] = { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1858 | 0x04020208, 0x00000000, /* DDR400 FSB400 */ |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1859 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1860 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1861 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1862 | 0x00060108, 0x00000000, /* DDR400 FSB533 */ |
| 1863 | 0x04020108, 0x00000000, /* DDR533 FSB533 */ |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1864 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1865 | |
| 1866 | 0x00040318, 0x00000000, /* DDR400 FSB667 */ |
| 1867 | 0x04020118, 0x00000000, /* DDR533 FSB667 */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1868 | 0x02010804, 0x00000000, /* DDR667 FSB667 */ |
| 1869 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1870 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1871 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1872 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1873 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1874 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1875 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1876 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1877 | }; |
| 1878 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 1879 | #elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1880 | /* i945 G/P */ |
| 1881 | static const u32 data_clock_crossing[] = { |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1882 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1883 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1884 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1885 | |
| 1886 | 0x10080201, 0x00000000, /* DDR400 FSB533 */ |
| 1887 | 0x00100401, 0x00000000, /* DDR533 FSB533 */ |
Patrick Georgi | 682ea3c | 2010-04-20 15:52:57 +0000 | [diff] [blame] | 1888 | 0x00010402, 0x00000000, /* DDR667 FSB533 - fake values */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1889 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1890 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1891 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1892 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1893 | |
| 1894 | 0x04020108, 0x00000000, /* DDR400 FSB800 */ |
| 1895 | 0x00020108, 0x00000000, /* DDR533 FSB800 */ |
| 1896 | 0x00080201, 0x00000000, /* DDR667 FSB800 */ |
| 1897 | |
| 1898 | 0x00010402, 0x00000000, /* DDR400 FSB1066 */ |
| 1899 | 0x04020108, 0x00000000, /* DDR533 FSB1066 */ |
| 1900 | 0x08040110, 0x00000000, /* DDR667 FSB1066 */ |
| 1901 | }; |
| 1902 | |
| 1903 | static const u32 command_clock_crossing[] = { |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1904 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1905 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1906 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1907 | |
| 1908 | 0x00010800, 0x00000402, /* DDR400 FSB533 */ |
| 1909 | 0x01000400, 0x00000200, /* DDR533 FSB533 */ |
Patrick Georgi | 682ea3c | 2010-04-20 15:52:57 +0000 | [diff] [blame] | 1910 | 0x00020904, 0x00000000, /* DDR667 FSB533 - fake values */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1911 | |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 1912 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1913 | 0xffffffff, 0xffffffff, /* nonexistent */ |
| 1914 | 0xffffffff, 0xffffffff, /* nonexistent */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1915 | |
| 1916 | 0x02010804, 0x00000000, /* DDR400 FSB800 */ |
| 1917 | 0x00010402, 0x00000000, /* DDR533 FSB800 */ |
Arthur Heymans | 8b6df62 | 2016-10-16 10:58:01 +0200 | [diff] [blame] | 1918 | 0x04020130, 0x00000008, /* DDR667 FSB800 */ |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1919 | |
| 1920 | 0x00020904, 0x00000000, /* DDR400 FSB1066 */ |
| 1921 | 0x02010804, 0x00000000, /* DDR533 FSB1066 */ |
| 1922 | 0x180601c0, 0x00000020, /* DDR667 FSB1066 */ |
| 1923 | }; |
| 1924 | #endif |
| 1925 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1926 | printk(BIOS_DEBUG, "Programming Clock Crossing..."); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1927 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1928 | printk(BIOS_DEBUG, "MEM="); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1929 | switch (memclk()) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1930 | case 400: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1931 | printk(BIOS_DEBUG, "400"); |
| 1932 | idx += 0; |
| 1933 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1934 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1935 | printk(BIOS_DEBUG, "533"); |
| 1936 | idx += 2; |
| 1937 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1938 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1939 | printk(BIOS_DEBUG, "667"); |
| 1940 | idx += 4; |
| 1941 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1942 | default: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1943 | printk(BIOS_DEBUG, "RSVD %x", memclk()); |
| 1944 | return; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1945 | } |
| 1946 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1947 | printk(BIOS_DEBUG, " FSB="); |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1948 | switch (fsbclk()) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1949 | case 400: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1950 | printk(BIOS_DEBUG, "400"); |
| 1951 | idx += 0; |
| 1952 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1953 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1954 | printk(BIOS_DEBUG, "533"); |
| 1955 | idx += 6; |
| 1956 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1957 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1958 | printk(BIOS_DEBUG, "667"); |
| 1959 | idx += 12; |
| 1960 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1961 | case 800: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1962 | printk(BIOS_DEBUG, "800"); |
| 1963 | idx += 18; |
| 1964 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1965 | case 1066: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1966 | printk(BIOS_DEBUG, "1066"); |
| 1967 | idx += 24; |
| 1968 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1969 | default: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 1970 | printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); |
| 1971 | return; |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 1972 | } |
| 1973 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 1974 | if (command_clock_crossing[idx] == 0xffffffff) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1975 | printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1976 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1977 | mchbar_write32(CCCFT + 0, command_clock_crossing[idx]); |
| 1978 | mchbar_write32(CCCFT + 4, command_clock_crossing[idx + 1]); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 1979 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1980 | mchbar_write32(C0DCCFT + 0, data_clock_crossing[idx]); |
| 1981 | mchbar_write32(C0DCCFT + 4, data_clock_crossing[idx + 1]); |
| 1982 | mchbar_write32(C1DCCFT + 0, data_clock_crossing[idx]); |
| 1983 | mchbar_write32(C1DCCFT + 4, data_clock_crossing[idx + 1]); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1984 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 1985 | printk(BIOS_DEBUG, "... ok\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1986 | } |
| 1987 | |
| 1988 | static void sdram_disable_fast_dispatch(void) |
| 1989 | { |
| 1990 | u32 reg32; |
| 1991 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1992 | reg32 = mchbar_read32(FSBPMC3); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1993 | reg32 |= (1 << 1); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1994 | mchbar_write32(FSBPMC3, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1995 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1996 | reg32 = mchbar_read32(SBTEST); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1997 | reg32 |= (3 << 1); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 1998 | mchbar_write32(SBTEST, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 1999 | } |
| 2000 | |
| 2001 | static void sdram_pre_jedec_initialization(void) |
| 2002 | { |
| 2003 | u32 reg32; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2004 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2005 | reg32 = mchbar_read32(WCC); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2006 | reg32 &= 0x113ff3ff; |
| 2007 | reg32 |= (4 << 29) | (3 << 25) | (1 << 10); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2008 | mchbar_write32(WCC, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2009 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2010 | mchbar_setbits32(SMVREFC, 1 << 6); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2011 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2012 | mchbar_clrbits32(MMARB0, 3 << 17); |
| 2013 | mchbar_setbits32(MMARB0, 1 << 21 | 1 << 16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2014 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2015 | mchbar_clrbits32(MMARB1, 7 << 8); |
| 2016 | mchbar_setbits32(MMARB1, 3 << 8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2017 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2018 | /* Adaptive Idle Timer Control */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2019 | mchbar_write32(C0AIT + 0, 0x000006c4); |
| 2020 | mchbar_write32(C0AIT + 4, 0x871a066d); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2021 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2022 | mchbar_write32(C1AIT + 0, 0x000006c4); |
| 2023 | mchbar_write32(C1AIT + 4, 0x871a066d); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2024 | } |
| 2025 | |
| 2026 | #define EA_DUALCHANNEL_XOR_BANK_RANK_MODE (0xd4 << 24) |
| 2027 | #define EA_DUALCHANNEL_XOR_BANK_MODE (0xf4 << 24) |
| 2028 | #define EA_DUALCHANNEL_BANK_RANK_MODE (0xc2 << 24) |
| 2029 | #define EA_DUALCHANNEL_BANK_MODE (0xe2 << 24) |
| 2030 | #define EA_SINGLECHANNEL_XOR_BANK_RANK_MODE (0x91 << 24) |
| 2031 | #define EA_SINGLECHANNEL_XOR_BANK_MODE (0xb1 << 24) |
| 2032 | #define EA_SINGLECHANNEL_BANK_RANK_MODE (0x80 << 24) |
| 2033 | #define EA_SINGLECHANNEL_BANK_MODE (0xa0 << 24) |
| 2034 | |
| 2035 | static void sdram_enhanced_addressing_mode(struct sys_info *sysinfo) |
| 2036 | { |
| 2037 | u32 chan0 = 0, chan1 = 0; |
Paul Menzel | d789b658 | 2020-03-14 11:50:34 +0100 | [diff] [blame] | 2038 | bool chan0_dualsided, chan1_dualsided, chan0_populated, chan1_populated; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2039 | |
Paul Menzel | 842dd33 | 2020-03-14 10:37:40 +0100 | [diff] [blame] | 2040 | chan0_populated = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2041 | sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); |
Elyes HAOUAS | 308aeff | 2017-02-24 12:53:07 +0100 | [diff] [blame] | 2042 | chan1_populated = (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2043 | sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2044 | chan0_dualsided = (sysinfo->banksize[1] || sysinfo->banksize[3]); |
| 2045 | chan1_dualsided = (sysinfo->banksize[5] || sysinfo->banksize[7]); |
| 2046 | |
| 2047 | if (sdram_capabilities_enhanced_addressing_xor()) { |
| 2048 | if (!sysinfo->interleaved) { |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 2049 | /* Single Channel & Dual Channel Asymmetric */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2050 | if (chan0_populated) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2051 | if (chan0_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2052 | chan0 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2053 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2054 | chan0 = EA_SINGLECHANNEL_XOR_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2055 | } |
| 2056 | if (chan1_populated) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2057 | if (chan1_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2058 | chan1 = EA_SINGLECHANNEL_XOR_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2059 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2060 | chan1 = EA_SINGLECHANNEL_XOR_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2061 | } |
| 2062 | } else { |
| 2063 | /* Interleaved has always both channels populated */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2064 | if (chan0_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2065 | chan0 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2066 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2067 | chan0 = EA_DUALCHANNEL_XOR_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2068 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2069 | if (chan1_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2070 | chan1 = EA_DUALCHANNEL_XOR_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2071 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2072 | chan1 = EA_DUALCHANNEL_XOR_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2073 | } |
| 2074 | } else { |
| 2075 | if (!sysinfo->interleaved) { |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 2076 | /* Single Channel & Dual Channel Asymmetric */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2077 | if (chan0_populated) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2078 | if (chan0_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2079 | chan0 = EA_SINGLECHANNEL_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2080 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2081 | chan0 = EA_SINGLECHANNEL_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2082 | } |
| 2083 | if (chan1_populated) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2084 | if (chan1_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2085 | chan1 = EA_SINGLECHANNEL_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2086 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2087 | chan1 = EA_SINGLECHANNEL_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2088 | } |
| 2089 | } else { |
| 2090 | /* Interleaved has always both channels populated */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2091 | if (chan0_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2092 | chan0 = EA_DUALCHANNEL_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2093 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2094 | chan0 = EA_DUALCHANNEL_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2095 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2096 | if (chan1_dualsided) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2097 | chan1 = EA_DUALCHANNEL_BANK_RANK_MODE; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2098 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2099 | chan1 = EA_DUALCHANNEL_BANK_MODE; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2100 | } |
| 2101 | } |
| 2102 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2103 | mchbar_clrbits32(C0DRC1, 0xff << 24); |
| 2104 | mchbar_setbits32(C0DRC1, chan0); |
| 2105 | mchbar_clrbits32(C1DRC1, 0xff << 24); |
| 2106 | mchbar_setbits32(C1DRC1, chan1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2107 | } |
| 2108 | |
| 2109 | static void sdram_post_jedec_initialization(struct sys_info *sysinfo) |
| 2110 | { |
| 2111 | u32 reg32; |
| 2112 | |
| 2113 | /* Enable Channel XORing for Dual Channel Interleave */ |
| 2114 | if (sysinfo->interleaved) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2115 | reg32 = mchbar_read32(DCC); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2116 | reg32 &= ~(1 << 10); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 2117 | reg32 |= (1 << 9); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2118 | mchbar_write32(DCC, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2119 | } |
| 2120 | |
| 2121 | /* DRAM mode optimizations */ |
| 2122 | sdram_enhanced_addressing_mode(sysinfo); |
| 2123 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2124 | reg32 = mchbar_read32(FSBPMC3); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2125 | reg32 &= ~(1 << 1); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2126 | mchbar_write32(FSBPMC3, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2127 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2128 | reg32 = mchbar_read32(SBTEST); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2129 | reg32 &= ~(1 << 2); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2130 | mchbar_write32(SBTEST, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2131 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2132 | reg32 = mchbar_read32(SBOCC); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2133 | reg32 &= 0xffbdb6ff; |
| 2134 | reg32 |= (0xbdb6 << 8) | (1 << 0); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2135 | mchbar_write32(SBOCC, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2136 | } |
| 2137 | |
| 2138 | static void sdram_power_management(struct sys_info *sysinfo) |
| 2139 | { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2140 | u16 reg16; |
| 2141 | u32 reg32; |
Elyes HAOUAS | 187bec7 | 2021-12-12 07:00:50 +0100 | [diff] [blame] | 2142 | bool integrated_graphics = true; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2143 | int i; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2144 | |
Elyes HAOUAS | 8f20b12 | 2021-02-14 13:22:10 +0100 | [diff] [blame] | 2145 | if (!(pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))) |
| 2146 | integrated_graphics = false; |
| 2147 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2148 | reg32 = mchbar_read32(C0DRT2); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2149 | reg32 &= 0xffffff00; |
| 2150 | /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2151 | reg32 |= (1 << 5) | (1 << 4); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2152 | mchbar_write32(C0DRT2, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2153 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2154 | reg32 = mchbar_read32(C1DRT2); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2155 | reg32 &= 0xffffff00; |
| 2156 | /* Idle timer = 8 clocks, CKE idle timer = 16 clocks */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2157 | reg32 |= (1 << 5) | (1 << 4); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2158 | mchbar_write32(C1DRT2, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2159 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2160 | reg32 = mchbar_read32(C0DRC1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2161 | |
| 2162 | reg32 |= (1 << 12) | (1 << 11); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2163 | mchbar_write32(C0DRC1, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2164 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2165 | reg32 = mchbar_read32(C1DRC1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2166 | |
| 2167 | reg32 |= (1 << 12) | (1 << 11); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2168 | mchbar_write32(C1DRC1, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2169 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 2170 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { |
Arthur Heymans | 2f6b52e | 2017-03-02 23:51:09 +0100 | [diff] [blame] | 2171 | if (i945_silicon_revision() > 1) { |
| 2172 | /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ |
| 2173 | u16 peg_bits = (1 << 5) | (1 << 0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2174 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2175 | mchbar_write16(UPMC1, 0x1010 | peg_bits); |
Arthur Heymans | 2f6b52e | 2017-03-02 23:51:09 +0100 | [diff] [blame] | 2176 | } else { |
| 2177 | /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ |
| 2178 | u16 peg_bits = (1 << 5) | (1 << 0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2179 | |
Arthur Heymans | 2f6b52e | 2017-03-02 23:51:09 +0100 | [diff] [blame] | 2180 | /* Rev 0 and 1 */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2181 | mchbar_write16(UPMC1, 0x0010 | peg_bits); |
Arthur Heymans | 2f6b52e | 2017-03-02 23:51:09 +0100 | [diff] [blame] | 2182 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2183 | } |
| 2184 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2185 | reg16 = mchbar_read16(UPMC2); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2186 | reg16 &= 0xfc00; |
| 2187 | reg16 |= 0x0100; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2188 | mchbar_write16(UPMC2, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2189 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2190 | mchbar_write32(UPMC3, 0x000f06ff); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2191 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 2192 | for (i = 0; i < 5; i++) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2193 | mchbar_clrbits32(UPMC3, 1 << 16); |
| 2194 | mchbar_setbits32(UPMC3, 1 << 16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2195 | } |
| 2196 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2197 | mchbar_write32(GIPMC1, 0x8000000c); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2198 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2199 | reg16 = mchbar_read16(CPCTL); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2200 | reg16 &= ~(7 << 11); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2201 | if (i945_silicon_revision() > 2) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2202 | reg16 |= (6 << 11); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2203 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2204 | reg16 |= (4 << 11); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2205 | mchbar_write16(CPCTL, reg16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2206 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 2207 | #if 0 |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2208 | if ((mchbar_read32(ECO) & (1 << 16)) != 0) { |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 2209 | #else |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 2210 | if (i945_silicon_revision() != 0) { |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 2211 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2212 | switch (sysinfo->fsb_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2213 | case 667: |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2214 | mchbar_write32(HGIPMC2, 0x0d590d59); |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2215 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2216 | case 533: |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2217 | mchbar_write32(HGIPMC2, 0x155b155b); |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2218 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2219 | } |
| 2220 | } else { |
| 2221 | switch (sysinfo->fsb_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2222 | case 667: |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2223 | mchbar_write32(HGIPMC2, 0x09c409c4); |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2224 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2225 | case 533: |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2226 | mchbar_write32(HGIPMC2, 0x0fa00fa0); |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2227 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2228 | } |
| 2229 | } |
| 2230 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2231 | mchbar_write32(FSBPMC1, 0x8000000c); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2232 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2233 | reg32 = mchbar_read32(C2C3TT); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2234 | reg32 &= 0xffff0000; |
| 2235 | switch (sysinfo->fsb_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2236 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2237 | reg32 |= 0x0600; |
| 2238 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2239 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2240 | reg32 |= 0x0480; |
| 2241 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2242 | } |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2243 | mchbar_write32(C2C3TT, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2244 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2245 | reg32 = mchbar_read32(C3C4TT); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2246 | reg32 &= 0xffff0000; |
| 2247 | switch (sysinfo->fsb_frequency) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2248 | case 667: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2249 | reg32 |= 0x0b80; |
| 2250 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2251 | case 533: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2252 | reg32 |= 0x0980; |
| 2253 | break; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2254 | } |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2255 | mchbar_write32(C3C4TT, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2256 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2257 | if (i945_silicon_revision() == 0) |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2258 | mchbar_clrbits32(ECO, 1 << 16); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2259 | else |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2260 | mchbar_setbits32(ECO, 1 << 16); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2261 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2262 | mchbar_clrbits32(FSBPMC3, 1 << 29); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2263 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2264 | mchbar_setbits32(FSBPMC3, 1 << 21); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2265 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2266 | mchbar_clrbits32(FSBPMC3, 1 << 19); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2267 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2268 | mchbar_clrbits32(FSBPMC3, 1 << 13); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2269 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2270 | reg32 = mchbar_read32(FSBPMC4); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2271 | reg32 &= ~(3 << 24); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2272 | reg32 |= (2 << 24); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2273 | mchbar_write32(FSBPMC4, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2274 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2275 | mchbar_setbits32(FSBPMC4, 1 << 21); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2276 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2277 | mchbar_setbits32(FSBPMC4, 1 << 5); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2278 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2279 | if ((i945_silicon_revision() < 2)) { /* || cpuid() = 0x6e8 */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2280 | /* stepping 0 and 1 or CPUID 6e8 */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2281 | mchbar_clrbits32(FSBPMC4, 1 << 4); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2282 | } else { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2283 | mchbar_setbits32(FSBPMC4, 1 << 4); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2284 | } |
| 2285 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 2286 | pci_or_config8(HOST_BRIDGE, 0xfc, 1 << 4); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2287 | |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 2288 | pci_or_config8(IGD_DEV, 0xc1, 1 << 2); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2289 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2290 | if (integrated_graphics) { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2291 | mchbar_write16(MIPMC4, 0x04f8); |
| 2292 | mchbar_write16(MIPMC5, 0x04fc); |
| 2293 | mchbar_write16(MIPMC6, 0x04fc); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2294 | } else { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2295 | mchbar_write16(MIPMC4, 0x64f8); |
| 2296 | mchbar_write16(MIPMC5, 0x64fc); |
| 2297 | mchbar_write16(MIPMC6, 0x64fc); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2298 | } |
| 2299 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2300 | reg32 = mchbar_read32(PMCFG); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2301 | reg32 &= ~(3 << 17); |
| 2302 | reg32 |= (2 << 17); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2303 | mchbar_write32(PMCFG, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2304 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2305 | mchbar_setbits32(PMCFG, 1 << 4); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2306 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2307 | reg32 = mchbar_read32(UPMC4); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2308 | reg32 &= 0xffffff00; |
| 2309 | reg32 |= 0x01; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2310 | mchbar_write32(UPMC4, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2311 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2312 | mchbar_clrbits32(0xb18, 1 << 21); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2313 | } |
| 2314 | |
| 2315 | static void sdram_thermal_management(void) |
| 2316 | { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2317 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2318 | mchbar_write8(TCO1, 0); |
| 2319 | mchbar_write8(TCO0, 0); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2320 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2321 | /* The Thermal Sensors for DIMMs at 0x50, 0x52 are at I2C addr 0x30/0x32. */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2322 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 2323 | /* TODO This is not implemented yet. Volunteers? */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2324 | } |
| 2325 | |
| 2326 | static void sdram_save_receive_enable(void) |
| 2327 | { |
| 2328 | int i; |
| 2329 | u32 reg32; |
| 2330 | u8 values[4]; |
| 2331 | |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2332 | /* The following values are stored to an unused CMOS area and restored instead of |
| 2333 | * recalculated in case of an S3 resume. |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2334 | * |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2335 | * C0WL0REOST [7:0] -> 8 bit |
| 2336 | * C1WL0REOST [7:0] -> 8 bit |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2337 | * RCVENMT [11:8] [3:0] -> 8 bit |
| 2338 | * C0DRT1 [27:24] -> 4 bit |
| 2339 | * C1DRT1 [27:24] -> 4 bit |
| 2340 | */ |
| 2341 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2342 | values[0] = mchbar_read8(C0WL0REOST); |
| 2343 | values[1] = mchbar_read8(C1WL0REOST); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2344 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2345 | reg32 = mchbar_read32(RCVENMT); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2346 | values[2] = (u8)((reg32 >> (8 - 4)) & 0xf0) | (reg32 & 0x0f); |
| 2347 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2348 | reg32 = mchbar_read32(C0DRT1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2349 | values[3] = (reg32 >> 24) & 0x0f; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2350 | reg32 = mchbar_read32(C1DRT1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2351 | values[3] |= (reg32 >> (24 - 4)) & 0xf0; |
| 2352 | |
| 2353 | /* coreboot only uses bytes 0 - 127 for its CMOS values so far |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 2354 | * so we grab bytes 128 - 131 to save the receive enable values |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2355 | */ |
| 2356 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 2357 | for (i = 0; i < 4; i++) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2358 | cmos_write(values[i], 128 + i); |
| 2359 | } |
| 2360 | |
| 2361 | static void sdram_recover_receive_enable(void) |
| 2362 | { |
| 2363 | int i; |
| 2364 | u32 reg32; |
| 2365 | u8 values[4]; |
| 2366 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 2367 | for (i = 0; i < 4; i++) |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2368 | values[i] = cmos_read(128 + i); |
| 2369 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2370 | mchbar_write8(C0WL0REOST, values[0]); |
| 2371 | mchbar_write8(C1WL0REOST, values[1]); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2372 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2373 | reg32 = mchbar_read32(RCVENMT); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2374 | reg32 &= ~((0x0f << 8) | (0x0f << 0)); |
| 2375 | reg32 |= ((u32)(values[2] & 0xf0) << (8 - 4)) | (values[2] & 0x0f); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2376 | mchbar_write32(RCVENMT, reg32); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2377 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2378 | reg32 = mchbar_read32(C0DRT1) & ~(0x0f << 24); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2379 | reg32 |= (u32)(values[3] & 0x0f) << 24; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2380 | mchbar_write32(C0DRT1, reg32); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2381 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2382 | reg32 = mchbar_read32(C1DRT1) & ~(0x0f << 24); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2383 | reg32 |= (u32)(values[3] & 0xf0) << (24 - 4); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2384 | mchbar_write32(C1DRT1, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2385 | } |
| 2386 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2387 | static void sdram_program_receive_enable(struct sys_info *sysinfo) |
| 2388 | { |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2389 | mchbar_setbits32(REPC, 1 << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2390 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2391 | /* Program Receive Enable Timings */ |
| 2392 | if (sysinfo->boot_path == BOOT_PATH_RESUME) { |
| 2393 | sdram_recover_receive_enable(); |
| 2394 | } else { |
| 2395 | receive_enable_adjust(sysinfo); |
| 2396 | sdram_save_receive_enable(); |
| 2397 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2398 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2399 | mchbar_setbits32(C0DRC1, 1 << 6); |
| 2400 | mchbar_setbits32(C1DRC1, 1 << 6); |
| 2401 | mchbar_clrbits32(C0DRC1, 1 << 6); |
| 2402 | mchbar_clrbits32(C1DRC1, 1 << 6); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2403 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2404 | mchbar_setbits32(MIPMC3, 0x0f << 0); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2405 | } |
| 2406 | |
| 2407 | /** |
| 2408 | * @brief Enable On-Die Termination for DDR2. |
| 2409 | * |
| 2410 | */ |
| 2411 | |
| 2412 | static void sdram_on_die_termination(struct sys_info *sysinfo) |
| 2413 | { |
| 2414 | static const u32 odt[] = { |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2415 | 0x00024911, 0xe0010000, |
| 2416 | 0x00049211, 0xe0020000, |
| 2417 | 0x0006db11, 0xe0030000, |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2418 | }; |
| 2419 | |
| 2420 | u32 reg32; |
| 2421 | int cas; |
| 2422 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2423 | reg32 = mchbar_read32(ODTC); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2424 | reg32 &= ~(3 << 16); |
| 2425 | reg32 |= (1 << 14) | (1 << 6) | (2 << 16); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2426 | mchbar_write32(ODTC, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2427 | |
Paul Menzel | b4d9f22 | 2020-03-14 10:34:29 +0100 | [diff] [blame] | 2428 | if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED || |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2429 | sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) { |
Elyes HAOUAS | 3842498 | 2016-08-21 12:01:04 +0200 | [diff] [blame] | 2430 | printk(BIOS_DEBUG, "one dimm per channel config..\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2431 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2432 | reg32 = mchbar_read32(C0ODT); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2433 | reg32 &= ~(7 << 28); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2434 | mchbar_write32(C0ODT, reg32); |
| 2435 | reg32 = mchbar_read32(C1ODT); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2436 | reg32 &= ~(7 << 28); |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2437 | mchbar_write32(C1ODT, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2438 | } |
| 2439 | |
| 2440 | cas = sysinfo->cas; |
| 2441 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2442 | reg32 = mchbar_read32(C0ODT) & 0xfff00000; |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 2443 | reg32 |= odt[(cas - 3) * 2]; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2444 | mchbar_write32(C0ODT, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2445 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2446 | reg32 = mchbar_read32(C1ODT) & 0xfff00000; |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 2447 | reg32 |= odt[(cas - 3) * 2]; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2448 | mchbar_write32(C1ODT, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2449 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2450 | reg32 = mchbar_read32(C0ODT + 4) & 0x1fc8ffff; |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 2451 | reg32 |= odt[((cas - 3) * 2) + 1]; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2452 | mchbar_write32(C0ODT + 4, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2453 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2454 | reg32 = mchbar_read32(C1ODT + 4) & 0x1fc8ffff; |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 2455 | reg32 |= odt[((cas - 3) * 2) + 1]; |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2456 | mchbar_write32(C1ODT + 4, reg32); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2457 | } |
| 2458 | |
| 2459 | /** |
| 2460 | * @brief Enable clocks to populated sockets |
| 2461 | */ |
| 2462 | |
| 2463 | static void sdram_enable_memory_clocks(struct sys_info *sysinfo) |
| 2464 | { |
| 2465 | u8 clocks[2] = { 0, 0 }; |
| 2466 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 2467 | #if CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 2468 | #define CLOCKS_WIDTH 2 |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 2469 | #elif CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC) |
Stefan Reinauer | 24b4df5 | 2010-01-17 13:47:35 +0000 | [diff] [blame] | 2470 | #define CLOCKS_WIDTH 3 |
| 2471 | #endif |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2472 | if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED) |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 2473 | clocks[0] |= (1 << CLOCKS_WIDTH) - 1; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2474 | |
| 2475 | if (sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 2476 | clocks[0] |= ((1 << CLOCKS_WIDTH) - 1) << CLOCKS_WIDTH; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2477 | |
| 2478 | if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED) |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 2479 | clocks[1] |= (1 << CLOCKS_WIDTH) - 1; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2480 | |
| 2481 | if (sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED) |
Angel Pons | 3049257 | 2020-06-11 13:24:54 +0200 | [diff] [blame] | 2482 | clocks[1] |= ((1 << CLOCKS_WIDTH) - 1) << CLOCKS_WIDTH; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2483 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 2484 | #if CONFIG(OVERRIDE_CLOCK_DISABLE) |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2485 | /* Usually system firmware turns off system memory clock signals to unused SO-DIMM slots |
| 2486 | * to reduce EMI and power consumption. |
| 2487 | * However, the Kontron 986LCD-M does not like unused clock signals to be disabled. |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2488 | */ |
| 2489 | |
| 2490 | clocks[0] = 0xf; /* force all clock gate pairs to enable */ |
| 2491 | clocks[1] = 0xf; /* force all clock gate pairs to enable */ |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2492 | #endif |
| 2493 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2494 | mchbar_write8(C0DCLKDIS, clocks[0]); |
| 2495 | mchbar_write8(C1DCLKDIS, clocks[1]); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2496 | } |
| 2497 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2498 | #define RTT_ODT_NONE 0 |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 2499 | #define RTT_ODT_50_OHM ((1 << 9) | (1 << 5)) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2500 | #define RTT_ODT_75_OHM (1 << 5) |
| 2501 | #define RTT_ODT_150_OHM (1 << 9) |
| 2502 | |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2503 | #define EMRS_OCD_DEFAULT ((1 << 12) | (1 << 11) | (1 << 10)) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2504 | |
| 2505 | #define MRS_CAS_3 (3 << 7) |
| 2506 | #define MRS_CAS_4 (4 << 7) |
| 2507 | #define MRS_CAS_5 (5 << 7) |
| 2508 | |
| 2509 | #define MRS_TWR_3 (2 << 12) |
| 2510 | #define MRS_TWR_4 (3 << 12) |
| 2511 | #define MRS_TWR_5 (4 << 12) |
| 2512 | |
| 2513 | #define MRS_BT (1 << 6) |
| 2514 | |
| 2515 | #define MRS_BL4 (2 << 3) |
| 2516 | #define MRS_BL8 (3 << 3) |
| 2517 | |
| 2518 | static void sdram_jedec_enable(struct sys_info *sysinfo) |
| 2519 | { |
| 2520 | int i, nonzero; |
| 2521 | u32 bankaddr = 0, tmpaddr, mrsaddr = 0; |
| 2522 | |
| 2523 | for (i = 0, nonzero = -1; i < 8; i++) { |
Elyes HAOUAS | 0191220 | 2019-01-19 16:36:38 +0100 | [diff] [blame] | 2524 | if (sysinfo->banksize[i] == 0) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2525 | continue; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2526 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 2527 | printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i); |
Elyes HAOUAS | 0191220 | 2019-01-19 16:36:38 +0100 | [diff] [blame] | 2528 | |
| 2529 | if (nonzero != -1) { |
| 2530 | if (sysinfo->interleaved && nonzero < 4 && i >= 4) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2531 | bankaddr = 0x40; |
Elyes HAOUAS | 0191220 | 2019-01-19 16:36:38 +0100 | [diff] [blame] | 2532 | } else { |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 2533 | printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", |
| 2534 | nonzero); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2535 | bankaddr += sysinfo->banksize[nonzero] << |
| 2536 | (sysinfo->interleaved ? 26 : 25); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2537 | } |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2538 | } |
| 2539 | |
Elyes HAOUAS | 95cdd9f | 2020-03-26 12:20:38 +0100 | [diff] [blame] | 2540 | /* |
| 2541 | * We have a bank with a non-zero size... Remember it |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2542 | * for the next offset we have to calculate |
| 2543 | */ |
| 2544 | nonzero = i; |
| 2545 | |
| 2546 | /* Get CAS latency set up */ |
| 2547 | switch (sysinfo->cas) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2548 | case 5: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2549 | mrsaddr = MRS_CAS_5; |
| 2550 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2551 | case 4: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2552 | mrsaddr = MRS_CAS_4; |
| 2553 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2554 | case 3: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2555 | mrsaddr = MRS_CAS_3; |
| 2556 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2557 | default: |
| 2558 | die("Jedec Error (CAS).\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2559 | } |
| 2560 | |
| 2561 | /* Get tWR set */ |
| 2562 | switch (sysinfo->twr) { |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2563 | case 5: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2564 | mrsaddr |= MRS_TWR_5; |
| 2565 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2566 | case 4: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2567 | mrsaddr |= MRS_TWR_4; |
| 2568 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2569 | case 3: |
Elyes HAOUAS | 3dff32c | 2020-03-30 17:16:51 +0200 | [diff] [blame] | 2570 | mrsaddr |= MRS_TWR_3; |
| 2571 | break; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2572 | default: |
| 2573 | die("Jedec Error (tWR).\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2574 | } |
| 2575 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2576 | /* Set "Burst Type" */ |
| 2577 | mrsaddr |= MRS_BT; |
| 2578 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2579 | /* Interleaved */ |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2580 | if (sysinfo->interleaved) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2581 | mrsaddr = mrsaddr << 1; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2582 | |
| 2583 | /* Only burst length 8 supported */ |
| 2584 | mrsaddr |= MRS_BL8; |
| 2585 | |
| 2586 | /* Apply NOP */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2587 | PRINTK_DEBUG("Apply NOP\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2588 | do_ram_command(RAM_COMMAND_NOP); |
| 2589 | ram_read32(bankaddr); |
| 2590 | |
| 2591 | /* Precharge all banks */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2592 | PRINTK_DEBUG("All Banks Precharge\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2593 | do_ram_command(RAM_COMMAND_PRECHARGE); |
| 2594 | ram_read32(bankaddr); |
| 2595 | |
| 2596 | /* Extended Mode Register Set (2) */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2597 | PRINTK_DEBUG("Extended Mode Register Set(2)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2598 | do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_2); |
| 2599 | ram_read32(bankaddr); |
| 2600 | |
| 2601 | /* Extended Mode Register Set (3) */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2602 | PRINTK_DEBUG("Extended Mode Register Set(3)\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2603 | do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_3); |
| 2604 | ram_read32(bankaddr); |
| 2605 | |
| 2606 | /* Extended Mode Register Set */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2607 | PRINTK_DEBUG("Extended Mode Register Set\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2608 | do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1); |
| 2609 | tmpaddr = bankaddr; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2610 | if (!sdram_capabilities_dual_channel()) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2611 | tmpaddr |= RTT_ODT_75_OHM; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2612 | else if (sysinfo->interleaved) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2613 | tmpaddr |= (RTT_ODT_150_OHM << 1); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2614 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2615 | tmpaddr |= RTT_ODT_150_OHM; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2616 | ram_read32(tmpaddr); |
| 2617 | |
| 2618 | /* Mode Register Set: Reset DLLs */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2619 | PRINTK_DEBUG("MRS: Reset DLLs\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2620 | do_ram_command(RAM_COMMAND_MRS); |
| 2621 | tmpaddr = bankaddr; |
| 2622 | tmpaddr |= mrsaddr; |
| 2623 | /* Set DLL reset bit */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2624 | if (sysinfo->interleaved) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2625 | tmpaddr |= (1 << 12); |
| 2626 | else |
| 2627 | tmpaddr |= (1 << 11); |
| 2628 | ram_read32(tmpaddr); |
| 2629 | |
| 2630 | /* Precharge all banks */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2631 | PRINTK_DEBUG("All Banks Precharge\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2632 | do_ram_command(RAM_COMMAND_PRECHARGE); |
| 2633 | ram_read32(bankaddr); |
| 2634 | |
| 2635 | /* CAS before RAS Refresh */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2636 | PRINTK_DEBUG("CAS before RAS\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2637 | do_ram_command(RAM_COMMAND_CBR); |
| 2638 | |
| 2639 | /* CBR wants two READs */ |
| 2640 | ram_read32(bankaddr); |
| 2641 | ram_read32(bankaddr); |
| 2642 | |
| 2643 | /* Mode Register Set: Enable DLLs */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2644 | PRINTK_DEBUG("MRS: Enable DLLs\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2645 | do_ram_command(RAM_COMMAND_MRS); |
| 2646 | |
| 2647 | tmpaddr = bankaddr; |
| 2648 | tmpaddr |= mrsaddr; |
| 2649 | ram_read32(tmpaddr); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2650 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2651 | /* Extended Mode Register Set */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2652 | PRINTK_DEBUG("Extended Mode Register Set: ODT/OCD\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2653 | do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2654 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2655 | tmpaddr = bankaddr; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2656 | if (!sdram_capabilities_dual_channel()) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2657 | tmpaddr |= RTT_ODT_75_OHM | EMRS_OCD_DEFAULT; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2658 | else if (sysinfo->interleaved) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2659 | tmpaddr |= ((RTT_ODT_150_OHM | EMRS_OCD_DEFAULT) << 1); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2660 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2661 | tmpaddr |= RTT_ODT_150_OHM | EMRS_OCD_DEFAULT; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2662 | ram_read32(tmpaddr); |
| 2663 | |
| 2664 | /* Extended Mode Register Set */ |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2665 | PRINTK_DEBUG("Extended Mode Register Set: OCD Exit\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2666 | do_ram_command(RAM_COMMAND_EMRS | RAM_EMRS_1); |
| 2667 | |
| 2668 | tmpaddr = bankaddr; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2669 | if (!sdram_capabilities_dual_channel()) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2670 | tmpaddr |= RTT_ODT_75_OHM; |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2671 | else if (sysinfo->interleaved) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2672 | tmpaddr |= (RTT_ODT_150_OHM << 1); |
Arthur Heymans | 70a8e34 | 2017-03-09 11:30:23 +0100 | [diff] [blame] | 2673 | else |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2674 | tmpaddr |= RTT_ODT_150_OHM; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2675 | ram_read32(tmpaddr); |
| 2676 | } |
| 2677 | } |
| 2678 | |
| 2679 | static void sdram_init_complete(void) |
| 2680 | { |
Stefan Reinauer | 779b3e3 | 2008-11-10 15:43:37 +0000 | [diff] [blame] | 2681 | PRINTK_DEBUG("Normal Operation\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2682 | do_ram_command(RAM_COMMAND_NORMAL); |
| 2683 | } |
| 2684 | |
| 2685 | static void sdram_setup_processor_side(void) |
| 2686 | { |
| 2687 | if (i945_silicon_revision() == 0) |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2688 | mchbar_setbits32(FSBPMC3, 1 << 2); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2689 | |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2690 | mchbar_setbits8(0xb00, 1); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2691 | |
| 2692 | if (i945_silicon_revision() == 0) |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2693 | mchbar_setbits32(SLPCTL, 1 << 8); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2694 | } |
| 2695 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2696 | /** |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2697 | * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 |
Martin Roth | f4cb412 | 2015-01-06 10:27:39 -0700 | [diff] [blame] | 2698 | * @param spd_addresses pointer to a list of SPD addresses |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2699 | */ |
Sven Schnelle | 541269b | 2011-02-21 09:39:17 +0000 | [diff] [blame] | 2700 | void sdram_initialize(int boot_path, const u8 *spd_addresses) |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2701 | { |
| 2702 | struct sys_info sysinfo; |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2703 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 2704 | timestamp_add_now(TS_INITRAM_START); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 2705 | printk(BIOS_DEBUG, "Setting up RAM controller.\n"); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2706 | |
| 2707 | memset(&sysinfo, 0, sizeof(sysinfo)); |
| 2708 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2709 | sysinfo.boot_path = boot_path; |
Sven Schnelle | 541269b | 2011-02-21 09:39:17 +0000 | [diff] [blame] | 2710 | sysinfo.spd_addresses = spd_addresses; |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2711 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2712 | /* Look at the type of DIMMs and verify all DIMMs are x8 or x16 width */ |
| 2713 | sdram_get_dram_configuration(&sysinfo); |
| 2714 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 2715 | /* If error, do cold boot */ |
| 2716 | sdram_detect_errors(&sysinfo); |
| 2717 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2718 | /* Program PLL settings */ |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2719 | sdram_program_pll_settings(&sysinfo); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2720 | |
Arthur Heymans | 1853781 | 2016-12-28 21:20:45 +0100 | [diff] [blame] | 2721 | /* |
| 2722 | * Program Graphics Frequency |
| 2723 | * Set core display and render clock on 945GC to the max |
| 2724 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 2725 | if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) |
Arthur Heymans | 1853781 | 2016-12-28 21:20:45 +0100 | [diff] [blame] | 2726 | sdram_program_graphics_frequency(&sysinfo); |
| 2727 | else |
Angel Pons | 3580d81 | 2020-06-11 14:13:33 +0200 | [diff] [blame] | 2728 | pci_write_config16(IGD_DEV, GCFC, 0x0534); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2729 | |
| 2730 | /* Program System Memory Frequency */ |
| 2731 | sdram_program_memory_frequency(&sysinfo); |
| 2732 | |
| 2733 | /* Determine Mode of Operation (Interleaved etc) */ |
| 2734 | sdram_set_channel_mode(&sysinfo); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2735 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2736 | /* Program Clock Crossing values */ |
| 2737 | sdram_program_clock_crossing(); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2738 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2739 | /* Disable fast dispatch */ |
| 2740 | sdram_disable_fast_dispatch(); |
| 2741 | |
| 2742 | /* Enable WIODLL Power Down in ACPI states */ |
Angel Pons | 1d4044a | 2021-03-27 19:11:51 +0100 | [diff] [blame] | 2743 | mchbar_setbits32(C0DMC, 1 << 24); |
| 2744 | mchbar_setbits32(C1DMC, 1 << 24); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2745 | |
| 2746 | /* Program DRAM Row Boundary/Attribute Registers */ |
| 2747 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2748 | /* program row size DRB and set TOLUD */ |
| 2749 | sdram_program_row_boundaries(&sysinfo); |
| 2750 | |
| 2751 | /* program page size DRA */ |
| 2752 | sdram_set_row_attributes(&sysinfo); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2753 | |
| 2754 | /* Program CxBNKARC */ |
| 2755 | sdram_set_bank_architecture(&sysinfo); |
| 2756 | |
| 2757 | /* Program DRAM Timing and Control registers based on SPD */ |
| 2758 | sdram_set_timing_and_control(&sysinfo); |
| 2759 | |
| 2760 | /* On-Die Termination Adjustment */ |
| 2761 | sdram_on_die_termination(&sysinfo); |
| 2762 | |
| 2763 | /* Pre Jedec Initialization */ |
| 2764 | sdram_pre_jedec_initialization(); |
| 2765 | |
| 2766 | /* Perform System Memory IO Initialization */ |
| 2767 | sdram_initialize_system_memory_io(&sysinfo); |
| 2768 | |
| 2769 | /* Perform System Memory IO Buffer Enable */ |
| 2770 | sdram_enable_system_memory_io(&sysinfo); |
| 2771 | |
| 2772 | /* Enable System Memory Clocks */ |
| 2773 | sdram_enable_memory_clocks(&sysinfo); |
| 2774 | |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2775 | if (boot_path == BOOT_PATH_NORMAL) { |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2776 | /* Jedec Initialization sequence */ |
| 2777 | sdram_jedec_enable(&sysinfo); |
| 2778 | } |
| 2779 | |
| 2780 | /* Program Power Management Registers */ |
| 2781 | sdram_power_management(&sysinfo); |
| 2782 | |
| 2783 | /* Post Jedec Init */ |
| 2784 | sdram_post_jedec_initialization(&sysinfo); |
| 2785 | |
| 2786 | /* Program DRAM Throttling */ |
| 2787 | sdram_thermal_management(); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2788 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2789 | /* Normal Operations */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 2790 | sdram_init_complete(); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2791 | |
| 2792 | /* Program Receive Enable Timings */ |
| 2793 | sdram_program_receive_enable(&sysinfo); |
| 2794 | |
| 2795 | /* Enable Periodic RCOMP */ |
| 2796 | sdram_enable_rcomp(); |
| 2797 | |
| 2798 | /* Tell ICH7 that we're done */ |
Angel Pons | e3c68d2 | 2020-06-08 12:09:03 +0200 | [diff] [blame] | 2799 | pci_and_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, (u8)~(1 << 7)); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2800 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 2801 | printk(BIOS_DEBUG, "RAM initialization finished.\n"); |
Stefan Reinauer | 71a3d96 | 2009-07-21 21:44:24 +0000 | [diff] [blame] | 2802 | |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2803 | sdram_setup_processor_side(); |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 2804 | timestamp_add_now(TS_INITRAM_END); |
Stefan Reinauer | 278534d | 2008-10-29 04:51:07 +0000 | [diff] [blame] | 2805 | } |