Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 4 | #include <acpi/acpi.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 6 | #include <stdint.h> |
| 7 | #include <delay.h> |
| 8 | #include <device/device.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <device/pci_ids.h> |
Sumeet R Pawnikar | fa42d56 | 2020-05-08 22:18:09 +0530 | [diff] [blame] | 11 | #include <intelblocks/power_limit.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 12 | #include <vendorcode/google/chromeos/chromeos.h> |
Angel Pons | e866a2f | 2020-10-23 15:54:33 +0200 | [diff] [blame^] | 13 | #include <soc/acpi.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 14 | #include <soc/cpu.h> |
| 15 | #include <soc/iomap.h> |
| 16 | #include <soc/pci_devs.h> |
| 17 | #include <soc/ramstage.h> |
| 18 | #include <soc/systemagent.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 19 | |
Duncan Laurie | 84b9cf4 | 2014-07-31 10:46:57 -0700 | [diff] [blame] | 20 | u8 systemagent_revision(void) |
| 21 | { |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 22 | struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 23 | return pci_read_config8(sa_dev, PCI_REVISION_ID); |
Duncan Laurie | 84b9cf4 | 2014-07-31 10:46:57 -0700 | [diff] [blame] | 24 | } |
| 25 | |
Matt DeVillier | 42d1660 | 2018-07-04 16:32:21 -0500 | [diff] [blame] | 26 | uintptr_t sa_get_tolud_base(void) |
| 27 | { |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 28 | struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
Matt DeVillier | 42d1660 | 2018-07-04 16:32:21 -0500 | [diff] [blame] | 29 | /* Bit 0 is lock bit, not part of address */ |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 30 | return pci_read_config32(sa_dev, TOLUD) & ~1; |
Matt DeVillier | 42d1660 | 2018-07-04 16:32:21 -0500 | [diff] [blame] | 31 | } |
| 32 | |
| 33 | uintptr_t sa_get_gsm_base(void) |
| 34 | { |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 35 | struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
Matt DeVillier | 42d1660 | 2018-07-04 16:32:21 -0500 | [diff] [blame] | 36 | /* Bit 0 is lock bit, not part of address */ |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 37 | return pci_read_config32(sa_dev, BGSM) & ~1; |
Matt DeVillier | 42d1660 | 2018-07-04 16:32:21 -0500 | [diff] [blame] | 38 | } |
| 39 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 40 | static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, |
| 41 | u32 *len) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 42 | { |
| 43 | u32 pciexbar_reg; |
| 44 | |
| 45 | *base = 0; |
| 46 | *len = 0; |
| 47 | |
| 48 | pciexbar_reg = pci_read_config32(dev, index); |
| 49 | |
| 50 | if (!(pciexbar_reg & (1 << 0))) |
| 51 | return 0; |
| 52 | |
| 53 | switch ((pciexbar_reg >> 1) & 3) { |
| 54 | case 0: // 256MB |
| 55 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| |
| 56 | (1 << 28)); |
| 57 | *len = 256 * 1024 * 1024; |
| 58 | return 1; |
| 59 | case 1: // 128M |
| 60 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| |
| 61 | (1 << 28)|(1 << 27)); |
| 62 | *len = 128 * 1024 * 1024; |
| 63 | return 1; |
| 64 | case 2: // 64M |
| 65 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| |
| 66 | (1 << 28)|(1 << 27)|(1 << 26)); |
| 67 | *len = 64 * 1024 * 1024; |
| 68 | return 1; |
| 69 | } |
| 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 74 | static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 75 | { |
| 76 | u32 bar; |
| 77 | |
| 78 | bar = pci_read_config32(dev, index); |
| 79 | |
| 80 | /* If not enabled don't report it. */ |
| 81 | if (!(bar & 0x1)) |
| 82 | return 0; |
| 83 | |
| 84 | /* Knock down the enable bit. */ |
| 85 | *base = bar & ~1; |
| 86 | |
| 87 | return 1; |
| 88 | } |
| 89 | |
| 90 | /* There are special BARs that actually are programmed in the MCHBAR. These |
| 91 | * Intel special features, but they do consume resources that need to be |
| 92 | * accounted for. */ |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 93 | static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 94 | u32 *len) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 95 | { |
| 96 | u32 bar; |
| 97 | |
| 98 | bar = MCHBAR32(index); |
| 99 | |
| 100 | /* If not enabled don't report it. */ |
| 101 | if (!(bar & 0x1)) |
| 102 | return 0; |
| 103 | |
| 104 | /* Knock down the enable bit. */ |
| 105 | *base = bar & ~1; |
| 106 | |
| 107 | return 1; |
| 108 | } |
| 109 | |
| 110 | struct fixed_mmio_descriptor { |
| 111 | unsigned int index; |
| 112 | u32 size; |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 113 | int (*get_resource)(struct device *dev, unsigned int index, |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 114 | u32 *base, u32 *size); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 115 | const char *description; |
| 116 | }; |
| 117 | |
| 118 | struct fixed_mmio_descriptor mc_fixed_resources[] = { |
| 119 | { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, |
| 120 | { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, |
| 121 | { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, |
| 122 | { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, |
| 123 | { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, |
| 124 | { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, |
| 125 | }; |
| 126 | |
| 127 | /* |
| 128 | * Add all known fixed MMIO ranges that hang off the host bridge/memory |
| 129 | * controller device. |
| 130 | */ |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 131 | static void mc_add_fixed_mmio_resources(struct device *dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 132 | { |
| 133 | int i; |
| 134 | |
| 135 | for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { |
| 136 | u32 base; |
| 137 | u32 size; |
| 138 | struct resource *resource; |
| 139 | unsigned int index; |
| 140 | |
| 141 | size = mc_fixed_resources[i].size; |
| 142 | index = mc_fixed_resources[i].index; |
| 143 | if (!mc_fixed_resources[i].get_resource(dev, index, |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 144 | &base, &size)) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 145 | continue; |
| 146 | |
| 147 | resource = new_resource(dev, mc_fixed_resources[i].index); |
| 148 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 149 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 150 | IORESOURCE_ASSIGNED; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 151 | resource->base = base; |
| 152 | resource->size = size; |
| 153 | printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", |
| 154 | __func__, mc_fixed_resources[i].description, index, |
| 155 | (unsigned long)base, (unsigned long)(base + size - 1)); |
| 156 | } |
| 157 | } |
| 158 | |
| 159 | /* Host Memory Map: |
| 160 | * |
| 161 | * +--------------------------+ TOUUD |
| 162 | * | | |
| 163 | * +--------------------------+ 4GiB |
| 164 | * | PCI Address Space | |
| 165 | * +--------------------------+ TOLUD (also maps into MC address space) |
| 166 | * | iGD | |
| 167 | * +--------------------------+ BDSM |
| 168 | * | GTT | |
| 169 | * +--------------------------+ BGSM |
| 170 | * | TSEG | |
| 171 | * +--------------------------+ TSEGMB |
| 172 | * | Usage DRAM | |
| 173 | * +--------------------------+ 0 |
| 174 | * |
| 175 | * Some of the base registers above can be equal making the size of those |
| 176 | * regions 0. The reason is because the memory controller internally subtracts |
| 177 | * the base registers from each other to determine sizes of the regions. In |
| 178 | * other words, the memory map is in a fixed order no matter what. |
| 179 | */ |
| 180 | |
| 181 | struct map_entry { |
| 182 | int reg; |
| 183 | int is_64_bit; |
| 184 | int is_limit; |
| 185 | const char *description; |
| 186 | }; |
| 187 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 188 | static void read_map_entry(struct device *dev, struct map_entry *entry, |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 189 | uint64_t *result) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 190 | { |
| 191 | uint64_t value; |
| 192 | uint64_t mask; |
| 193 | |
| 194 | /* All registers are on a 1MiB granularity. */ |
| 195 | mask = ((1ULL<<20)-1); |
| 196 | mask = ~mask; |
| 197 | |
| 198 | value = 0; |
| 199 | |
| 200 | if (entry->is_64_bit) { |
| 201 | value = pci_read_config32(dev, entry->reg + 4); |
| 202 | value <<= 32; |
| 203 | } |
| 204 | |
| 205 | value |= pci_read_config32(dev, entry->reg); |
| 206 | value &= mask; |
| 207 | |
| 208 | if (entry->is_limit) |
| 209 | value |= ~mask; |
| 210 | |
| 211 | *result = value; |
| 212 | } |
| 213 | |
| 214 | #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ |
| 215 | { \ |
| 216 | .reg = reg_, \ |
| 217 | .is_64_bit = is_64_, \ |
| 218 | .is_limit = is_limit_, \ |
| 219 | .description = desc_, \ |
| 220 | } |
| 221 | |
| 222 | #define MAP_ENTRY_BASE_64(reg_, desc_) \ |
| 223 | MAP_ENTRY(reg_, 1, 0, desc_) |
| 224 | #define MAP_ENTRY_LIMIT_64(reg_, desc_) \ |
| 225 | MAP_ENTRY(reg_, 1, 1, desc_) |
| 226 | #define MAP_ENTRY_BASE_32(reg_, desc_) \ |
| 227 | MAP_ENTRY(reg_, 0, 0, desc_) |
| 228 | |
| 229 | enum { |
| 230 | TOM_REG, |
| 231 | TOUUD_REG, |
| 232 | MESEG_BASE_REG, |
| 233 | MESEG_LIMIT_REG, |
| 234 | REMAP_BASE_REG, |
| 235 | REMAP_LIMIT_REG, |
| 236 | TOLUD_REG, |
| 237 | BGSM_REG, |
| 238 | BDSM_REG, |
| 239 | TSEG_REG, |
| 240 | // Must be last. |
| 241 | NUM_MAP_ENTRIES |
| 242 | }; |
| 243 | |
| 244 | static struct map_entry memory_map[NUM_MAP_ENTRIES] = { |
| 245 | [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), |
| 246 | [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), |
| 247 | [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), |
| 248 | [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), |
| 249 | [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), |
| 250 | [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), |
| 251 | [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), |
| 252 | [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), |
| 253 | [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), |
Angel Pons | 40b3943 | 2020-06-20 18:06:47 +0200 | [diff] [blame] | 254 | [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 255 | }; |
| 256 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 257 | static void mc_read_map_entries(struct device *dev, uint64_t *values) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 258 | { |
| 259 | int i; |
Lee Leahy | 8a9c7dc | 2017-03-17 10:43:25 -0700 | [diff] [blame] | 260 | for (i = 0; i < NUM_MAP_ENTRIES; i++) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 261 | read_map_entry(dev, &memory_map[i], &values[i]); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 262 | } |
| 263 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 264 | static void mc_report_map_entries(struct device *dev, uint64_t *values) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 265 | { |
| 266 | int i; |
| 267 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 268 | printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", |
| 269 | memory_map[i].description, values[i]); |
| 270 | } |
| 271 | /* One can validate the BDSM and BGSM against the GGC. */ |
| 272 | printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); |
| 273 | } |
| 274 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 275 | static void mc_add_dram_resources(struct device *dev, int *resource_cnt) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 276 | { |
| 277 | unsigned long base_k, size_k; |
| 278 | unsigned long touud_k; |
| 279 | unsigned long index; |
| 280 | struct resource *resource; |
| 281 | uint64_t mc_values[NUM_MAP_ENTRIES]; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 282 | unsigned long dpr_size = 0; |
| 283 | u32 dpr_reg; |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 284 | struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 285 | |
| 286 | /* Read in the MAP registers and report their values. */ |
| 287 | mc_read_map_entries(dev, &mc_values[0]); |
| 288 | mc_report_map_entries(dev, &mc_values[0]); |
| 289 | |
| 290 | /* |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 291 | * DMA Protected Range can be reserved below TSEG for PCODE patch |
| 292 | * or TXT/BootGuard related data. Rather than report a base address |
| 293 | * the DPR register reports the TOP of the region, which is the same |
| 294 | * as TSEG base. The region size is reported in MiB in bits 11:4. |
| 295 | */ |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 296 | dpr_reg = pci_read_config32(sa_dev, DPR); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 297 | if (dpr_reg & DPR_EPM) { |
| 298 | dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; |
| 299 | printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); |
| 300 | } |
| 301 | |
| 302 | /* |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 303 | * These are the host memory ranges that should be added: |
| 304 | * - 0 -> 0xa0000: cacheable |
| 305 | * - 0xc0000 -> TSEG : cacheable |
| 306 | * - TESG -> BGSM: cacheable with standard MTRRs and reserved |
| 307 | * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved |
| 308 | * - 4GiB -> TOUUD: cacheable |
| 309 | * |
| 310 | * The default SMRAM space is reserved so that the range doesn't |
| 311 | * have to be saved during S3 Resume. Once marked reserved the OS |
| 312 | * cannot use the memory. This is a bit of an odd place to reserve |
| 313 | * the region, but the CPU devices don't have dev_ops->read_resources() |
| 314 | * called on them. |
| 315 | * |
| 316 | * The range 0xa0000 -> 0xc0000 does not have any resources |
| 317 | * associated with it to handle legacy VGA memory. If this range |
| 318 | * is not omitted the mtrr code will setup the area as cacheable |
| 319 | * causing VGA access to not work. |
| 320 | * |
| 321 | * The TSEG region is mapped as cacheable so that one can perform |
| 322 | * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes |
| 323 | * precedence over the existing MTRRs covering this region. |
| 324 | * |
| 325 | * It should be noted that cacheable entry types need to be added in |
| 326 | * order. The reason is that the current MTRR code assumes this and |
| 327 | * falls over itself if it isn't. |
| 328 | * |
| 329 | * The resource index starts low and should not meet or exceed |
| 330 | * PCI_BASE_ADDRESS_0. |
| 331 | */ |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 332 | index = *resource_cnt; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 333 | |
| 334 | /* 0 - > 0xa0000 */ |
| 335 | base_k = 0; |
| 336 | size_k = (0xa0000 >> 10) - base_k; |
| 337 | ram_resource(dev, index++, base_k, size_k); |
| 338 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 339 | /* 0xc0000 -> TSEG - DPR */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 340 | base_k = 0xc0000 >> 10; |
| 341 | size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 342 | size_k -= dpr_size >> 10; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 343 | ram_resource(dev, index++, base_k, size_k); |
| 344 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 345 | /* TSEG - DPR -> BGSM */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 346 | resource = new_resource(dev, index++); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 347 | resource->base = mc_values[TSEG_REG] - dpr_size; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 348 | resource->size = mc_values[BGSM_REG] - resource->base; |
| 349 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 350 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 351 | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 352 | |
| 353 | /* BGSM -> TOLUD */ |
| 354 | resource = new_resource(dev, index++); |
| 355 | resource->base = mc_values[BGSM_REG]; |
| 356 | resource->size = mc_values[TOLUD_REG] - resource->base; |
| 357 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 358 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 359 | IORESOURCE_ASSIGNED; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 360 | |
| 361 | /* 4GiB -> TOUUD */ |
| 362 | base_k = 4096 * 1024; /* 4GiB */ |
| 363 | touud_k = mc_values[TOUUD_REG] >> 10; |
| 364 | size_k = touud_k - base_k; |
| 365 | if (touud_k > base_k) |
| 366 | ram_resource(dev, index++, base_k, size_k); |
| 367 | |
| 368 | /* Reserve everything between A segment and 1MB: |
| 369 | * |
| 370 | * 0xa0000 - 0xbffff: legacy VGA |
| 371 | * 0xc0000 - 0xfffff: RAM |
| 372 | */ |
| 373 | mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); |
| 374 | reserved_ram_resource(dev, index++, (0xc0000 >> 10), |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 375 | (0x100000 - 0xc0000) >> 10); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 376 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 377 | if (CONFIG(CHROMEOS)) |
Frans Hendriks | ef05dc8 | 2018-11-27 10:35:16 +0100 | [diff] [blame] | 378 | chromeos_reserve_ram_oops(dev, index++); |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 379 | |
| 380 | *resource_cnt = index; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 381 | } |
| 382 | |
Elyes HAOUAS | 040aff2 | 2018-05-27 16:30:36 +0200 | [diff] [blame] | 383 | static void systemagent_read_resources(struct device *dev) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 384 | { |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 385 | int index = 0; |
| 386 | const bool vtd_capable = |
| 387 | !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); |
| 388 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 389 | /* Read standard PCI resources. */ |
| 390 | pci_dev_read_resources(dev); |
| 391 | |
| 392 | /* Add all fixed MMIO resources. */ |
| 393 | mc_add_fixed_mmio_resources(dev); |
| 394 | |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 395 | /* Add VT-d MMIO resources if capable */ |
| 396 | if (vtd_capable) { |
| 397 | mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, |
| 398 | GFXVT_BASE_SIZE / KiB); |
| 399 | mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, |
| 400 | VTVC0_BASE_SIZE / KiB); |
| 401 | } |
| 402 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 403 | /* Calculate and add DRAM resources. */ |
Matt DeVillier | 81a6f10 | 2018-02-19 17:33:48 -0600 | [diff] [blame] | 404 | mc_add_dram_resources(dev, &index); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 405 | } |
| 406 | |
| 407 | static void systemagent_init(struct device *dev) |
| 408 | { |
Sumeet R Pawnikar | fa42d56 | 2020-05-08 22:18:09 +0530 | [diff] [blame] | 409 | struct soc_power_limits_config *config; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 410 | u8 bios_reset_cpl, pair; |
| 411 | |
| 412 | /* Enable Power Aware Interrupt Routing */ |
| 413 | pair = MCHBAR8(MCH_PAIR); |
| 414 | pair &= ~0x7; /* Clear 2:0 */ |
| 415 | pair |= 0x4; /* Fixed Priority */ |
| 416 | MCHBAR8(MCH_PAIR) = pair; |
| 417 | |
| 418 | /* |
| 419 | * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU |
| 420 | * that BIOS has initialized memory and power management |
| 421 | */ |
| 422 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
| 423 | bios_reset_cpl |= 3; |
| 424 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 425 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 426 | |
| 427 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 428 | mdelay(1); |
Sumeet R Pawnikar | fa42d56 | 2020-05-08 22:18:09 +0530 | [diff] [blame] | 429 | config = config_of_soc(); |
| 430 | set_power_limits(MOBILE_SKU_PL1_TIME_SEC, config); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 431 | } |
| 432 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 433 | static struct device_operations systemagent_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 434 | .read_resources = systemagent_read_resources, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 435 | .acpi_fill_ssdt = generate_cpu_entries, |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 436 | .set_resources = pci_dev_set_resources, |
| 437 | .enable_resources = pci_dev_enable_resources, |
| 438 | .init = systemagent_init, |
Angel Pons | cb2080f | 2020-10-23 15:45:44 +0200 | [diff] [blame] | 439 | .ops_pci = &pci_dev_ops_pci, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 440 | }; |
| 441 | |
| 442 | static const unsigned short systemagent_ids[] = { |
| 443 | 0x0a04, /* Haswell ULT */ |
| 444 | 0x1604, /* Broadwell-U/Y */ |
| 445 | 0x1610, /* Broadwell-H Desktop */ |
| 446 | 0x1614, /* Broadwell-H Mobile */ |
| 447 | 0 |
| 448 | }; |
| 449 | |
| 450 | static const struct pci_driver systemagent_driver __pci_driver = { |
| 451 | .ops = &systemagent_ops, |
| 452 | .vendor = PCI_VENDOR_ID_INTEL, |
| 453 | .devices = systemagent_ids |
| 454 | }; |
Angel Pons | e866a2f | 2020-10-23 15:54:33 +0200 | [diff] [blame^] | 455 | |
| 456 | static struct device_operations pci_domain_ops = { |
| 457 | .read_resources = &pci_domain_read_resources, |
| 458 | .set_resources = &pci_domain_set_resources, |
| 459 | .scan_bus = &pci_domain_scan_bus, |
| 460 | #if CONFIG(HAVE_ACPI_TABLES) |
| 461 | .write_acpi_tables = &northbridge_write_acpi_tables, |
| 462 | #endif |
| 463 | }; |
| 464 | |
| 465 | static struct device_operations cpu_bus_ops = { |
| 466 | .read_resources = noop_read_resources, |
| 467 | .set_resources = noop_set_resources, |
| 468 | .init = &broadwell_init_cpus, |
| 469 | }; |
| 470 | |
| 471 | static void broadwell_enable(struct device *dev) |
| 472 | { |
| 473 | /* Set the operations if it is a special bus type */ |
| 474 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 475 | dev->ops = &pci_domain_ops; |
| 476 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 477 | dev->ops = &cpu_bus_ops; |
| 478 | } else if (dev->path.type == DEVICE_PATH_PCI) { |
| 479 | /* Handle PCH device enable */ |
| 480 | if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && |
| 481 | (dev->ops == NULL || dev->ops->enable == NULL)) { |
| 482 | broadwell_pch_enable_dev(dev); |
| 483 | } |
| 484 | } |
| 485 | } |
| 486 | |
| 487 | struct chip_operations soc_intel_broadwell_ops = { |
| 488 | CHIP_NAME("Intel Broadwell") |
| 489 | .enable_dev = &broadwell_enable, |
| 490 | .init = &broadwell_init_pre_device, |
| 491 | }; |