Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <arch/acpi.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <stdint.h> |
| 25 | #include <delay.h> |
| 26 | #include <device/device.h> |
| 27 | #include <device/pci.h> |
| 28 | #include <device/pci_ids.h> |
| 29 | #include <stdlib.h> |
| 30 | #include <string.h> |
| 31 | #include <cbmem.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 32 | #include <vendorcode/google/chromeos/chromeos.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame^] | 33 | #include <soc/cpu.h> |
| 34 | #include <soc/iomap.h> |
| 35 | #include <soc/pci_devs.h> |
| 36 | #include <soc/ramstage.h> |
| 37 | #include <soc/systemagent.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 38 | |
Duncan Laurie | 84b9cf4 | 2014-07-31 10:46:57 -0700 | [diff] [blame] | 39 | u8 systemagent_revision(void) |
| 40 | { |
| 41 | return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); |
| 42 | } |
| 43 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 44 | static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) |
| 45 | { |
| 46 | u32 pciexbar_reg; |
| 47 | |
| 48 | *base = 0; |
| 49 | *len = 0; |
| 50 | |
| 51 | pciexbar_reg = pci_read_config32(dev, index); |
| 52 | |
| 53 | if (!(pciexbar_reg & (1 << 0))) |
| 54 | return 0; |
| 55 | |
| 56 | switch ((pciexbar_reg >> 1) & 3) { |
| 57 | case 0: // 256MB |
| 58 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| |
| 59 | (1 << 28)); |
| 60 | *len = 256 * 1024 * 1024; |
| 61 | return 1; |
| 62 | case 1: // 128M |
| 63 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| |
| 64 | (1 << 28)|(1 << 27)); |
| 65 | *len = 128 * 1024 * 1024; |
| 66 | return 1; |
| 67 | case 2: // 64M |
| 68 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| |
| 69 | (1 << 28)|(1 << 27)|(1 << 26)); |
| 70 | *len = 64 * 1024 * 1024; |
| 71 | return 1; |
| 72 | } |
| 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) |
| 78 | { |
| 79 | u32 bar; |
| 80 | |
| 81 | bar = pci_read_config32(dev, index); |
| 82 | |
| 83 | /* If not enabled don't report it. */ |
| 84 | if (!(bar & 0x1)) |
| 85 | return 0; |
| 86 | |
| 87 | /* Knock down the enable bit. */ |
| 88 | *base = bar & ~1; |
| 89 | |
| 90 | return 1; |
| 91 | } |
| 92 | |
| 93 | /* There are special BARs that actually are programmed in the MCHBAR. These |
| 94 | * Intel special features, but they do consume resources that need to be |
| 95 | * accounted for. */ |
| 96 | static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, |
| 97 | u32 *len) |
| 98 | { |
| 99 | u32 bar; |
| 100 | |
| 101 | bar = MCHBAR32(index); |
| 102 | |
| 103 | /* If not enabled don't report it. */ |
| 104 | if (!(bar & 0x1)) |
| 105 | return 0; |
| 106 | |
| 107 | /* Knock down the enable bit. */ |
| 108 | *base = bar & ~1; |
| 109 | |
| 110 | return 1; |
| 111 | } |
| 112 | |
| 113 | struct fixed_mmio_descriptor { |
| 114 | unsigned int index; |
| 115 | u32 size; |
| 116 | int (*get_resource)(device_t dev, unsigned int index, |
| 117 | u32 *base, u32 *size); |
| 118 | const char *description; |
| 119 | }; |
| 120 | |
| 121 | struct fixed_mmio_descriptor mc_fixed_resources[] = { |
| 122 | { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, |
| 123 | { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, |
| 124 | { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, |
| 125 | { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, |
| 126 | { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, |
| 127 | { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, |
| 128 | }; |
| 129 | |
| 130 | /* |
| 131 | * Add all known fixed MMIO ranges that hang off the host bridge/memory |
| 132 | * controller device. |
| 133 | */ |
| 134 | static void mc_add_fixed_mmio_resources(device_t dev) |
| 135 | { |
| 136 | int i; |
| 137 | |
| 138 | for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { |
| 139 | u32 base; |
| 140 | u32 size; |
| 141 | struct resource *resource; |
| 142 | unsigned int index; |
| 143 | |
| 144 | size = mc_fixed_resources[i].size; |
| 145 | index = mc_fixed_resources[i].index; |
| 146 | if (!mc_fixed_resources[i].get_resource(dev, index, |
| 147 | &base, &size)) |
| 148 | continue; |
| 149 | |
| 150 | resource = new_resource(dev, mc_fixed_resources[i].index); |
| 151 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 152 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 153 | IORESOURCE_ASSIGNED; |
| 154 | resource->base = base; |
| 155 | resource->size = size; |
| 156 | printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", |
| 157 | __func__, mc_fixed_resources[i].description, index, |
| 158 | (unsigned long)base, (unsigned long)(base + size - 1)); |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | /* Host Memory Map: |
| 163 | * |
| 164 | * +--------------------------+ TOUUD |
| 165 | * | | |
| 166 | * +--------------------------+ 4GiB |
| 167 | * | PCI Address Space | |
| 168 | * +--------------------------+ TOLUD (also maps into MC address space) |
| 169 | * | iGD | |
| 170 | * +--------------------------+ BDSM |
| 171 | * | GTT | |
| 172 | * +--------------------------+ BGSM |
| 173 | * | TSEG | |
| 174 | * +--------------------------+ TSEGMB |
| 175 | * | Usage DRAM | |
| 176 | * +--------------------------+ 0 |
| 177 | * |
| 178 | * Some of the base registers above can be equal making the size of those |
| 179 | * regions 0. The reason is because the memory controller internally subtracts |
| 180 | * the base registers from each other to determine sizes of the regions. In |
| 181 | * other words, the memory map is in a fixed order no matter what. |
| 182 | */ |
| 183 | |
| 184 | struct map_entry { |
| 185 | int reg; |
| 186 | int is_64_bit; |
| 187 | int is_limit; |
| 188 | const char *description; |
| 189 | }; |
| 190 | |
| 191 | static void read_map_entry(device_t dev, struct map_entry *entry, |
| 192 | uint64_t *result) |
| 193 | { |
| 194 | uint64_t value; |
| 195 | uint64_t mask; |
| 196 | |
| 197 | /* All registers are on a 1MiB granularity. */ |
| 198 | mask = ((1ULL<<20)-1); |
| 199 | mask = ~mask; |
| 200 | |
| 201 | value = 0; |
| 202 | |
| 203 | if (entry->is_64_bit) { |
| 204 | value = pci_read_config32(dev, entry->reg + 4); |
| 205 | value <<= 32; |
| 206 | } |
| 207 | |
| 208 | value |= pci_read_config32(dev, entry->reg); |
| 209 | value &= mask; |
| 210 | |
| 211 | if (entry->is_limit) |
| 212 | value |= ~mask; |
| 213 | |
| 214 | *result = value; |
| 215 | } |
| 216 | |
| 217 | #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ |
| 218 | { \ |
| 219 | .reg = reg_, \ |
| 220 | .is_64_bit = is_64_, \ |
| 221 | .is_limit = is_limit_, \ |
| 222 | .description = desc_, \ |
| 223 | } |
| 224 | |
| 225 | #define MAP_ENTRY_BASE_64(reg_, desc_) \ |
| 226 | MAP_ENTRY(reg_, 1, 0, desc_) |
| 227 | #define MAP_ENTRY_LIMIT_64(reg_, desc_) \ |
| 228 | MAP_ENTRY(reg_, 1, 1, desc_) |
| 229 | #define MAP_ENTRY_BASE_32(reg_, desc_) \ |
| 230 | MAP_ENTRY(reg_, 0, 0, desc_) |
| 231 | |
| 232 | enum { |
| 233 | TOM_REG, |
| 234 | TOUUD_REG, |
| 235 | MESEG_BASE_REG, |
| 236 | MESEG_LIMIT_REG, |
| 237 | REMAP_BASE_REG, |
| 238 | REMAP_LIMIT_REG, |
| 239 | TOLUD_REG, |
| 240 | BGSM_REG, |
| 241 | BDSM_REG, |
| 242 | TSEG_REG, |
| 243 | // Must be last. |
| 244 | NUM_MAP_ENTRIES |
| 245 | }; |
| 246 | |
| 247 | static struct map_entry memory_map[NUM_MAP_ENTRIES] = { |
| 248 | [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), |
| 249 | [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), |
| 250 | [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), |
| 251 | [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), |
| 252 | [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), |
| 253 | [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), |
| 254 | [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), |
| 255 | [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), |
| 256 | [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), |
| 257 | [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), |
| 258 | }; |
| 259 | |
| 260 | static void mc_read_map_entries(device_t dev, uint64_t *values) |
| 261 | { |
| 262 | int i; |
| 263 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 264 | read_map_entry(dev, &memory_map[i], &values[i]); |
| 265 | } |
| 266 | } |
| 267 | |
| 268 | static void mc_report_map_entries(device_t dev, uint64_t *values) |
| 269 | { |
| 270 | int i; |
| 271 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 272 | printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", |
| 273 | memory_map[i].description, values[i]); |
| 274 | } |
| 275 | /* One can validate the BDSM and BGSM against the GGC. */ |
| 276 | printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); |
| 277 | } |
| 278 | |
| 279 | static void mc_add_dram_resources(device_t dev) |
| 280 | { |
| 281 | unsigned long base_k, size_k; |
| 282 | unsigned long touud_k; |
| 283 | unsigned long index; |
| 284 | struct resource *resource; |
| 285 | uint64_t mc_values[NUM_MAP_ENTRIES]; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 286 | unsigned long dpr_size = 0; |
| 287 | u32 dpr_reg; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 288 | |
| 289 | /* Read in the MAP registers and report their values. */ |
| 290 | mc_read_map_entries(dev, &mc_values[0]); |
| 291 | mc_report_map_entries(dev, &mc_values[0]); |
| 292 | |
| 293 | /* |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 294 | * DMA Protected Range can be reserved below TSEG for PCODE patch |
| 295 | * or TXT/BootGuard related data. Rather than report a base address |
| 296 | * the DPR register reports the TOP of the region, which is the same |
| 297 | * as TSEG base. The region size is reported in MiB in bits 11:4. |
| 298 | */ |
| 299 | dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR); |
| 300 | if (dpr_reg & DPR_EPM) { |
| 301 | dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; |
| 302 | printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); |
| 303 | } |
| 304 | |
| 305 | /* |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 306 | * These are the host memory ranges that should be added: |
| 307 | * - 0 -> 0xa0000: cacheable |
| 308 | * - 0xc0000 -> TSEG : cacheable |
| 309 | * - TESG -> BGSM: cacheable with standard MTRRs and reserved |
| 310 | * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved |
| 311 | * - 4GiB -> TOUUD: cacheable |
| 312 | * |
| 313 | * The default SMRAM space is reserved so that the range doesn't |
| 314 | * have to be saved during S3 Resume. Once marked reserved the OS |
| 315 | * cannot use the memory. This is a bit of an odd place to reserve |
| 316 | * the region, but the CPU devices don't have dev_ops->read_resources() |
| 317 | * called on them. |
| 318 | * |
| 319 | * The range 0xa0000 -> 0xc0000 does not have any resources |
| 320 | * associated with it to handle legacy VGA memory. If this range |
| 321 | * is not omitted the mtrr code will setup the area as cacheable |
| 322 | * causing VGA access to not work. |
| 323 | * |
| 324 | * The TSEG region is mapped as cacheable so that one can perform |
| 325 | * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes |
| 326 | * precedence over the existing MTRRs covering this region. |
| 327 | * |
| 328 | * It should be noted that cacheable entry types need to be added in |
| 329 | * order. The reason is that the current MTRR code assumes this and |
| 330 | * falls over itself if it isn't. |
| 331 | * |
| 332 | * The resource index starts low and should not meet or exceed |
| 333 | * PCI_BASE_ADDRESS_0. |
| 334 | */ |
| 335 | index = 0; |
| 336 | |
| 337 | /* 0 - > 0xa0000 */ |
| 338 | base_k = 0; |
| 339 | size_k = (0xa0000 >> 10) - base_k; |
| 340 | ram_resource(dev, index++, base_k, size_k); |
| 341 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 342 | /* 0xc0000 -> TSEG - DPR */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 343 | base_k = 0xc0000 >> 10; |
| 344 | size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 345 | size_k -= dpr_size >> 10; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 346 | ram_resource(dev, index++, base_k, size_k); |
| 347 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 348 | /* TSEG - DPR -> BGSM */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 349 | resource = new_resource(dev, index++); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 350 | resource->base = mc_values[TSEG_REG] - dpr_size; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 351 | resource->size = mc_values[BGSM_REG] - resource->base; |
| 352 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 353 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 354 | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; |
| 355 | |
| 356 | /* BGSM -> TOLUD */ |
| 357 | resource = new_resource(dev, index++); |
| 358 | resource->base = mc_values[BGSM_REG]; |
| 359 | resource->size = mc_values[TOLUD_REG] - resource->base; |
| 360 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 361 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 362 | IORESOURCE_ASSIGNED; |
| 363 | |
| 364 | /* 4GiB -> TOUUD */ |
| 365 | base_k = 4096 * 1024; /* 4GiB */ |
| 366 | touud_k = mc_values[TOUUD_REG] >> 10; |
| 367 | size_k = touud_k - base_k; |
| 368 | if (touud_k > base_k) |
| 369 | ram_resource(dev, index++, base_k, size_k); |
| 370 | |
| 371 | /* Reserve everything between A segment and 1MB: |
| 372 | * |
| 373 | * 0xa0000 - 0xbffff: legacy VGA |
| 374 | * 0xc0000 - 0xfffff: RAM |
| 375 | */ |
| 376 | mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); |
| 377 | reserved_ram_resource(dev, index++, (0xc0000 >> 10), |
| 378 | (0x100000 - 0xc0000) >> 10); |
| 379 | |
| 380 | chromeos_reserve_ram_oops(dev, index++); |
| 381 | } |
| 382 | |
| 383 | static void systemagent_read_resources(device_t dev) |
| 384 | { |
| 385 | /* Read standard PCI resources. */ |
| 386 | pci_dev_read_resources(dev); |
| 387 | |
| 388 | /* Add all fixed MMIO resources. */ |
| 389 | mc_add_fixed_mmio_resources(dev); |
| 390 | |
| 391 | /* Calculate and add DRAM resources. */ |
| 392 | mc_add_dram_resources(dev); |
| 393 | } |
| 394 | |
| 395 | static void systemagent_init(struct device *dev) |
| 396 | { |
| 397 | u8 bios_reset_cpl, pair; |
| 398 | |
| 399 | /* Enable Power Aware Interrupt Routing */ |
| 400 | pair = MCHBAR8(MCH_PAIR); |
| 401 | pair &= ~0x7; /* Clear 2:0 */ |
| 402 | pair |= 0x4; /* Fixed Priority */ |
| 403 | MCHBAR8(MCH_PAIR) = pair; |
| 404 | |
| 405 | /* |
| 406 | * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU |
| 407 | * that BIOS has initialized memory and power management |
| 408 | */ |
| 409 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
| 410 | bios_reset_cpl |= 3; |
| 411 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 412 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 413 | |
| 414 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 415 | mdelay(1); |
| 416 | set_power_limits(28); |
| 417 | } |
| 418 | |
Vladimir Serbinenko | b219da8 | 2014-11-09 03:29:30 +0100 | [diff] [blame] | 419 | unsigned long acpi_fill_slit(unsigned long current) |
| 420 | { |
| 421 | // Not implemented |
| 422 | return current; |
| 423 | } |
| 424 | |
| 425 | unsigned long acpi_fill_srat(unsigned long current) |
| 426 | { |
| 427 | /* No NUMA, no SRAT */ |
| 428 | return current; |
| 429 | } |
| 430 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 431 | static struct device_operations systemagent_ops = { |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 432 | .read_resources = &systemagent_read_resources, |
| 433 | .acpi_fill_ssdt_generator = &generate_cpu_entries, |
| 434 | .set_resources = &pci_dev_set_resources, |
| 435 | .enable_resources = &pci_dev_enable_resources, |
| 436 | .init = &systemagent_init, |
Marc Jones | a6354a1 | 2014-12-26 22:11:14 -0700 | [diff] [blame] | 437 | .ops_pci = &broadwell_pci_ops, |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 438 | }; |
| 439 | |
| 440 | static const unsigned short systemagent_ids[] = { |
| 441 | 0x0a04, /* Haswell ULT */ |
| 442 | 0x1604, /* Broadwell-U/Y */ |
| 443 | 0x1610, /* Broadwell-H Desktop */ |
| 444 | 0x1614, /* Broadwell-H Mobile */ |
| 445 | 0 |
| 446 | }; |
| 447 | |
| 448 | static const struct pci_driver systemagent_driver __pci_driver = { |
| 449 | .ops = &systemagent_ops, |
| 450 | .vendor = PCI_VENDOR_ID_INTEL, |
| 451 | .devices = systemagent_ids |
| 452 | }; |