Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Chromium OS Authors |
| 5 | * Copyright (C) 2013 Vladimir Serbinenko |
| 6 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <console/console.h> |
| 20 | #include <delay.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <string.h> |
| 25 | #include <device/pci_ops.h> |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 26 | #include <commonlib/helpers.h> |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 27 | #include <cbmem.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 28 | |
| 29 | #include "drivers/intel/gma/i915_reg.h" |
| 30 | #include "chip.h" |
| 31 | #include "x4x.h" |
| 32 | #include <drivers/intel/gma/intel_bios.h> |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 33 | #include <drivers/intel/gma/edid.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 34 | #include <drivers/intel/gma/i915.h> |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 35 | #include <drivers/intel/gma/opregion.h> |
Nico Huber | f2dd049 | 2017-10-29 15:42:44 +0100 | [diff] [blame] | 36 | #include <drivers/intel/gma/libgfxinit.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 37 | #include <pc80/vga.h> |
| 38 | #include <pc80/vga_io.h> |
| 39 | |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 40 | #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX) |
| 41 | #include <southbridge/intel/i82801jx/nvs.h> |
| 42 | #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) |
| 43 | #include <southbridge/intel/i82801gx/nvs.h> |
| 44 | #endif |
| 45 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 46 | #define BASE_FREQUENCY 96000 |
| 47 | |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 48 | uintptr_t gma_get_gnvs_aslb(const void *gnvs) |
| 49 | { |
| 50 | const global_nvs_t *gnvs_ptr = gnvs; |
| 51 | return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); |
| 52 | } |
| 53 | |
| 54 | void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) |
| 55 | { |
| 56 | global_nvs_t *gnvs_ptr = gnvs; |
| 57 | if (gnvs_ptr) |
| 58 | gnvs_ptr->aslb = aslb; |
| 59 | } |
| 60 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 61 | static u8 edid_is_present(u8 *edid, u32 edid_size) |
| 62 | { |
| 63 | u32 i; |
| 64 | for (i = 0; i < edid_size; i++) { |
| 65 | if (*(edid + i) != 0) |
| 66 | return 1; |
| 67 | } |
| 68 | return 0; |
| 69 | } |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 70 | static void intel_gma_init(const struct northbridge_intel_x4x_config *info, |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 71 | u8 *mmio, u32 physbase, u16 piobase, u32 lfb) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 72 | { |
| 73 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 74 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 75 | int i; |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 76 | u8 edid_data[128]; |
| 77 | struct edid edid; |
| 78 | struct edid_mode *mode; |
| 79 | u8 edid_is_found; |
| 80 | |
| 81 | /* Initialise mode variables for 640 x 480 @ 60Hz */ |
| 82 | u32 hactive = 640, vactive = 480; |
| 83 | u32 right_border = 0, bottom_border = 0; |
| 84 | int hpolarity = 0, vpolarity = 0; |
| 85 | u32 hsync = 96, vsync = 2; |
| 86 | u32 hblank = 160, vblank = 45; |
| 87 | u32 hfront_porch = 16, vfront_porch = 10; |
| 88 | u32 target_frequency = 25175; |
| 89 | |
| 90 | u32 err_most = 0xffffffff; |
| 91 | u32 pixel_p1 = 1; |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 92 | u32 pixel_p2; |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 93 | u32 pixel_n = 1; |
| 94 | u32 pixel_m1 = 1; |
| 95 | u32 pixel_m2 = 1; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 96 | |
Arthur Heymans | c3cbe94 | 2017-08-06 16:00:18 +0200 | [diff] [blame] | 97 | u8 vga_gmbus = GMBUS_PORT_VGADDC; |
| 98 | |
| 99 | if (IS_ENABLED(CONFIG_GFX_GMA_ANALOG_I2C_HDMI_B)) |
| 100 | vga_gmbus = GMBUS_PORT_DPB; |
| 101 | else if (IS_ENABLED(CONFIG_GFX_GMA_ANALOG_I2C_HDMI_C)) |
| 102 | vga_gmbus = GMBUS_PORT_DPC; |
| 103 | else if (IS_ENABLED(CONFIG_GFX_GMA_ANALOG_I2C_HDMI_D)) |
| 104 | vga_gmbus = GMBUS_PORT_DPD; |
| 105 | |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 106 | vga_gr_write(0x18, 0); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 107 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 108 | /* Set up GTT */ |
| 109 | for (i = 0; i < 0x1000; i++) { |
| 110 | outl((i << 2) | 1, piobase); |
| 111 | outl(physbase + (i << 12) + 1, piobase + 4); |
| 112 | } |
| 113 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 114 | write32(mmio + VGA0, 0x31108); |
| 115 | write32(mmio + VGA1, 0x31406); |
| 116 | |
| 117 | write32(mmio + ADPA, ADPA_DAC_ENABLE |
| 118 | | ADPA_PIPE_A_SELECT |
| 119 | | ADPA_CRT_HOTPLUG_MONITOR_COLOR |
| 120 | | ADPA_CRT_HOTPLUG_ENABLE |
| 121 | | ADPA_USE_VGA_HVPOLARITY |
| 122 | | ADPA_VSYNC_CNTL_ENABLE |
| 123 | | ADPA_HSYNC_CNTL_ENABLE |
| 124 | | ADPA_DPMS_ON |
| 125 | ); |
| 126 | |
| 127 | write32(mmio + 0x7041c, 0x0); |
| 128 | write32(mmio + DPLL_MD(0), 0x3); |
| 129 | write32(mmio + DPLL_MD(1), 0x3); |
| 130 | |
| 131 | vga_misc_write(0x67); |
| 132 | |
| 133 | const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, |
| 134 | 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, |
| 135 | 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, |
| 136 | 0xff |
| 137 | }; |
| 138 | vga_cr_write(0x11, 0); |
| 139 | |
| 140 | for (i = 0; i <= 0x18; i++) |
| 141 | vga_cr_write(i, cr[i]); |
| 142 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 143 | udelay(1); |
| 144 | |
Arthur Heymans | c3cbe94 | 2017-08-06 16:00:18 +0200 | [diff] [blame] | 145 | /* |
| 146 | * TODO: check if it is actually an analog display. |
| 147 | * No harm is done but the console output could be confusing. |
| 148 | */ |
| 149 | intel_gmbus_read_edid(mmio + GMBUS0, vga_gmbus, 0x50, edid_data, |
Arthur Heymans | 7141ff3 | 2016-10-10 17:49:00 +0200 | [diff] [blame] | 150 | sizeof(edid_data)); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 151 | intel_gmbus_stop(mmio + GMBUS0); |
| 152 | decode_edid(edid_data, |
| 153 | sizeof(edid_data), &edid); |
| 154 | mode = &edid.mode; |
| 155 | |
| 156 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 157 | /* Disable screen memory to prevent garbage from appearing. */ |
| 158 | vga_sr_write(1, vga_sr_read(1) | 0x20); |
| 159 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 160 | edid_is_found = edid_is_present(edid_data, sizeof(edid_data)); |
| 161 | if (edid_is_found) { |
| 162 | printk(BIOS_DEBUG, "EDID is not null"); |
| 163 | hactive = edid.x_resolution; |
| 164 | vactive = edid.y_resolution; |
| 165 | right_border = mode->hborder; |
| 166 | bottom_border = mode->vborder; |
| 167 | hpolarity = (mode->phsync == '-'); |
| 168 | vpolarity = (mode->pvsync == '-'); |
| 169 | vsync = mode->vspw; |
| 170 | hsync = mode->hspw; |
| 171 | vblank = mode->vbl; |
| 172 | hblank = mode->hbl; |
| 173 | hfront_porch = mode->hso; |
| 174 | vfront_porch = mode->vso; |
| 175 | target_frequency = mode->pixel_clock; |
| 176 | } else |
| 177 | printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode"); |
| 178 | |
Nico Huber | 6d8266b | 2017-05-20 16:46:01 +0200 | [diff] [blame] | 179 | if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 180 | vga_sr_write(1, 1); |
| 181 | vga_sr_write(0x2, 0xf); |
| 182 | vga_sr_write(0x3, 0x0); |
| 183 | vga_sr_write(0x4, 0xe); |
| 184 | vga_gr_write(0, 0x0); |
| 185 | vga_gr_write(1, 0x0); |
| 186 | vga_gr_write(2, 0x0); |
| 187 | vga_gr_write(3, 0x0); |
| 188 | vga_gr_write(4, 0x0); |
| 189 | vga_gr_write(5, 0x0); |
| 190 | vga_gr_write(6, 0x5); |
| 191 | vga_gr_write(7, 0xf); |
| 192 | vga_gr_write(0x10, 0x1); |
| 193 | vga_gr_write(0x11, 0); |
| 194 | |
| 195 | edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; |
| 196 | |
| 197 | write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE |
| 198 | | DISPPLANE_BGRX888); |
| 199 | write32(mmio + DSPADDR(0), 0); |
| 200 | write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); |
| 201 | write32(mmio + DSPSURF(0), 0); |
| 202 | for (i = 0; i < 0x100; i++) |
| 203 | write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); |
| 204 | } else { |
| 205 | vga_textmode_init(); |
| 206 | } |
| 207 | |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 208 | pixel_p2 = target_frequency <= 225000 ? 10 : 5; |
| 209 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 210 | u32 candn, candm1, candm2, candp1; |
| 211 | for (candn = 1; candn <= 4; candn++) { |
| 212 | for (candm1 = 23; candm1 >= 16; candm1--) { |
| 213 | for (candm2 = 11; candm2 >= 5; candm2--) { |
| 214 | for (candp1 = 8; candp1 >= 1; candp1--) { |
| 215 | u32 m = 5 * (candm1 + 2) + (candm2 + 2); |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 216 | u32 p = candp1 * pixel_p2; |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 217 | u32 vco = DIV_ROUND_CLOSEST( |
| 218 | BASE_FREQUENCY * m, candn + 2); |
| 219 | u32 dot = DIV_ROUND_CLOSEST(vco, p); |
Arthur Heymans | 75f9131 | 2016-10-12 01:04:28 +0200 | [diff] [blame] | 220 | u32 this_err = MAX(dot, target_frequency) - |
| 221 | MIN(dot, target_frequency); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 222 | if (this_err < err_most) { |
| 223 | err_most = this_err; |
| 224 | pixel_n = candn; |
| 225 | pixel_m1 = candm1; |
| 226 | pixel_m2 = candm2; |
| 227 | pixel_p1 = candp1; |
| 228 | } |
| 229 | } |
| 230 | } |
| 231 | } |
| 232 | } |
| 233 | |
| 234 | if (err_most == 0xffffffff) { |
| 235 | printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); |
| 236 | return; |
| 237 | } |
| 238 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 239 | printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", |
| 240 | hactive, vactive); |
| 241 | printk(BIOS_DEBUG, "Borders %d x %d\n", |
| 242 | right_border, bottom_border); |
| 243 | printk(BIOS_DEBUG, "Blank %d x %d\n", |
| 244 | hblank, vblank); |
| 245 | printk(BIOS_DEBUG, "Sync %d x %d\n", |
| 246 | hsync, vsync); |
| 247 | printk(BIOS_DEBUG, "Front porch %d x %d\n", |
| 248 | hfront_porch, vfront_porch); |
| 249 | printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock |
| 250 | ? "Spread spectrum clock\n" : "DREF clock\n")); |
| 251 | printk(BIOS_DEBUG, "Polarities %d, %d\n", |
| 252 | hpolarity, vpolarity); |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 253 | printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", |
| 254 | pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 255 | printk(BIOS_DEBUG, "Pixel clock %d kHz\n", |
| 256 | BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 257 | (pixel_n + 2) / (pixel_p1 * pixel_p2)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 258 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 259 | mdelay(1); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 260 | write32(mmio + FP0(0), (pixel_n << 16) |
| 261 | | (pixel_m1 << 8) | pixel_m2); |
| 262 | write32(mmio + DPLL(0), DPLL_VCO_ENABLE |
| 263 | | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 264 | | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : |
| 265 | DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 266 | | (0x10000 << (pixel_p1 - 1)) |
| 267 | | (6 << 9)); |
| 268 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 269 | mdelay(1); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 270 | write32(mmio + DPLL(0), DPLL_VCO_ENABLE |
| 271 | | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 272 | | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : |
| 273 | DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 274 | | (0x10000 << (pixel_p1 - 1)) |
| 275 | | (6 << 9)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 276 | |
| 277 | write32(mmio + ADPA, ADPA_DAC_ENABLE |
| 278 | | ADPA_PIPE_A_SELECT |
| 279 | | ADPA_CRT_HOTPLUG_MONITOR_COLOR |
| 280 | | ADPA_CRT_HOTPLUG_ENABLE |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 281 | | ADPA_VSYNC_CNTL_ENABLE |
| 282 | | ADPA_HSYNC_CNTL_ENABLE |
| 283 | | ADPA_DPMS_ON |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 284 | | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : |
| 285 | ADPA_VSYNC_ACTIVE_HIGH) |
| 286 | | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : |
| 287 | ADPA_HSYNC_ACTIVE_HIGH)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 288 | |
| 289 | write32(mmio + HTOTAL(0), |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 290 | ((hactive + right_border + hblank - 1) << 16) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 291 | | (hactive - 1)); |
| 292 | write32(mmio + HBLANK(0), |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 293 | ((hactive + right_border + hblank - 1) << 16) |
| 294 | | (hactive + right_border - 1)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 295 | write32(mmio + HSYNC(0), |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 296 | ((hactive + right_border + hfront_porch + hsync - 1) << 16) |
| 297 | | (hactive + right_border + hfront_porch - 1)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 298 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 299 | write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 300 | | (vactive - 1)); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 301 | write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) |
| 302 | | (vactive + bottom_border - 1)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 303 | write32(mmio + VSYNC(0), |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 304 | ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) |
| 305 | | (vactive + bottom_border + vfront_porch - 1)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 306 | |
| 307 | write32(mmio + PIPECONF(0), PIPECONF_DISABLE); |
| 308 | |
| 309 | write32(mmio + PF_WIN_POS(0), 0); |
Nico Huber | 6d8266b | 2017-05-20 16:46:01 +0200 | [diff] [blame] | 310 | if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 311 | write32(mmio + PIPESRC(0), ((hactive - 1) << 16) |
| 312 | | (vactive - 1)); |
| 313 | write32(mmio + PF_CTL(0), 0); |
| 314 | write32(mmio + PF_WIN_SZ(0), 0); |
| 315 | write32(mmio + PFIT_CONTROL, 0); |
| 316 | } else { |
| 317 | write32(mmio + PIPESRC(0), (639 << 16) | 399); |
| 318 | write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); |
| 319 | write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); |
| 320 | write32(mmio + PFIT_CONTROL, 0x80000000); |
| 321 | } |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 322 | |
| 323 | mdelay(1); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 324 | write32(mmio + PIPECONF(0), PIPECONF_BPP_6); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 325 | write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 326 | write32(mmio + PIPECONF(0), PIPECONF_ENABLE |
| 327 | | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 328 | |
Nico Huber | 6d8266b | 2017-05-20 16:46:01 +0200 | [diff] [blame] | 329 | if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 330 | write32(mmio + VGACNTRL, VGA_DISP_DISABLE); |
| 331 | write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE |
| 332 | | DISPPLANE_BGRX888); |
| 333 | mdelay(1); |
| 334 | } else { |
| 335 | write32(mmio + VGACNTRL, 0xc4008e); |
| 336 | } |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 337 | |
| 338 | write32(mmio + ADPA, ADPA_DAC_ENABLE |
| 339 | | ADPA_PIPE_A_SELECT |
| 340 | | ADPA_CRT_HOTPLUG_MONITOR_COLOR |
| 341 | | ADPA_CRT_HOTPLUG_ENABLE |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 342 | | ADPA_VSYNC_CNTL_ENABLE |
| 343 | | ADPA_HSYNC_CNTL_ENABLE |
| 344 | | ADPA_DPMS_ON |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 345 | | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : |
| 346 | ADPA_VSYNC_ACTIVE_HIGH) |
| 347 | | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : |
| 348 | ADPA_HSYNC_ACTIVE_HIGH)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 349 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 350 | write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 351 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 352 | /* Enable screen memory. */ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 353 | vga_sr_write(1, vga_sr_read(1) & ~0x20); |
| 354 | |
| 355 | /* Clear interrupts. */ |
| 356 | write32(mmio + DEIIR, 0xffffffff); |
| 357 | write32(mmio + SDEIIR, 0xffffffff); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 358 | |
Nico Huber | 6d8266b | 2017-05-20 16:46:01 +0200 | [diff] [blame] | 359 | if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 360 | memset((void *) lfb, 0, |
| 361 | hactive * vactive * 4); |
| 362 | set_vbe_mode_info_valid(&edid, lfb); |
| 363 | } |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 364 | } |
| 365 | |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 366 | static void native_init(struct device *dev) |
| 367 | { |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 368 | struct resource *lfb_res; |
| 369 | struct resource *pio_res; |
| 370 | u32 physbase; |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 371 | struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 372 | struct northbridge_intel_x4x_config *conf = dev->chip_info; |
| 373 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 374 | lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 375 | pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); |
| 376 | physbase = pci_read_config32(dev, 0x5c) & ~0xf; |
| 377 | |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 378 | if (gtt_res && gtt_res->base) { |
| 379 | printk(BIOS_SPEW, |
| 380 | "Initializing VGA without OPROM. MMIO 0x%llx\n", |
| 381 | gtt_res->base); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 382 | intel_gma_init(conf, res2mmio(gtt_res, 0, 0), |
| 383 | physbase, pio_res->base, lfb_res->base); |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | /* Linux relies on VBT for panel info. */ |
Arthur Heymans | d3284a6 | 2016-09-25 22:48:00 +0200 | [diff] [blame] | 387 | generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE"); |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 388 | } |
| 389 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 390 | static void gma_func0_init(struct device *dev) |
| 391 | { |
Arthur Heymans | 2e7efe6 | 2017-05-06 18:05:57 +0200 | [diff] [blame] | 392 | u16 reg16, ggc; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 393 | u32 reg32; |
| 394 | |
| 395 | /* IGD needs to be Bus Master */ |
| 396 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 397 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 398 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 399 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 400 | /* configure GMBUSFREQ */ |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 401 | reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 402 | reg16 &= ~0x1ff; |
| 403 | reg16 |= 0xbc; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 404 | pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc, reg16); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 405 | |
Arthur Heymans | 2e7efe6 | 2017-05-06 18:05:57 +0200 | [diff] [blame] | 406 | ggc = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC); |
| 407 | |
| 408 | if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { |
| 409 | if (ggc & (1 << 1)) { |
| 410 | printk(BIOS_DEBUG, "VGA cycles not assigned to IGD. " |
| 411 | "Not running native graphic init.\n"); |
| 412 | return; |
| 413 | } |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 414 | native_init(dev); |
Nico Huber | f2dd049 | 2017-10-29 15:42:44 +0100 | [diff] [blame] | 415 | } else if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { |
| 416 | int lightup_ok; |
| 417 | gma_gfxinit(&lightup_ok); |
Arthur Heymans | 2e7efe6 | 2017-05-06 18:05:57 +0200 | [diff] [blame] | 418 | } else { |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 419 | pci_dev_init(dev); |
Arthur Heymans | 2e7efe6 | 2017-05-06 18:05:57 +0200 | [diff] [blame] | 420 | } |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 421 | |
| 422 | intel_gma_restore_opregion(); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 423 | } |
| 424 | |
Arthur Heymans | c80748c | 2017-02-26 23:04:51 +0100 | [diff] [blame] | 425 | static void gma_func0_disable(struct device *dev) |
| 426 | { |
| 427 | struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 428 | u16 ggc; |
| 429 | |
| 430 | ggc = pci_read_config16(dev_host, D0F0_GGC); |
| 431 | ggc |= (1 << 1); /* VGA cycles to discrete GPU */ |
| 432 | pci_write_config16(dev_host, D0F0_GGC, ggc); |
| 433 | } |
| 434 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 435 | static void gma_set_subsystem(struct device *dev, unsigned int vendor, |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 436 | unsigned int device) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 437 | { |
| 438 | if (!vendor || !device) { |
| 439 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 440 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 441 | } else { |
| 442 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 443 | ((device & 0xffff) << 16) | (vendor & |
| 444 | 0xffff)); |
| 445 | } |
| 446 | } |
| 447 | |
| 448 | const struct i915_gpu_controller_info * |
| 449 | intel_gma_get_controller_info(void) |
| 450 | { |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 451 | struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 452 | if (!dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 453 | return NULL; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 454 | struct northbridge_intel_x4x_config *chip = dev->chip_info; |
| 455 | return &chip->gfx; |
| 456 | } |
| 457 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 458 | static void gma_ssdt(struct device *device) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 459 | { |
| 460 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 461 | if (!gfx) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 462 | return; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 463 | |
| 464 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 465 | } |
| 466 | |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 467 | static unsigned long |
| 468 | gma_write_acpi_tables(struct device *const dev, |
| 469 | unsigned long current, |
| 470 | struct acpi_rsdp *const rsdp) |
| 471 | { |
| 472 | igd_opregion_t *opregion = (igd_opregion_t *)current; |
| 473 | global_nvs_t *gnvs; |
| 474 | |
| 475 | if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) |
| 476 | return current; |
| 477 | |
| 478 | current += sizeof(igd_opregion_t); |
| 479 | |
| 480 | /* GNVS has been already set up */ |
| 481 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 482 | if (gnvs) { |
| 483 | /* IGD OpRegion Base Address */ |
| 484 | gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); |
| 485 | } else { |
| 486 | printk(BIOS_ERR, "Error: GNVS table not found.\n"); |
| 487 | } |
| 488 | |
| 489 | current = acpi_align_current(current); |
| 490 | return current; |
| 491 | } |
| 492 | |
| 493 | static const char *gma_acpi_name(const struct device *dev) |
| 494 | { |
| 495 | return "GFX0"; |
| 496 | } |
| 497 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 498 | static struct pci_operations gma_pci_ops = { |
| 499 | .set_subsystem = gma_set_subsystem, |
| 500 | }; |
| 501 | |
| 502 | static struct device_operations gma_func0_ops = { |
| 503 | .read_resources = pci_dev_read_resources, |
| 504 | .set_resources = pci_dev_set_resources, |
| 505 | .enable_resources = pci_dev_enable_resources, |
| 506 | .acpi_fill_ssdt_generator = gma_ssdt, |
| 507 | .init = gma_func0_init, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 508 | .ops_pci = &gma_pci_ops, |
Arthur Heymans | c80748c | 2017-02-26 23:04:51 +0100 | [diff] [blame] | 509 | .disable = gma_func0_disable, |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 510 | .acpi_name = gma_acpi_name, |
| 511 | .write_acpi_tables = gma_write_acpi_tables, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 512 | }; |
| 513 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 514 | static const unsigned short pci_device_ids[] = { |
Arthur Heymans | 9e70ce0 | 2016-12-16 15:32:32 +0100 | [diff] [blame] | 515 | 0x2e02, /* Eaglelake */ |
| 516 | 0x2e12, /* Q43/Q45 */ |
| 517 | 0x2e22, /* G43/G45 */ |
| 518 | 0x2e32, /* G41 */ |
| 519 | 0x2e42, /* B43 */ |
| 520 | 0x2e92, /* B43_I */ |
| 521 | 0 |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 522 | }; |
| 523 | |
| 524 | static const struct pci_driver gma __pci_driver = { |
| 525 | .ops = &gma_func0_ops, |
| 526 | .vendor = PCI_VENDOR_ID_INTEL, |
| 527 | .devices = pci_device_ids, |
| 528 | }; |