Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Chromium OS Authors |
| 5 | * Copyright (C) 2013 Vladimir Serbinenko |
| 6 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <console/console.h> |
| 20 | #include <delay.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <string.h> |
| 25 | #include <device/pci_ops.h> |
| 26 | #include <cpu/x86/msr.h> |
| 27 | #include <cpu/x86/mtrr.h> |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 28 | #include <commonlib/helpers.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 29 | |
| 30 | #include "drivers/intel/gma/i915_reg.h" |
| 31 | #include "chip.h" |
| 32 | #include "x4x.h" |
| 33 | #include <drivers/intel/gma/intel_bios.h> |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 34 | #include <drivers/intel/gma/edid.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 35 | #include <drivers/intel/gma/i915.h> |
| 36 | #include <pc80/vga.h> |
| 37 | #include <pc80/vga_io.h> |
| 38 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 39 | #define BASE_FREQUENCY 96000 |
| 40 | |
| 41 | static u8 edid_is_present(u8 *edid, u32 edid_size) |
| 42 | { |
| 43 | u32 i; |
| 44 | for (i = 0; i < edid_size; i++) { |
| 45 | if (*(edid + i) != 0) |
| 46 | return 1; |
| 47 | } |
| 48 | return 0; |
| 49 | } |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 50 | static void intel_gma_init(const struct northbridge_intel_x4x_config *info, |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 51 | u8 *mmio, u32 physbase, u16 piobase, u32 lfb) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 52 | { |
| 53 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 54 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 55 | int i; |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 56 | u8 edid_data[128]; |
| 57 | struct edid edid; |
| 58 | struct edid_mode *mode; |
| 59 | u8 edid_is_found; |
| 60 | |
| 61 | /* Initialise mode variables for 640 x 480 @ 60Hz */ |
| 62 | u32 hactive = 640, vactive = 480; |
| 63 | u32 right_border = 0, bottom_border = 0; |
| 64 | int hpolarity = 0, vpolarity = 0; |
| 65 | u32 hsync = 96, vsync = 2; |
| 66 | u32 hblank = 160, vblank = 45; |
| 67 | u32 hfront_porch = 16, vfront_porch = 10; |
| 68 | u32 target_frequency = 25175; |
| 69 | |
| 70 | u32 err_most = 0xffffffff; |
| 71 | u32 pixel_p1 = 1; |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 72 | u32 pixel_p2; |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 73 | u32 pixel_n = 1; |
| 74 | u32 pixel_m1 = 1; |
| 75 | u32 pixel_m2 = 1; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 76 | |
Arthur Heymans | c3cbe94 | 2017-08-06 16:00:18 +0200 | [diff] [blame^] | 77 | u8 vga_gmbus = GMBUS_PORT_VGADDC; |
| 78 | |
| 79 | if (IS_ENABLED(CONFIG_GFX_GMA_ANALOG_I2C_HDMI_B)) |
| 80 | vga_gmbus = GMBUS_PORT_DPB; |
| 81 | else if (IS_ENABLED(CONFIG_GFX_GMA_ANALOG_I2C_HDMI_C)) |
| 82 | vga_gmbus = GMBUS_PORT_DPC; |
| 83 | else if (IS_ENABLED(CONFIG_GFX_GMA_ANALOG_I2C_HDMI_D)) |
| 84 | vga_gmbus = GMBUS_PORT_DPD; |
| 85 | |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 86 | vga_gr_write(0x18, 0); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 87 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 88 | /* Set up GTT */ |
| 89 | for (i = 0; i < 0x1000; i++) { |
| 90 | outl((i << 2) | 1, piobase); |
| 91 | outl(physbase + (i << 12) + 1, piobase + 4); |
| 92 | } |
| 93 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 94 | write32(mmio + VGA0, 0x31108); |
| 95 | write32(mmio + VGA1, 0x31406); |
| 96 | |
| 97 | write32(mmio + ADPA, ADPA_DAC_ENABLE |
| 98 | | ADPA_PIPE_A_SELECT |
| 99 | | ADPA_CRT_HOTPLUG_MONITOR_COLOR |
| 100 | | ADPA_CRT_HOTPLUG_ENABLE |
| 101 | | ADPA_USE_VGA_HVPOLARITY |
| 102 | | ADPA_VSYNC_CNTL_ENABLE |
| 103 | | ADPA_HSYNC_CNTL_ENABLE |
| 104 | | ADPA_DPMS_ON |
| 105 | ); |
| 106 | |
| 107 | write32(mmio + 0x7041c, 0x0); |
| 108 | write32(mmio + DPLL_MD(0), 0x3); |
| 109 | write32(mmio + DPLL_MD(1), 0x3); |
| 110 | |
| 111 | vga_misc_write(0x67); |
| 112 | |
| 113 | const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, |
| 114 | 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, |
| 115 | 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, |
| 116 | 0xff |
| 117 | }; |
| 118 | vga_cr_write(0x11, 0); |
| 119 | |
| 120 | for (i = 0; i <= 0x18; i++) |
| 121 | vga_cr_write(i, cr[i]); |
| 122 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 123 | udelay(1); |
| 124 | |
Arthur Heymans | c3cbe94 | 2017-08-06 16:00:18 +0200 | [diff] [blame^] | 125 | /* |
| 126 | * TODO: check if it is actually an analog display. |
| 127 | * No harm is done but the console output could be confusing. |
| 128 | */ |
| 129 | intel_gmbus_read_edid(mmio + GMBUS0, vga_gmbus, 0x50, edid_data, |
Arthur Heymans | 7141ff3 | 2016-10-10 17:49:00 +0200 | [diff] [blame] | 130 | sizeof(edid_data)); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 131 | intel_gmbus_stop(mmio + GMBUS0); |
| 132 | decode_edid(edid_data, |
| 133 | sizeof(edid_data), &edid); |
| 134 | mode = &edid.mode; |
| 135 | |
| 136 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 137 | /* Disable screen memory to prevent garbage from appearing. */ |
| 138 | vga_sr_write(1, vga_sr_read(1) | 0x20); |
| 139 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 140 | edid_is_found = edid_is_present(edid_data, sizeof(edid_data)); |
| 141 | if (edid_is_found) { |
| 142 | printk(BIOS_DEBUG, "EDID is not null"); |
| 143 | hactive = edid.x_resolution; |
| 144 | vactive = edid.y_resolution; |
| 145 | right_border = mode->hborder; |
| 146 | bottom_border = mode->vborder; |
| 147 | hpolarity = (mode->phsync == '-'); |
| 148 | vpolarity = (mode->pvsync == '-'); |
| 149 | vsync = mode->vspw; |
| 150 | hsync = mode->hspw; |
| 151 | vblank = mode->vbl; |
| 152 | hblank = mode->hbl; |
| 153 | hfront_porch = mode->hso; |
| 154 | vfront_porch = mode->vso; |
| 155 | target_frequency = mode->pixel_clock; |
| 156 | } else |
| 157 | printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode"); |
| 158 | |
Nico Huber | 6d8266b | 2017-05-20 16:46:01 +0200 | [diff] [blame] | 159 | if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 160 | vga_sr_write(1, 1); |
| 161 | vga_sr_write(0x2, 0xf); |
| 162 | vga_sr_write(0x3, 0x0); |
| 163 | vga_sr_write(0x4, 0xe); |
| 164 | vga_gr_write(0, 0x0); |
| 165 | vga_gr_write(1, 0x0); |
| 166 | vga_gr_write(2, 0x0); |
| 167 | vga_gr_write(3, 0x0); |
| 168 | vga_gr_write(4, 0x0); |
| 169 | vga_gr_write(5, 0x0); |
| 170 | vga_gr_write(6, 0x5); |
| 171 | vga_gr_write(7, 0xf); |
| 172 | vga_gr_write(0x10, 0x1); |
| 173 | vga_gr_write(0x11, 0); |
| 174 | |
| 175 | edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; |
| 176 | |
| 177 | write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE |
| 178 | | DISPPLANE_BGRX888); |
| 179 | write32(mmio + DSPADDR(0), 0); |
| 180 | write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); |
| 181 | write32(mmio + DSPSURF(0), 0); |
| 182 | for (i = 0; i < 0x100; i++) |
| 183 | write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); |
| 184 | } else { |
| 185 | vga_textmode_init(); |
| 186 | } |
| 187 | |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 188 | pixel_p2 = target_frequency <= 225000 ? 10 : 5; |
| 189 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 190 | u32 candn, candm1, candm2, candp1; |
| 191 | for (candn = 1; candn <= 4; candn++) { |
| 192 | for (candm1 = 23; candm1 >= 16; candm1--) { |
| 193 | for (candm2 = 11; candm2 >= 5; candm2--) { |
| 194 | for (candp1 = 8; candp1 >= 1; candp1--) { |
| 195 | u32 m = 5 * (candm1 + 2) + (candm2 + 2); |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 196 | u32 p = candp1 * pixel_p2; |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 197 | u32 vco = DIV_ROUND_CLOSEST( |
| 198 | BASE_FREQUENCY * m, candn + 2); |
| 199 | u32 dot = DIV_ROUND_CLOSEST(vco, p); |
Arthur Heymans | 75f9131 | 2016-10-12 01:04:28 +0200 | [diff] [blame] | 200 | u32 this_err = MAX(dot, target_frequency) - |
| 201 | MIN(dot, target_frequency); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 202 | if (this_err < err_most) { |
| 203 | err_most = this_err; |
| 204 | pixel_n = candn; |
| 205 | pixel_m1 = candm1; |
| 206 | pixel_m2 = candm2; |
| 207 | pixel_p1 = candp1; |
| 208 | } |
| 209 | } |
| 210 | } |
| 211 | } |
| 212 | } |
| 213 | |
| 214 | if (err_most == 0xffffffff) { |
| 215 | printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); |
| 216 | return; |
| 217 | } |
| 218 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 219 | printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", |
| 220 | hactive, vactive); |
| 221 | printk(BIOS_DEBUG, "Borders %d x %d\n", |
| 222 | right_border, bottom_border); |
| 223 | printk(BIOS_DEBUG, "Blank %d x %d\n", |
| 224 | hblank, vblank); |
| 225 | printk(BIOS_DEBUG, "Sync %d x %d\n", |
| 226 | hsync, vsync); |
| 227 | printk(BIOS_DEBUG, "Front porch %d x %d\n", |
| 228 | hfront_porch, vfront_porch); |
| 229 | printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock |
| 230 | ? "Spread spectrum clock\n" : "DREF clock\n")); |
| 231 | printk(BIOS_DEBUG, "Polarities %d, %d\n", |
| 232 | hpolarity, vpolarity); |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 233 | printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", |
| 234 | pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 235 | printk(BIOS_DEBUG, "Pixel clock %d kHz\n", |
| 236 | BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 237 | (pixel_n + 2) / (pixel_p1 * pixel_p2)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 238 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 239 | mdelay(1); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 240 | write32(mmio + FP0(0), (pixel_n << 16) |
| 241 | | (pixel_m1 << 8) | pixel_m2); |
| 242 | write32(mmio + DPLL(0), DPLL_VCO_ENABLE |
| 243 | | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 244 | | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : |
| 245 | DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 246 | | (0x10000 << (pixel_p1 - 1)) |
| 247 | | (6 << 9)); |
| 248 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 249 | mdelay(1); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 250 | write32(mmio + DPLL(0), DPLL_VCO_ENABLE |
| 251 | | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL |
Arthur Heymans | 063cd5f | 2016-10-12 00:05:00 +0200 | [diff] [blame] | 252 | | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : |
| 253 | DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 254 | | (0x10000 << (pixel_p1 - 1)) |
| 255 | | (6 << 9)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 256 | |
| 257 | write32(mmio + ADPA, ADPA_DAC_ENABLE |
| 258 | | ADPA_PIPE_A_SELECT |
| 259 | | ADPA_CRT_HOTPLUG_MONITOR_COLOR |
| 260 | | ADPA_CRT_HOTPLUG_ENABLE |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 261 | | ADPA_VSYNC_CNTL_ENABLE |
| 262 | | ADPA_HSYNC_CNTL_ENABLE |
| 263 | | ADPA_DPMS_ON |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 264 | | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : |
| 265 | ADPA_VSYNC_ACTIVE_HIGH) |
| 266 | | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : |
| 267 | ADPA_HSYNC_ACTIVE_HIGH)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 268 | |
| 269 | write32(mmio + HTOTAL(0), |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 270 | ((hactive + right_border + hblank - 1) << 16) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 271 | | (hactive - 1)); |
| 272 | write32(mmio + HBLANK(0), |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 273 | ((hactive + right_border + hblank - 1) << 16) |
| 274 | | (hactive + right_border - 1)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 275 | write32(mmio + HSYNC(0), |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 276 | ((hactive + right_border + hfront_porch + hsync - 1) << 16) |
| 277 | | (hactive + right_border + hfront_porch - 1)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 278 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 279 | write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 280 | | (vactive - 1)); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 281 | write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) |
| 282 | | (vactive + bottom_border - 1)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 283 | write32(mmio + VSYNC(0), |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 284 | ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) |
| 285 | | (vactive + bottom_border + vfront_porch - 1)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 286 | |
| 287 | write32(mmio + PIPECONF(0), PIPECONF_DISABLE); |
| 288 | |
| 289 | write32(mmio + PF_WIN_POS(0), 0); |
Nico Huber | 6d8266b | 2017-05-20 16:46:01 +0200 | [diff] [blame] | 290 | if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 291 | write32(mmio + PIPESRC(0), ((hactive - 1) << 16) |
| 292 | | (vactive - 1)); |
| 293 | write32(mmio + PF_CTL(0), 0); |
| 294 | write32(mmio + PF_WIN_SZ(0), 0); |
| 295 | write32(mmio + PFIT_CONTROL, 0); |
| 296 | } else { |
| 297 | write32(mmio + PIPESRC(0), (639 << 16) | 399); |
| 298 | write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); |
| 299 | write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); |
| 300 | write32(mmio + PFIT_CONTROL, 0x80000000); |
| 301 | } |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 302 | |
| 303 | mdelay(1); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 304 | write32(mmio + PIPECONF(0), PIPECONF_BPP_6); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 305 | write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 306 | write32(mmio + PIPECONF(0), PIPECONF_ENABLE |
| 307 | | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 308 | |
Nico Huber | 6d8266b | 2017-05-20 16:46:01 +0200 | [diff] [blame] | 309 | if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 310 | write32(mmio + VGACNTRL, VGA_DISP_DISABLE); |
| 311 | write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE |
| 312 | | DISPPLANE_BGRX888); |
| 313 | mdelay(1); |
| 314 | } else { |
| 315 | write32(mmio + VGACNTRL, 0xc4008e); |
| 316 | } |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 317 | |
| 318 | write32(mmio + ADPA, ADPA_DAC_ENABLE |
| 319 | | ADPA_PIPE_A_SELECT |
| 320 | | ADPA_CRT_HOTPLUG_MONITOR_COLOR |
| 321 | | ADPA_CRT_HOTPLUG_ENABLE |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 322 | | ADPA_VSYNC_CNTL_ENABLE |
| 323 | | ADPA_HSYNC_CNTL_ENABLE |
| 324 | | ADPA_DPMS_ON |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 325 | | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : |
| 326 | ADPA_VSYNC_ACTIVE_HIGH) |
| 327 | | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : |
| 328 | ADPA_HSYNC_ACTIVE_HIGH)); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 329 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 330 | write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 331 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 332 | /* Enable screen memory. */ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 333 | vga_sr_write(1, vga_sr_read(1) & ~0x20); |
| 334 | |
| 335 | /* Clear interrupts. */ |
| 336 | write32(mmio + DEIIR, 0xffffffff); |
| 337 | write32(mmio + SDEIIR, 0xffffffff); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 338 | |
Nico Huber | 6d8266b | 2017-05-20 16:46:01 +0200 | [diff] [blame] | 339 | if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) { |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 340 | memset((void *) lfb, 0, |
| 341 | hactive * vactive * 4); |
| 342 | set_vbe_mode_info_valid(&edid, lfb); |
| 343 | } |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 344 | } |
| 345 | |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 346 | static void native_init(struct device *dev) |
| 347 | { |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 348 | struct resource *lfb_res; |
| 349 | struct resource *pio_res; |
| 350 | u32 physbase; |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 351 | struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 352 | struct northbridge_intel_x4x_config *conf = dev->chip_info; |
| 353 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 354 | lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 355 | pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); |
| 356 | physbase = pci_read_config32(dev, 0x5c) & ~0xf; |
| 357 | |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 358 | if (gtt_res && gtt_res->base) { |
| 359 | printk(BIOS_SPEW, |
| 360 | "Initializing VGA without OPROM. MMIO 0x%llx\n", |
| 361 | gtt_res->base); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 362 | intel_gma_init(conf, res2mmio(gtt_res, 0, 0), |
| 363 | physbase, pio_res->base, lfb_res->base); |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 364 | } |
| 365 | |
| 366 | /* Linux relies on VBT for panel info. */ |
Arthur Heymans | d3284a6 | 2016-09-25 22:48:00 +0200 | [diff] [blame] | 367 | generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE"); |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 368 | } |
| 369 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 370 | static void gma_func0_init(struct device *dev) |
| 371 | { |
Arthur Heymans | 2e7efe6 | 2017-05-06 18:05:57 +0200 | [diff] [blame] | 372 | u16 reg16, ggc; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 373 | u32 reg32; |
| 374 | |
| 375 | /* IGD needs to be Bus Master */ |
| 376 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 377 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 378 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 379 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 380 | /* configure GMBUSFREQ */ |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 381 | reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 382 | reg16 &= ~0x1ff; |
| 383 | reg16 |= 0xbc; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 384 | pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc, reg16); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 385 | |
Arthur Heymans | 2e7efe6 | 2017-05-06 18:05:57 +0200 | [diff] [blame] | 386 | ggc = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC); |
| 387 | |
| 388 | if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { |
| 389 | if (ggc & (1 << 1)) { |
| 390 | printk(BIOS_DEBUG, "VGA cycles not assigned to IGD. " |
| 391 | "Not running native graphic init.\n"); |
| 392 | return; |
| 393 | } |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 394 | native_init(dev); |
Arthur Heymans | 2e7efe6 | 2017-05-06 18:05:57 +0200 | [diff] [blame] | 395 | } else { |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 396 | pci_dev_init(dev); |
Arthur Heymans | 2e7efe6 | 2017-05-06 18:05:57 +0200 | [diff] [blame] | 397 | } |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 398 | } |
| 399 | |
Arthur Heymans | c80748c | 2017-02-26 23:04:51 +0100 | [diff] [blame] | 400 | static void gma_func0_disable(struct device *dev) |
| 401 | { |
| 402 | struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 403 | u16 ggc; |
| 404 | |
| 405 | ggc = pci_read_config16(dev_host, D0F0_GGC); |
| 406 | ggc |= (1 << 1); /* VGA cycles to discrete GPU */ |
| 407 | pci_write_config16(dev_host, D0F0_GGC, ggc); |
| 408 | } |
| 409 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 410 | static void gma_set_subsystem(device_t dev, unsigned int vendor, |
| 411 | unsigned int device) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 412 | { |
| 413 | if (!vendor || !device) { |
| 414 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 415 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 416 | } else { |
| 417 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 418 | ((device & 0xffff) << 16) | (vendor & |
| 419 | 0xffff)); |
| 420 | } |
| 421 | } |
| 422 | |
| 423 | const struct i915_gpu_controller_info * |
| 424 | intel_gma_get_controller_info(void) |
| 425 | { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 426 | device_t dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); |
| 427 | if (!dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 428 | return NULL; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 429 | struct northbridge_intel_x4x_config *chip = dev->chip_info; |
| 430 | return &chip->gfx; |
| 431 | } |
| 432 | |
| 433 | static void gma_ssdt(device_t device) |
| 434 | { |
| 435 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 436 | if (!gfx) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 437 | return; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 438 | |
| 439 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 440 | } |
| 441 | |
| 442 | static struct pci_operations gma_pci_ops = { |
| 443 | .set_subsystem = gma_set_subsystem, |
| 444 | }; |
| 445 | |
| 446 | static struct device_operations gma_func0_ops = { |
| 447 | .read_resources = pci_dev_read_resources, |
| 448 | .set_resources = pci_dev_set_resources, |
| 449 | .enable_resources = pci_dev_enable_resources, |
| 450 | .acpi_fill_ssdt_generator = gma_ssdt, |
| 451 | .init = gma_func0_init, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 452 | .ops_pci = &gma_pci_ops, |
Arthur Heymans | c80748c | 2017-02-26 23:04:51 +0100 | [diff] [blame] | 453 | .disable = gma_func0_disable, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 454 | }; |
| 455 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 456 | static const unsigned short pci_device_ids[] = { |
Arthur Heymans | 9e70ce0 | 2016-12-16 15:32:32 +0100 | [diff] [blame] | 457 | 0x2e02, /* Eaglelake */ |
| 458 | 0x2e12, /* Q43/Q45 */ |
| 459 | 0x2e22, /* G43/G45 */ |
| 460 | 0x2e32, /* G41 */ |
| 461 | 0x2e42, /* B43 */ |
| 462 | 0x2e92, /* B43_I */ |
| 463 | 0 |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 464 | }; |
| 465 | |
| 466 | static const struct pci_driver gma __pci_driver = { |
| 467 | .ops = &gma_func0_ops, |
| 468 | .vendor = PCI_VENDOR_ID_INTEL, |
| 469 | .devices = pci_device_ids, |
| 470 | }; |