blob: 561e776f24e826a5f9a2fc961af5ea82552fd6a8 [file] [log] [blame]
Damien Zammit43a1f782015-08-19 15:16:59 +10001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Chromium OS Authors
5 * Copyright (C) 2013 Vladimir Serbinenko
6 * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <arch/io.h>
19#include <console/console.h>
20#include <delay.h>
21#include <device/device.h>
22#include <device/pci.h>
23#include <device/pci_ids.h>
24#include <string.h>
25#include <device/pci_ops.h>
26#include <cpu/x86/msr.h>
27#include <cpu/x86/mtrr.h>
Arthur Heymansde14ea72016-09-04 16:01:11 +020028#include <commonlib/helpers.h>
Damien Zammit43a1f782015-08-19 15:16:59 +100029
30#include "drivers/intel/gma/i915_reg.h"
31#include "chip.h"
32#include "x4x.h"
33#include <drivers/intel/gma/intel_bios.h>
Arthur Heymansde14ea72016-09-04 16:01:11 +020034#include <drivers/intel/gma/edid.h>
Damien Zammit43a1f782015-08-19 15:16:59 +100035#include <drivers/intel/gma/i915.h>
36#include <pc80/vga.h>
37#include <pc80/vga_io.h>
38
Arthur Heymansde14ea72016-09-04 16:01:11 +020039#define BASE_FREQUENCY 96000
40
41static u8 edid_is_present(u8 *edid, u32 edid_size)
42{
43 u32 i;
44 for (i = 0; i < edid_size; i++) {
45 if (*(edid + i) != 0)
46 return 1;
47 }
48 return 0;
49}
Damien Zammit43a1f782015-08-19 15:16:59 +100050static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
Arthur Heymansde14ea72016-09-04 16:01:11 +020051 u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
Damien Zammit43a1f782015-08-19 15:16:59 +100052{
53
Arthur Heymansde14ea72016-09-04 16:01:11 +020054
Damien Zammit43a1f782015-08-19 15:16:59 +100055 int i;
Arthur Heymansde14ea72016-09-04 16:01:11 +020056 u8 edid_data[128];
57 struct edid edid;
58 struct edid_mode *mode;
59 u8 edid_is_found;
60
61 /* Initialise mode variables for 640 x 480 @ 60Hz */
62 u32 hactive = 640, vactive = 480;
63 u32 right_border = 0, bottom_border = 0;
64 int hpolarity = 0, vpolarity = 0;
65 u32 hsync = 96, vsync = 2;
66 u32 hblank = 160, vblank = 45;
67 u32 hfront_porch = 16, vfront_porch = 10;
68 u32 target_frequency = 25175;
69
70 u32 err_most = 0xffffffff;
71 u32 pixel_p1 = 1;
Arthur Heymans063cd5f2016-10-12 00:05:00 +020072 u32 pixel_p2;
Arthur Heymansde14ea72016-09-04 16:01:11 +020073 u32 pixel_n = 1;
74 u32 pixel_m1 = 1;
75 u32 pixel_m2 = 1;
Damien Zammit43a1f782015-08-19 15:16:59 +100076
Damien Zammit216fc502016-01-22 19:13:18 +110077 vga_gr_write(0x18, 0);
Damien Zammit43a1f782015-08-19 15:16:59 +100078
Arthur Heymansde14ea72016-09-04 16:01:11 +020079 /* Set up GTT */
80 for (i = 0; i < 0x1000; i++) {
81 outl((i << 2) | 1, piobase);
82 outl(physbase + (i << 12) + 1, piobase + 4);
83 }
84
Damien Zammit43a1f782015-08-19 15:16:59 +100085 write32(mmio + VGA0, 0x31108);
86 write32(mmio + VGA1, 0x31406);
87
88 write32(mmio + ADPA, ADPA_DAC_ENABLE
89 | ADPA_PIPE_A_SELECT
90 | ADPA_CRT_HOTPLUG_MONITOR_COLOR
91 | ADPA_CRT_HOTPLUG_ENABLE
92 | ADPA_USE_VGA_HVPOLARITY
93 | ADPA_VSYNC_CNTL_ENABLE
94 | ADPA_HSYNC_CNTL_ENABLE
95 | ADPA_DPMS_ON
96 );
97
98 write32(mmio + 0x7041c, 0x0);
99 write32(mmio + DPLL_MD(0), 0x3);
100 write32(mmio + DPLL_MD(1), 0x3);
101
102 vga_misc_write(0x67);
103
104 const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
105 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
106 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
107 0xff
108 };
109 vga_cr_write(0x11, 0);
110
111 for (i = 0; i <= 0x18; i++)
112 vga_cr_write(i, cr[i]);
113
Arthur Heymansde14ea72016-09-04 16:01:11 +0200114 udelay(1);
115
Arthur Heymans7141ff32016-10-10 17:49:00 +0200116 intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data,
117 sizeof(edid_data));
Arthur Heymansde14ea72016-09-04 16:01:11 +0200118 intel_gmbus_stop(mmio + GMBUS0);
119 decode_edid(edid_data,
120 sizeof(edid_data), &edid);
121 mode = &edid.mode;
122
123
Damien Zammit43a1f782015-08-19 15:16:59 +1000124 /* Disable screen memory to prevent garbage from appearing. */
125 vga_sr_write(1, vga_sr_read(1) | 0x20);
126
Arthur Heymansde14ea72016-09-04 16:01:11 +0200127 edid_is_found = edid_is_present(edid_data, sizeof(edid_data));
128 if (edid_is_found) {
129 printk(BIOS_DEBUG, "EDID is not null");
130 hactive = edid.x_resolution;
131 vactive = edid.y_resolution;
132 right_border = mode->hborder;
133 bottom_border = mode->vborder;
134 hpolarity = (mode->phsync == '-');
135 vpolarity = (mode->pvsync == '-');
136 vsync = mode->vspw;
137 hsync = mode->hspw;
138 vblank = mode->vbl;
139 hblank = mode->hbl;
140 hfront_porch = mode->hso;
141 vfront_porch = mode->vso;
142 target_frequency = mode->pixel_clock;
143 } else
144 printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode");
145
Nico Huber6d8266b2017-05-20 16:46:01 +0200146 if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
Arthur Heymansde14ea72016-09-04 16:01:11 +0200147 vga_sr_write(1, 1);
148 vga_sr_write(0x2, 0xf);
149 vga_sr_write(0x3, 0x0);
150 vga_sr_write(0x4, 0xe);
151 vga_gr_write(0, 0x0);
152 vga_gr_write(1, 0x0);
153 vga_gr_write(2, 0x0);
154 vga_gr_write(3, 0x0);
155 vga_gr_write(4, 0x0);
156 vga_gr_write(5, 0x0);
157 vga_gr_write(6, 0x5);
158 vga_gr_write(7, 0xf);
159 vga_gr_write(0x10, 0x1);
160 vga_gr_write(0x11, 0);
161
162 edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
163
164 write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
165 | DISPPLANE_BGRX888);
166 write32(mmio + DSPADDR(0), 0);
167 write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
168 write32(mmio + DSPSURF(0), 0);
169 for (i = 0; i < 0x100; i++)
170 write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
171 } else {
172 vga_textmode_init();
173 }
174
Arthur Heymans063cd5f2016-10-12 00:05:00 +0200175 pixel_p2 = target_frequency <= 225000 ? 10 : 5;
176
Arthur Heymansde14ea72016-09-04 16:01:11 +0200177 u32 candn, candm1, candm2, candp1;
178 for (candn = 1; candn <= 4; candn++) {
179 for (candm1 = 23; candm1 >= 16; candm1--) {
180 for (candm2 = 11; candm2 >= 5; candm2--) {
181 for (candp1 = 8; candp1 >= 1; candp1--) {
182 u32 m = 5 * (candm1 + 2) + (candm2 + 2);
Arthur Heymans063cd5f2016-10-12 00:05:00 +0200183 u32 p = candp1 * pixel_p2;
Arthur Heymansde14ea72016-09-04 16:01:11 +0200184 u32 vco = DIV_ROUND_CLOSEST(
185 BASE_FREQUENCY * m, candn + 2);
186 u32 dot = DIV_ROUND_CLOSEST(vco, p);
Arthur Heymans75f91312016-10-12 01:04:28 +0200187 u32 this_err = MAX(dot, target_frequency) -
188 MIN(dot, target_frequency);
Arthur Heymansde14ea72016-09-04 16:01:11 +0200189 if (this_err < err_most) {
190 err_most = this_err;
191 pixel_n = candn;
192 pixel_m1 = candm1;
193 pixel_m2 = candm2;
194 pixel_p1 = candp1;
195 }
196 }
197 }
198 }
199 }
200
201 if (err_most == 0xffffffff) {
202 printk(BIOS_ERR, "Couldn't find GFX clock divisors\n");
203 return;
204 }
205
Arthur Heymansde14ea72016-09-04 16:01:11 +0200206 printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
207 hactive, vactive);
208 printk(BIOS_DEBUG, "Borders %d x %d\n",
209 right_border, bottom_border);
210 printk(BIOS_DEBUG, "Blank %d x %d\n",
211 hblank, vblank);
212 printk(BIOS_DEBUG, "Sync %d x %d\n",
213 hsync, vsync);
214 printk(BIOS_DEBUG, "Front porch %d x %d\n",
215 hfront_porch, vfront_porch);
216 printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
217 ? "Spread spectrum clock\n" : "DREF clock\n"));
218 printk(BIOS_DEBUG, "Polarities %d, %d\n",
219 hpolarity, vpolarity);
Arthur Heymans063cd5f2016-10-12 00:05:00 +0200220 printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n",
221 pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2);
Arthur Heymansde14ea72016-09-04 16:01:11 +0200222 printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
223 BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
Arthur Heymans063cd5f2016-10-12 00:05:00 +0200224 (pixel_n + 2) / (pixel_p1 * pixel_p2));
Damien Zammit43a1f782015-08-19 15:16:59 +1000225
Damien Zammit43a1f782015-08-19 15:16:59 +1000226 mdelay(1);
Arthur Heymansde14ea72016-09-04 16:01:11 +0200227 write32(mmio + FP0(0), (pixel_n << 16)
228 | (pixel_m1 << 8) | pixel_m2);
229 write32(mmio + DPLL(0), DPLL_VCO_ENABLE
230 | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL
Arthur Heymans063cd5f2016-10-12 00:05:00 +0200231 | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 :
232 DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
Arthur Heymansde14ea72016-09-04 16:01:11 +0200233 | (0x10000 << (pixel_p1 - 1))
234 | (6 << 9));
235
Damien Zammit43a1f782015-08-19 15:16:59 +1000236 mdelay(1);
Arthur Heymansde14ea72016-09-04 16:01:11 +0200237 write32(mmio + DPLL(0), DPLL_VCO_ENABLE
238 | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL
Arthur Heymans063cd5f2016-10-12 00:05:00 +0200239 | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 :
240 DPLL_DAC_SERIAL_P2_CLOCK_DIV_5)
Arthur Heymansde14ea72016-09-04 16:01:11 +0200241 | (0x10000 << (pixel_p1 - 1))
242 | (6 << 9));
Damien Zammit43a1f782015-08-19 15:16:59 +1000243
244 write32(mmio + ADPA, ADPA_DAC_ENABLE
245 | ADPA_PIPE_A_SELECT
246 | ADPA_CRT_HOTPLUG_MONITOR_COLOR
247 | ADPA_CRT_HOTPLUG_ENABLE
Damien Zammit43a1f782015-08-19 15:16:59 +1000248 | ADPA_VSYNC_CNTL_ENABLE
249 | ADPA_HSYNC_CNTL_ENABLE
250 | ADPA_DPMS_ON
Arthur Heymansde14ea72016-09-04 16:01:11 +0200251 | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :
252 ADPA_VSYNC_ACTIVE_HIGH)
253 | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :
254 ADPA_HSYNC_ACTIVE_HIGH));
Damien Zammit43a1f782015-08-19 15:16:59 +1000255
256 write32(mmio + HTOTAL(0),
Arthur Heymansde14ea72016-09-04 16:01:11 +0200257 ((hactive + right_border + hblank - 1) << 16)
Damien Zammit43a1f782015-08-19 15:16:59 +1000258 | (hactive - 1));
259 write32(mmio + HBLANK(0),
Arthur Heymansde14ea72016-09-04 16:01:11 +0200260 ((hactive + right_border + hblank - 1) << 16)
261 | (hactive + right_border - 1));
Damien Zammit43a1f782015-08-19 15:16:59 +1000262 write32(mmio + HSYNC(0),
Arthur Heymansde14ea72016-09-04 16:01:11 +0200263 ((hactive + right_border + hfront_porch + hsync - 1) << 16)
264 | (hactive + right_border + hfront_porch - 1));
Damien Zammit43a1f782015-08-19 15:16:59 +1000265
Arthur Heymansde14ea72016-09-04 16:01:11 +0200266 write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
Damien Zammit43a1f782015-08-19 15:16:59 +1000267 | (vactive - 1));
Arthur Heymansde14ea72016-09-04 16:01:11 +0200268 write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
269 | (vactive + bottom_border - 1));
Damien Zammit43a1f782015-08-19 15:16:59 +1000270 write32(mmio + VSYNC(0),
Arthur Heymansde14ea72016-09-04 16:01:11 +0200271 ((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
272 | (vactive + bottom_border + vfront_porch - 1));
Damien Zammit43a1f782015-08-19 15:16:59 +1000273
274 write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
275
276 write32(mmio + PF_WIN_POS(0), 0);
Nico Huber6d8266b2017-05-20 16:46:01 +0200277 if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
Arthur Heymansde14ea72016-09-04 16:01:11 +0200278 write32(mmio + PIPESRC(0), ((hactive - 1) << 16)
279 | (vactive - 1));
280 write32(mmio + PF_CTL(0), 0);
281 write32(mmio + PF_WIN_SZ(0), 0);
282 write32(mmio + PFIT_CONTROL, 0);
283 } else {
284 write32(mmio + PIPESRC(0), (639 << 16) | 399);
285 write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
286 write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
287 write32(mmio + PFIT_CONTROL, 0x80000000);
288 }
Damien Zammit43a1f782015-08-19 15:16:59 +1000289
290 mdelay(1);
Arthur Heymansde14ea72016-09-04 16:01:11 +0200291 write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
Arthur Heymansde14ea72016-09-04 16:01:11 +0200292 write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
Damien Zammit216fc502016-01-22 19:13:18 +1100293 write32(mmio + PIPECONF(0), PIPECONF_ENABLE
294 | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
Damien Zammit43a1f782015-08-19 15:16:59 +1000295
Nico Huber6d8266b2017-05-20 16:46:01 +0200296 if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
Arthur Heymansde14ea72016-09-04 16:01:11 +0200297 write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
298 write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
299 | DISPPLANE_BGRX888);
300 mdelay(1);
301 } else {
302 write32(mmio + VGACNTRL, 0xc4008e);
303 }
Damien Zammit43a1f782015-08-19 15:16:59 +1000304
305 write32(mmio + ADPA, ADPA_DAC_ENABLE
306 | ADPA_PIPE_A_SELECT
307 | ADPA_CRT_HOTPLUG_MONITOR_COLOR
308 | ADPA_CRT_HOTPLUG_ENABLE
Damien Zammit43a1f782015-08-19 15:16:59 +1000309 | ADPA_VSYNC_CNTL_ENABLE
310 | ADPA_HSYNC_CNTL_ENABLE
311 | ADPA_DPMS_ON
Arthur Heymansde14ea72016-09-04 16:01:11 +0200312 | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW :
313 ADPA_VSYNC_ACTIVE_HIGH)
314 | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW :
315 ADPA_HSYNC_ACTIVE_HIGH));
Damien Zammit43a1f782015-08-19 15:16:59 +1000316
Arthur Heymansde14ea72016-09-04 16:01:11 +0200317 write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
Damien Zammit43a1f782015-08-19 15:16:59 +1000318
Arthur Heymansde14ea72016-09-04 16:01:11 +0200319 /* Enable screen memory. */
Damien Zammit43a1f782015-08-19 15:16:59 +1000320 vga_sr_write(1, vga_sr_read(1) & ~0x20);
321
322 /* Clear interrupts. */
323 write32(mmio + DEIIR, 0xffffffff);
324 write32(mmio + SDEIIR, 0xffffffff);
Arthur Heymansde14ea72016-09-04 16:01:11 +0200325
Nico Huber6d8266b2017-05-20 16:46:01 +0200326 if (IS_ENABLED(CONFIG_LINEAR_FRAMEBUFFER)) {
Arthur Heymansde14ea72016-09-04 16:01:11 +0200327 memset((void *) lfb, 0,
328 hactive * vactive * 4);
329 set_vbe_mode_info_valid(&edid, lfb);
330 }
Damien Zammit43a1f782015-08-19 15:16:59 +1000331}
332
Damien Zammit216fc502016-01-22 19:13:18 +1100333static void native_init(struct device *dev)
334{
Arthur Heymansde14ea72016-09-04 16:01:11 +0200335 struct resource *lfb_res;
336 struct resource *pio_res;
337 u32 physbase;
Damien Zammit216fc502016-01-22 19:13:18 +1100338 struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
339 struct northbridge_intel_x4x_config *conf = dev->chip_info;
340
Arthur Heymansde14ea72016-09-04 16:01:11 +0200341 lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
342 pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
343 physbase = pci_read_config32(dev, 0x5c) & ~0xf;
344
Damien Zammit216fc502016-01-22 19:13:18 +1100345 if (gtt_res && gtt_res->base) {
346 printk(BIOS_SPEW,
347 "Initializing VGA without OPROM. MMIO 0x%llx\n",
348 gtt_res->base);
Arthur Heymansde14ea72016-09-04 16:01:11 +0200349 intel_gma_init(conf, res2mmio(gtt_res, 0, 0),
350 physbase, pio_res->base, lfb_res->base);
Damien Zammit216fc502016-01-22 19:13:18 +1100351 }
352
353 /* Linux relies on VBT for panel info. */
Arthur Heymansd3284a62016-09-25 22:48:00 +0200354 generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE");
Damien Zammit216fc502016-01-22 19:13:18 +1100355}
356
Damien Zammit43a1f782015-08-19 15:16:59 +1000357static void gma_func0_init(struct device *dev)
358{
Arthur Heymans2e7efe62017-05-06 18:05:57 +0200359 u16 reg16, ggc;
Damien Zammit43a1f782015-08-19 15:16:59 +1000360 u32 reg32;
361
362 /* IGD needs to be Bus Master */
363 reg32 = pci_read_config32(dev, PCI_COMMAND);
364 reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
365 pci_write_config32(dev, PCI_COMMAND, reg32);
366
Arthur Heymansde14ea72016-09-04 16:01:11 +0200367 /* configure GMBUSFREQ */
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100368 reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc);
Arthur Heymansde14ea72016-09-04 16:01:11 +0200369 reg16 &= ~0x1ff;
370 reg16 |= 0xbc;
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100371 pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2, 0)), 0xcc, reg16);
Arthur Heymansde14ea72016-09-04 16:01:11 +0200372
Arthur Heymans2e7efe62017-05-06 18:05:57 +0200373 ggc = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC);
374
375 if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
376 if (ggc & (1 << 1)) {
377 printk(BIOS_DEBUG, "VGA cycles not assigned to IGD. "
378 "Not running native graphic init.\n");
379 return;
380 }
Damien Zammit216fc502016-01-22 19:13:18 +1100381 native_init(dev);
Arthur Heymans2e7efe62017-05-06 18:05:57 +0200382 } else {
Damien Zammit216fc502016-01-22 19:13:18 +1100383 pci_dev_init(dev);
Arthur Heymans2e7efe62017-05-06 18:05:57 +0200384 }
Damien Zammit43a1f782015-08-19 15:16:59 +1000385}
386
Arthur Heymansc80748c2017-02-26 23:04:51 +0100387static void gma_func0_disable(struct device *dev)
388{
389 struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0, 0));
390 u16 ggc;
391
392 ggc = pci_read_config16(dev_host, D0F0_GGC);
393 ggc |= (1 << 1); /* VGA cycles to discrete GPU */
394 pci_write_config16(dev_host, D0F0_GGC, ggc);
395}
396
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100397static void gma_set_subsystem(device_t dev, unsigned int vendor,
398 unsigned int device)
Damien Zammit43a1f782015-08-19 15:16:59 +1000399{
400 if (!vendor || !device) {
401 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
402 pci_read_config32(dev, PCI_VENDOR_ID));
403 } else {
404 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
405 ((device & 0xffff) << 16) | (vendor &
406 0xffff));
407 }
408}
409
410const struct i915_gpu_controller_info *
411intel_gma_get_controller_info(void)
412{
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100413 device_t dev = dev_find_slot(0, PCI_DEVFN(0x2, 0));
414 if (!dev)
Damien Zammit43a1f782015-08-19 15:16:59 +1000415 return NULL;
Damien Zammit43a1f782015-08-19 15:16:59 +1000416 struct northbridge_intel_x4x_config *chip = dev->chip_info;
417 return &chip->gfx;
418}
419
420static void gma_ssdt(device_t device)
421{
422 const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100423 if (!gfx)
Damien Zammit43a1f782015-08-19 15:16:59 +1000424 return;
Damien Zammit43a1f782015-08-19 15:16:59 +1000425
426 drivers_intel_gma_displays_ssdt_generate(gfx);
427}
428
429static struct pci_operations gma_pci_ops = {
430 .set_subsystem = gma_set_subsystem,
431};
432
433static struct device_operations gma_func0_ops = {
434 .read_resources = pci_dev_read_resources,
435 .set_resources = pci_dev_set_resources,
436 .enable_resources = pci_dev_enable_resources,
437 .acpi_fill_ssdt_generator = gma_ssdt,
438 .init = gma_func0_init,
Damien Zammit43a1f782015-08-19 15:16:59 +1000439 .ops_pci = &gma_pci_ops,
Arthur Heymansc80748c2017-02-26 23:04:51 +0100440 .disable = gma_func0_disable,
Damien Zammit43a1f782015-08-19 15:16:59 +1000441};
442
Arthur Heymans70a1dda2017-03-09 01:58:24 +0100443static const unsigned short pci_device_ids[] = {
Arthur Heymans9e70ce02016-12-16 15:32:32 +0100444 0x2e02, /* Eaglelake */
445 0x2e12, /* Q43/Q45 */
446 0x2e22, /* G43/G45 */
447 0x2e32, /* G41 */
448 0x2e42, /* B43 */
449 0x2e92, /* B43_I */
450 0
Damien Zammit43a1f782015-08-19 15:16:59 +1000451};
452
453static const struct pci_driver gma __pci_driver = {
454 .ops = &gma_func0_ops,
455 .vendor = PCI_VENDOR_ID_INTEL,
456 .devices = pci_device_ids,
457};