Subrata Banik | 76806c3 | 2022-01-03 17:33:35 +0000 | [diff] [blame] | 1 | config DISABLE_HECI1_AT_PRE_BOOT |
| 2 | bool "Disable HECI1 at the end of boot" |
| 3 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 4 | default n |
| 5 | help |
| 6 | This config decides the state of HECI1(CSE) device at the end of boot. |
| 7 | Mainboard users to select this config to make HECI1 `function disable` |
| 8 | prior to handing off to payload. |
| 9 | |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 10 | config MAX_HECI_DEVICES |
| 11 | int |
| 12 | default 6 |
| 13 | |
| 14 | config SOC_INTEL_COMMON_BLOCK_CSE |
| 15 | bool |
| 16 | default n |
| 17 | help |
| 18 | Driver for communication with Converged Security Engine (CSE) |
| 19 | over Host Embedded Controller Interface (HECI) |
| 20 | |
Subrata Banik | 32e0673 | 2022-01-28 02:05:15 +0530 | [diff] [blame] | 21 | config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI |
Subrata Banik | 7e89984 | 2018-05-17 18:28:26 +0530 | [diff] [blame] | 22 | bool |
| 23 | default y if HECI_DISABLE_USING_SMM |
| 24 | select SOC_INTEL_COMMON_BLOCK_P2SB |
| 25 | help |
Subrata Banik | 32e0673 | 2022-01-28 02:05:15 +0530 | [diff] [blame] | 26 | Use this config to allow common CSE block to make HECI1 function disable |
| 27 | in the SMM mode. From CNL PCH onwards,`HECI1` disabling can only be done |
| 28 | using the non-posted sideband write after FSP-S sets the postboot_sai |
| 29 | attribute. |
| 30 | |
| 31 | config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC |
| 32 | bool |
| 33 | default n |
| 34 | select SOC_INTEL_COMMON_BLOCK_PMC |
| 35 | help |
| 36 | Use this config to allow common CSE block to make HECI1 function disable |
| 37 | using PMC IPC command `0xA9`. From TGL PCH onwards, disabling heci1 |
| 38 | device using PMC IPC doesn't required to run the operation in SMM. |
| 39 | |
| 40 | config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR |
| 41 | bool |
| 42 | default n |
| 43 | select SOC_INTEL_COMMON_BLOCK_PCR |
| 44 | help |
| 45 | Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) |
| 46 | to make `HECI1` device disable using private configuration register (PCR) write. |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 47 | |
MAULIK V VAGHELA | 61b8f89 | 2021-12-17 17:55:22 +0530 | [diff] [blame] | 48 | config SOC_INTEL_CSE_SEND_EOP_EARLY |
Michał Kopeć | 9c4ae91 | 2022-10-29 18:00:18 +0200 | [diff] [blame] | 49 | bool "CSE send EOP early" |
MAULIK V VAGHELA | 61b8f89 | 2021-12-17 17:55:22 +0530 | [diff] [blame] | 50 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 51 | help |
| 52 | Use this config to send End Of Post (EOP) earlier through SoC code in order to |
| 53 | reduce time required to send EOP and getting CSE response. |
| 54 | In later stages, CSE might be busy and might require more time to process EOP command. |
| 55 | SoC can use this Kconfig to send EOP earlier by itself. |
| 56 | |
Subrata Banik | bed82b0 | 2022-11-24 21:02:00 +0530 | [diff] [blame] | 57 | config SOC_INTEL_CSE_SEND_EOP_LATE |
| 58 | bool |
| 59 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 60 | help |
| 61 | Use this config to send End Of Post (EOP) late (even after CSE `final` operation) |
| 62 | using boot state either `BS_PAYLOAD_BOOT` or `BS_PAYLOAD_LOAD` from common code |
| 63 | in order to reduce time required to send EOP and getting CSE response. |
| 64 | It has been observed that CSE might be busy and might require more time to |
| 65 | process the EOP command. |
| 66 | SoC can use this Kconfig to send EOP later by itself. |
| 67 | Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this |
| 68 | config is applicable for those platforms. |
| 69 | |
Jeremy Compostella | e7a1204 | 2023-03-13 13:59:08 -0700 | [diff] [blame^] | 70 | config SOC_INTEL_CSE_SEND_EOP_ASYNC |
| 71 | bool |
| 72 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 73 | depends on !SOC_INTEL_CSE_SEND_EOP_LATE |
| 74 | depends on !SOC_INTEL_CSE_SEND_EOP_EARLY |
| 75 | help |
| 76 | Use this config to handle End Of Post (EOP) completion |
| 77 | asynchronously. The EOP command is sent first and the result |
| 78 | is checked later leaving time to CSE to complete the |
| 79 | operation while coreboot perform other activities. |
| 80 | Performing EOP asynchronously reduces the time spent |
| 81 | actively waiting for command completion which can have a |
| 82 | significant impact on boot time. |
| 83 | |
| 84 | Using this asynchronous approach comes with the limitation |
| 85 | that no HECI command should be sent between the time the EOP |
| 86 | request is posted (at CSE .final device operation) and the |
| 87 | time coreboot check for its completion (BS_PAYLOAD_LOAD). |
| 88 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 89 | config SOC_INTEL_CSE_LITE_SKU |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 90 | bool |
| 91 | default n |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 92 | help |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 93 | Enables CSE Lite SKU |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 94 | |
Johnny Lin | a3e68c9 | 2022-08-09 15:36:30 +0800 | [diff] [blame] | 95 | config SOC_INTEL_CSE_SERVER_SKU |
| 96 | bool |
| 97 | default n |
| 98 | help |
| 99 | Enables CSE Server SKU |
| 100 | |
V Sowmya | f990552 | 2020-11-12 20:19:04 +0530 | [diff] [blame] | 101 | config SOC_INTEL_CSE_RW_UPDATE |
| 102 | bool "Enable the CSE RW Update Feature" |
| 103 | default n |
| 104 | depends on SOC_INTEL_CSE_LITE_SKU |
| 105 | help |
| 106 | This config will enable CSE RW firmware update feature and also will be used ensure |
| 107 | all the required configs are provided by mainboard. |
| 108 | |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 109 | config SOC_INTEL_CSE_FMAP_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 110 | string "Name of CSE Region in FMAP" if SOC_INTEL_CSE_RW_UPDATE |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 111 | default "SI_ME" |
| 112 | help |
| 113 | Name of CSE region in FMAP |
| 114 | |
Sridhar Siricilla | 361e364 | 2020-10-18 20:14:07 +0530 | [diff] [blame] | 115 | config SOC_INTEL_CSE_RW_A_FMAP_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 116 | string "Location of CSE RW A in FMAP" if SOC_INTEL_CSE_RW_UPDATE |
Sridhar Siricilla | 361e364 | 2020-10-18 20:14:07 +0530 | [diff] [blame] | 117 | default "ME_RW_A" |
| 118 | help |
| 119 | Name of CSE RW A region in FMAP |
| 120 | |
| 121 | config SOC_INTEL_CSE_RW_B_FMAP_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 122 | string "Location of CSE RW B in FMAP" if SOC_INTEL_CSE_RW_UPDATE |
Sridhar Siricilla | 361e364 | 2020-10-18 20:14:07 +0530 | [diff] [blame] | 123 | default "ME_RW_B" |
| 124 | help |
| 125 | Name of CSE RW B region in FMAP |
| 126 | |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 127 | config SOC_INTEL_CSE_RW_CBFS_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 128 | string "CBFS entry name for CSE RW blob" if SOC_INTEL_CSE_RW_UPDATE |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 129 | default "me_rw" |
| 130 | help |
| 131 | CBFS entry name for Intel CSE CBFS RW blob |
Sridhar Siricilla | b2353a7 | 2019-09-13 16:32:00 +0530 | [diff] [blame] | 132 | |
Furquan Shaikh | d2da870 | 2021-10-07 00:08:59 -0700 | [diff] [blame] | 133 | config SOC_INTEL_CSE_RW_HASH_CBFS_NAME |
| 134 | string "CBFS name for CSE RW hash file" if SOC_INTEL_CSE_RW_UPDATE |
| 135 | default "me_rw.hash" |
V Sowmya | 338b83c | 2020-11-11 07:04:13 +0530 | [diff] [blame] | 136 | help |
Furquan Shaikh | d2da870 | 2021-10-07 00:08:59 -0700 | [diff] [blame] | 137 | CBFS name for Intel CSE CBFS RW hash file |
| 138 | |
| 139 | config SOC_INTEL_CSE_RW_VERSION_CBFS_NAME |
| 140 | string "CBFS name for CSE RW version file" if SOC_INTEL_CSE_RW_UPDATE |
| 141 | default "me_rw.version" |
| 142 | help |
| 143 | CBFS name for Intel CSE CBFS RW version file |
V Sowmya | 338b83c | 2020-11-11 07:04:13 +0530 | [diff] [blame] | 144 | |
Sridhar Siricilla | b2353a7 | 2019-09-13 16:32:00 +0530 | [diff] [blame] | 145 | config SOC_INTEL_CSE_RW_FILE |
Furquan Shaikh | 3f0d643 | 2021-10-09 00:08:56 -0700 | [diff] [blame] | 146 | string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE && !STITCH_ME_BIN |
Sridhar Siricilla | b2353a7 | 2019-09-13 16:32:00 +0530 | [diff] [blame] | 147 | default "" |
| 148 | help |
| 149 | Intel CSE CBFS RW blob path and file name |
V Sowmya | 187f06f | 2020-11-11 06:33:43 +0530 | [diff] [blame] | 150 | |
| 151 | config SOC_INTEL_CSE_RW_VERSION |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 152 | string "Intel CSE RW firmware version" if SOC_INTEL_CSE_RW_UPDATE |
V Sowmya | 187f06f | 2020-11-11 06:33:43 +0530 | [diff] [blame] | 153 | default "" |
| 154 | help |
| 155 | This config contains the Intel CSE RW version of the blob that is provided by |
| 156 | SOC_INTEL_CSE_RW_FILE config and the version must be set in the format |
| 157 | major.minor.hotfix.build (ex: 14.0.40.1209). |
Tim Wawrzynczak | 064ca18 | 2021-06-17 12:40:13 -0600 | [diff] [blame] | 158 | |
| 159 | config SOC_INTEL_CSE_SET_EOP |
| 160 | bool |
| 161 | default n |
Tim Wawrzynczak | 9fdd2b2 | 2021-06-18 10:34:09 -0600 | [diff] [blame] | 162 | select PMC_IPC_ACPI_INTERFACE |
Tim Wawrzynczak | 064ca18 | 2021-06-17 12:40:13 -0600 | [diff] [blame] | 163 | help |
| 164 | This config ensures coreboot will send the CSE the End-of-POST message |
| 165 | just prior to loading the payload. This is a security feature so the |
| 166 | CSE will no longer respond to Pre-Boot commands. |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 167 | |
Krishna Prasad Bhat | 333edcc | 2021-11-26 06:52:27 +0530 | [diff] [blame] | 168 | config SOC_INTEL_CSE_SUB_PART_UPDATE |
| 169 | bool "Enable the CSE sub-partition update Feature" |
| 170 | default n |
| 171 | depends on SOC_INTEL_CSE_LITE_SKU |
| 172 | help |
| 173 | This config will enable CSE sub-partition firmware update feature and also will be used ensure |
| 174 | all the required configs are provided by mainboard. |
| 175 | |
| 176 | config SOC_INTEL_CSE_IOM_CBFS_NAME |
| 177 | string "CBFS name for CSE sub-partition IOM binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 178 | default "cse_iom" |
| 179 | help |
| 180 | CBFS entry name for Intel CSE sub-partition IOM binary |
| 181 | |
| 182 | config SOC_INTEL_CSE_IOM_CBFS_FILE |
| 183 | string "Intel CBFS path and file name for CSE sub-partition IOM binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 184 | default "" |
| 185 | help |
| 186 | CBFS path and file name for Intel CSE sub-partition IOM binary |
| 187 | |
| 188 | config SOC_INTEL_CSE_NPHY_CBFS_NAME |
| 189 | string "CBFS name for CSE sub-partition NPHY binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 190 | default "cse_nphy" |
| 191 | help |
| 192 | CBFS entry name for Intel CSE sub-partition NPHY binary |
| 193 | |
| 194 | config SOC_INTEL_CSE_NPHY_CBFS_FILE |
| 195 | string "Intel CBFS path and file name for CSE sub-partition NPHY binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 196 | default "" |
| 197 | help |
| 198 | CBFS path and file name for Intel CSE sub-partition NPHY binary |
| 199 | |
Krishna Prasad Bhat | a67a92e | 2022-02-25 10:45:55 +0530 | [diff] [blame] | 200 | config SOC_INTEL_CSE_LITE_COMPRESS_ME_RW |
| 201 | bool |
| 202 | default n |
| 203 | depends on SOC_INTEL_CSE_LITE_SKU |
| 204 | help |
| 205 | Enable compression on Intel CSE CBFS RW blob |
| 206 | |
Bora Guvendik | 860672e | 2021-09-26 17:25:48 -0700 | [diff] [blame] | 207 | config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY |
| 208 | def_bool n |
| 209 | depends on SOC_INTEL_CSE_LITE_SKU |
| 210 | help |
| 211 | Mainboard user to select this Kconfig in order to capture pre-cpu |
| 212 | reset boot performance telemetry data. |
| 213 | |
Krishna Prasad Bhat | ddd66ed | 2022-06-23 22:14:28 +0530 | [diff] [blame] | 214 | config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE |
| 215 | bool |
| 216 | default y |
| 217 | depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW |
| 218 | help |
| 219 | Use default flow of CSE FW Update in romstage when uncompressed ME_RW blobs are used. |
| 220 | |
| 221 | config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE |
| 222 | bool |
| 223 | default n |
| 224 | depends on SOC_INTEL_CSE_LITE_COMPRESS_ME_RW |
| 225 | help |
| 226 | Use this option for CSE FW Update when compressed blobs are used. |
| 227 | |
Dinesh Gehlot | 73fcbf1 | 2023-02-20 06:18:23 +0000 | [diff] [blame] | 228 | config SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 229 | bool |
| 230 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 231 | default n |
| 232 | help |
| 233 | This option config will allow SoC platform to use applicable ME specification. |
| 234 | The version based CSE measured ME specification data structures are defined at |
| 235 | common code. Enabling this option will use those CSE defined ME specification |
| 236 | for the SoC. User should select pertinent ME spec version along with this option. |
| 237 | |
| 238 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_12 |
| 239 | bool |
| 240 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 241 | help |
| 242 | This config will enable 'ME specification version 12'. It will ensure ME specific |
| 243 | declaration and uses of required data structures for Host firmware status registers. |
| 244 | |
| 245 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_13 |
| 246 | bool |
| 247 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 248 | help |
| 249 | This config will enable 'ME specification version 13'. It will ensure ME specific |
| 250 | declaration and uses of required data structures for Host firmware status registers. |
| 251 | |
| 252 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_15 |
| 253 | bool |
| 254 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 255 | help |
| 256 | This config will enable 'ME specification version 15'. It will ensure ME specific |
| 257 | declaration and uses of required data structures for Host firmware status registers. |
| 258 | |
| 259 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 |
| 260 | bool |
| 261 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 262 | help |
| 263 | This config will enable 'ME specification version 16'. It will ensure ME specific |
| 264 | declaration and uses of required data structures for Host firmware status registers. |
| 265 | |
| 266 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 |
| 267 | bool |
| 268 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 269 | help |
| 270 | This config will enable 'ME specification version 18'. It will ensure ME specific |
| 271 | declaration and uses of required data structures for Host firmware status registers. |
| 272 | |
| 273 | if SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 274 | |
| 275 | config ME_SPEC |
| 276 | int |
| 277 | default 12 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_12 |
| 278 | default 13 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_13 |
| 279 | default 15 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_15 |
| 280 | default 16 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 |
| 281 | default 18 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 |
| 282 | help |
| 283 | This config holds the ME spec version if defined. |
| 284 | |
| 285 | endif # SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 286 | |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 287 | if STITCH_ME_BIN |
| 288 | |
| 289 | config CSE_COMPONENTS_PATH |
| 290 | string "Path to directory containing all CSE input components to stitch" |
| 291 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/firmware" |
| 292 | help |
| 293 | This is the file path containing all the input CSE component files. |
| 294 | These will be used by cse_serger tool to stitch CSE image. |
| 295 | |
| 296 | config CSE_FPT_FILE |
| 297 | string "Name of CSE FPT file" |
| 298 | default "cse_fpt.bin" |
| 299 | help |
| 300 | This file is the CSE input binary as released by Intel in a CSE kit. |
| 301 | |
| 302 | config CSE_DATA_FILE |
| 303 | string "Name of CSE data file" |
| 304 | default "cse_data.bin" |
| 305 | help |
| 306 | This file is the CSE data binary typically generated by Intel FIT tool. |
| 307 | |
| 308 | config CSE_PMCP_FILE |
| 309 | string "Name of PMC file" |
| 310 | default "pmc.bin" |
| 311 | help |
| 312 | This file is the PMC input binary as released by Intel in a CSE kit. |
| 313 | |
| 314 | config CSE_IOMP_FILE |
| 315 | string "Name of IOM file" |
| 316 | default "iom.bin" |
| 317 | help |
| 318 | This file is the IOM input binary as released by Intel in a CSE kit. |
| 319 | |
| 320 | config CSE_TBTP_FILE |
| 321 | string "Name of TBT file" |
| 322 | default "tbt.bin" |
| 323 | help |
| 324 | This file is the TBT input binary as released by Intel in a CSE kit. |
| 325 | |
| 326 | config CSE_NPHY_FILE |
| 327 | string "Name of NPHY file" |
| 328 | default "nphy.bin" |
| 329 | help |
| 330 | This file is the NPHY input binary as released by Intel in a CSE kit. |
| 331 | |
| 332 | config CSE_PCHC_FILE |
| 333 | string "Name of PCHC file" |
| 334 | default "pchc.bin" |
| 335 | help |
| 336 | This file is the PCHC input binary as released by Intel in a CSE kit. |
| 337 | |
| 338 | config CSE_IUNP_FILE |
| 339 | string "Name of IUNIT file" |
| 340 | default "iunit.bin" |
| 341 | help |
| 342 | This file is the PCHC input binary as released by Intel in a CSE kit. |
| 343 | |
| 344 | config CSE_BPDT_VERSION |
| 345 | string |
| 346 | help |
| 347 | This config indicates the BPDT version used by CSE for a given SoC. |
| 348 | |
Ravindra N | 0709218 | 2021-12-06 10:11:51 +0530 | [diff] [blame] | 349 | config CSE_OEMP_FILE |
ravindr1 | 123312d | 2021-12-10 09:11:23 +0530 | [diff] [blame] | 350 | string "Name of OEM Key Manifest file" |
Ravindra N | 0709218 | 2021-12-06 10:11:51 +0530 | [diff] [blame] | 351 | default "oem_km.bin" |
ravindr1 | 123312d | 2021-12-10 09:11:23 +0530 | [diff] [blame] | 352 | help |
| 353 | OEM Key Manifest lists the public key hashes used for authenticating the |
| 354 | OEM created binaries to be loaded. This binary is generated by signing with |
| 355 | the key owned by trusted owner. |
Ravindra N | 0709218 | 2021-12-06 10:11:51 +0530 | [diff] [blame] | 356 | |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 357 | endif |