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review.coreboot.org / coreboot / 333edcc7c60bee7412773c33a715b83063b4eb25
commit333edcc7c60bee7412773c33a715b83063b4eb25[log] [tgz]
authorKrishna Prasad Bhat <krishna.p.bhat.d@intel.com>Fri Nov 26 06:52:27 2021 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>Fri Dec 03 21:48:20 2021 +0000
treef2d7d5500566df7b6fbdcf333c393cab02556ca8
parent49c25f2cefe63d9607c4b930097e11e073d0ed25 [diff]
soc/intel/common: Add support for CSE IOM/NPHY sub-parition update

This patch adds the following support to coreboot
1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B
partition of BIOS
2. Helper functions to support update.

Pre-requisites to enable IOM/NPHY FW Update:
1. NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and
   FW_MAIN_B through board configuration files.
   CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path
   SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path

2. Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition
   NPHY/IOM update.

coreboot follows below procedure to update NPHY and IOM:
NPHY Update:
1. coreboot will navigate through the CSE region,
   identify the CSE’s NPHY FW version and BIOS NPHY version.
2. Compare both versions, if there is a difference, CSE will trigger an
   NPHY FW update. Otherwise, skips the NPHY FW update.

IOM Update:
1. coreboot will navigate through the CSE region, identify CSE's IOM
    FW version and BIOS IOM version.
2. Compares both versions, if there is a difference, coreboot will
   trigger an IOM FW update.Otherwise, skip IOM FW update.

Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT
PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE
boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only
if CSE boots from CSE RO Boot partition.

Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then
triggers update of NPHY and IOM FW in the CSE Region(RO and RW).

coreboot triggers NPHY/IOM update procedure in all ChromeOS boot
modes(Normal and Recovery).

BUG=b:202143532
BRANCH=None
TEST=Build and verify CSE sub-partitions IOM and NPHY are getting
updated with CBFS IOM and NPHY blobs.
Verified TBT, type-C display, NVMe, SD card, WWAN, Wifi working after
the update.

Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
5 files changed
tree: f2d7d5500566df7b6fbdcf333c393cab02556ca8
  1. 3rdparty/
  2. configs/
  3. Documentation/
  4. LICENSES/
  5. payloads/
  6. spd/
  7. src/
  8. tests/
  9. util/
  10. .checkpatch.conf
  11. .clang-format
  12. .editorconfig
  13. .gitignore
  14. .gitmodules
  15. .gitreview
  16. AUTHORS
  17. COPYING
  18. gnat.adc
  19. MAINTAINERS
  20. Makefile
  21. Makefile.inc
  22. README.md
  23. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.