Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1 | /** @file |
| 2 | |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 3 | Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 4 | |
| 5 | Redistribution and use in source and binary forms, with or without modification, |
| 6 | are permitted provided that the following conditions are met: |
| 7 | |
| 8 | * Redistributions of source code must retain the above copyright notice, this |
| 9 | list of conditions and the following disclaimer. |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, this |
| 11 | list of conditions and the following disclaimer in the documentation and/or |
| 12 | other materials provided with the distribution. |
| 13 | * Neither the name of Intel Corporation nor the names of its contributors may |
| 14 | be used to endorse or promote products derived from this software without |
| 15 | specific prior written permission. |
| 16 | |
| 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 27 | THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | |
| 29 | This file is automatically generated. Please do NOT modify !!! |
| 30 | |
| 31 | **/ |
| 32 | |
| 33 | #ifndef __FSPMUPD_H__ |
| 34 | #define __FSPMUPD_H__ |
| 35 | |
| 36 | #include <FspUpd.h> |
| 37 | |
| 38 | #pragma pack(1) |
| 39 | |
| 40 | |
| 41 | #include <MemInfoHob.h> |
| 42 | |
| 43 | /// |
| 44 | /// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. |
| 45 | /// |
| 46 | typedef struct { |
| 47 | UINT8 Revision; ///< Chipset Init Info Revision |
| 48 | UINT8 Rsvd[3]; ///< Reserved |
| 49 | UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table |
| 50 | UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table |
| 51 | } CHIPSET_INIT_INFO; |
| 52 | |
| 53 | |
| 54 | /** Fsp M Configuration |
| 55 | **/ |
| 56 | typedef struct { |
| 57 | |
| 58 | /** Offset 0x0040 - Platform Reserved Memory Size |
| 59 | The minimum platform memory size required to pass control into DXE |
| 60 | **/ |
| 61 | UINT64 PlatformMemorySize; |
| 62 | |
| 63 | /** Offset 0x0048 - SPD Data Length |
| 64 | Length of SPD Data |
| 65 | 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes |
| 66 | **/ |
| 67 | UINT16 MemorySpdDataLen; |
| 68 | |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 69 | /** Offset 0x004A - Enable above 4GB MMIO resource support |
| 70 | Enable/disable above 4GB MMIO resource support |
| 71 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 72 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 73 | UINT8 EnableAbove4GBMmio; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 74 | |
Srinidhi N Kaushik | 15b439e | 2022-07-29 16:06:05 -0700 | [diff] [blame] | 75 | /** Offset 0x004B - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 76 | **/ |
Srinidhi N Kaushik | 15b439e | 2022-07-29 16:06:05 -0700 | [diff] [blame] | 77 | UINT8 Reserved0; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 78 | |
| 79 | /** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 |
| 80 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 81 | **/ |
| 82 | UINT32 MemorySpdPtr000; |
| 83 | |
| 84 | /** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 |
| 85 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 86 | **/ |
| 87 | UINT32 MemorySpdPtr001; |
| 88 | |
| 89 | /** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 |
| 90 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 91 | **/ |
| 92 | UINT32 MemorySpdPtr010; |
| 93 | |
| 94 | /** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 |
| 95 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 96 | **/ |
| 97 | UINT32 MemorySpdPtr011; |
| 98 | |
| 99 | /** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 |
| 100 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 101 | **/ |
| 102 | UINT32 MemorySpdPtr020; |
| 103 | |
| 104 | /** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 |
| 105 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 106 | **/ |
| 107 | UINT32 MemorySpdPtr021; |
| 108 | |
| 109 | /** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 |
| 110 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 111 | **/ |
| 112 | UINT32 MemorySpdPtr030; |
| 113 | |
| 114 | /** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 |
| 115 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 116 | **/ |
| 117 | UINT32 MemorySpdPtr031; |
| 118 | |
| 119 | /** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 |
| 120 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 121 | **/ |
| 122 | UINT32 MemorySpdPtr100; |
| 123 | |
| 124 | /** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 |
| 125 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 126 | **/ |
| 127 | UINT32 MemorySpdPtr101; |
| 128 | |
| 129 | /** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 |
| 130 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 131 | **/ |
| 132 | UINT32 MemorySpdPtr110; |
| 133 | |
| 134 | /** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 |
| 135 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 136 | **/ |
| 137 | UINT32 MemorySpdPtr111; |
| 138 | |
| 139 | /** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 |
| 140 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 141 | **/ |
| 142 | UINT32 MemorySpdPtr120; |
| 143 | |
| 144 | /** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 |
| 145 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 146 | **/ |
| 147 | UINT32 MemorySpdPtr121; |
| 148 | |
| 149 | /** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 |
| 150 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 151 | **/ |
| 152 | UINT32 MemorySpdPtr130; |
| 153 | |
| 154 | /** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 |
| 155 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 156 | **/ |
| 157 | UINT32 MemorySpdPtr131; |
| 158 | |
| 159 | /** Offset 0x008C - RcompResistor settings |
| 160 | Indicates RcompResistor settings: Board-dependent |
| 161 | **/ |
| 162 | UINT16 RcompResistor; |
| 163 | |
| 164 | /** Offset 0x008E - RcompTarget settings |
| 165 | RcompTarget settings: board-dependent |
| 166 | **/ |
| 167 | UINT16 RcompTarget[5]; |
| 168 | |
| 169 | /** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0 |
| 170 | Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| 171 | **/ |
| 172 | UINT8 DqsMapCpu2DramMc0Ch0[2]; |
| 173 | |
| 174 | /** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1 |
| 175 | Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| 176 | **/ |
| 177 | UINT8 DqsMapCpu2DramMc0Ch1[2]; |
| 178 | |
| 179 | /** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2 |
| 180 | Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| 181 | **/ |
| 182 | UINT8 DqsMapCpu2DramMc0Ch2[2]; |
| 183 | |
| 184 | /** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3 |
| 185 | Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| 186 | **/ |
| 187 | UINT8 DqsMapCpu2DramMc0Ch3[2]; |
| 188 | |
| 189 | /** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0 |
| 190 | Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| 191 | **/ |
| 192 | UINT8 DqsMapCpu2DramMc1Ch0[2]; |
| 193 | |
| 194 | /** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1 |
| 195 | Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| 196 | **/ |
| 197 | UINT8 DqsMapCpu2DramMc1Ch1[2]; |
| 198 | |
| 199 | /** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2 |
| 200 | Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| 201 | **/ |
| 202 | UINT8 DqsMapCpu2DramMc1Ch2[2]; |
| 203 | |
| 204 | /** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3 |
| 205 | Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| 206 | **/ |
| 207 | UINT8 DqsMapCpu2DramMc1Ch3[2]; |
| 208 | |
| 209 | /** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0 |
| 210 | Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| 211 | **/ |
| 212 | UINT8 DqMapCpu2DramMc0Ch0[16]; |
| 213 | |
| 214 | /** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1 |
| 215 | Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| 216 | **/ |
| 217 | UINT8 DqMapCpu2DramMc0Ch1[16]; |
| 218 | |
| 219 | /** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2 |
| 220 | Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| 221 | **/ |
| 222 | UINT8 DqMapCpu2DramMc0Ch2[16]; |
| 223 | |
| 224 | /** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3 |
| 225 | Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| 226 | **/ |
| 227 | UINT8 DqMapCpu2DramMc0Ch3[16]; |
| 228 | |
| 229 | /** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0 |
| 230 | Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| 231 | **/ |
| 232 | UINT8 DqMapCpu2DramMc1Ch0[16]; |
| 233 | |
| 234 | /** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1 |
| 235 | Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| 236 | **/ |
| 237 | UINT8 DqMapCpu2DramMc1Ch1[16]; |
| 238 | |
| 239 | /** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2 |
| 240 | Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| 241 | **/ |
| 242 | UINT8 DqMapCpu2DramMc1Ch2[16]; |
| 243 | |
| 244 | /** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3 |
| 245 | Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| 246 | **/ |
| 247 | UINT8 DqMapCpu2DramMc1Ch3[16]; |
| 248 | |
| 249 | /** Offset 0x0128 - Dqs Pins Interleaved Setting |
| 250 | Indicates DqPinsInterleaved setting: board-dependent |
| 251 | $EN_DIS |
| 252 | **/ |
| 253 | UINT8 DqPinsInterleaved; |
| 254 | |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 255 | /** Offset 0x0129 - Smram Mask |
| 256 | The SMM Regions AB-SEG and/or H-SEG reserved |
| 257 | 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 258 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 259 | UINT8 SmramMask; |
| 260 | |
| 261 | /** Offset 0x012A - MRC Fast Boot |
| 262 | Enables/Disable the MRC fast path thru the MRC |
| 263 | $EN_DIS |
| 264 | **/ |
| 265 | UINT8 MrcFastBoot; |
| 266 | |
| 267 | /** Offset 0x012B - Rank Margin Tool per Task |
| 268 | This option enables the user to execute Rank Margin Tool per major training step |
| 269 | in the MRC. |
| 270 | $EN_DIS |
| 271 | **/ |
| 272 | UINT8 RmtPerTask; |
| 273 | |
| 274 | /** Offset 0x012C - Training Trace |
| 275 | This option enables the trained state tracing feature in MRC. This feature will |
| 276 | print out the key training parameters state across major training steps. |
| 277 | $EN_DIS |
| 278 | **/ |
| 279 | UINT8 TrainTrace; |
| 280 | |
| 281 | /** Offset 0x012D - Reserved |
| 282 | **/ |
Srinidhi N Kaushik | 15b439e | 2022-07-29 16:06:05 -0700 | [diff] [blame] | 283 | UINT8 Reserved1[3]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 284 | |
| 285 | /** Offset 0x0130 - Tseg Size |
| 286 | Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build |
| 287 | 0x0400000:4MB, 0x01000000:16MB |
| 288 | **/ |
| 289 | UINT32 TsegSize; |
| 290 | |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 291 | /** Offset 0x0134 - MMIO Size |
| 292 | Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 293 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 294 | UINT16 MmioSize; |
| 295 | |
| 296 | /** Offset 0x0136 - Probeless Trace |
| 297 | Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. |
| 298 | This also requires IED to be enabled. |
| 299 | $EN_DIS |
| 300 | **/ |
| 301 | UINT8 ProbelessTrace; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 302 | |
| 303 | /** Offset 0x0137 - Enable SMBus |
| 304 | Enable/disable SMBus controller. |
| 305 | $EN_DIS |
| 306 | **/ |
| 307 | UINT8 SmbusEnable; |
| 308 | |
| 309 | /** Offset 0x0138 - Spd Address Tabl |
| 310 | Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used |
| 311 | if SPD Address is 00 |
| 312 | **/ |
| 313 | UINT8 SpdAddressTable[16]; |
| 314 | |
| 315 | /** Offset 0x0148 - Platform Debug Consent |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 316 | Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 317 | \n |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 318 | Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 319 | \n |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 320 | Enabled Trace power off: TraceHub is powergated, provide setting close to functional |
| 321 | low power state\n |
| 322 | \n |
| 323 | Manual: user needs to configure Advanced Debug Settings manually, aimed at advanced users |
| 324 | 0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready, 6:Enable Trace Power-Off, 7:Manual |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 325 | **/ |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 326 | UINT8 PlatformDebugOption; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 327 | |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 328 | /** Offset 0x0149 - DCI Enable |
| 329 | Determine if to enable DCI debug from host |
| 330 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 331 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 332 | UINT8 DciEn; |
| 333 | |
| 334 | /** Offset 0x014A - Reserved |
| 335 | **/ |
Srinidhi N Kaushik | 15b439e | 2022-07-29 16:06:05 -0700 | [diff] [blame] | 336 | UINT8 Reserved2; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 337 | |
| 338 | /** Offset 0x014B - DCI DbC Mode |
| 339 | Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: |
| 340 | Set both USB2/3DBCEN; No Change: Comply with HW value |
| 341 | 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change |
| 342 | **/ |
| 343 | UINT8 DciDbcMode; |
| 344 | |
| 345 | /** Offset 0x014C - USB3 Type-C UFP2DFP Kernel/Platform Debug Support |
| 346 | This BIOS option enables kernel and platform debug for USB3 interface over a UFP |
| 347 | Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. |
| 348 | 0:Disabled, 1:Enabled, 2:No Change |
| 349 | **/ |
| 350 | UINT8 DciUsb3TypecUfpDbg; |
| 351 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 352 | /** Offset 0x014D - SOC Trace Hub Mode |
| 353 | Enable/Disable SOC TraceHub |
| 354 | $EN_DIS |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 355 | **/ |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 356 | UINT8 SocTraceHubMode; |
| 357 | |
| 358 | /** Offset 0x014E - SOC Trace Hub Memory Region 0 buffer Size |
| 359 | Select size of memory region 0 buffer. Memory allocated by BIOS only applies to |
| 360 | ITH tool running on the host. For ITH tool running on the target, choose None/OS, |
| 361 | memory shall be allocated by tool. User should be cautious to choose the amount |
| 362 | of memory. If chosen size is larger than half of system memory, setup will automatically |
| 363 | rollback to default value. |
| 364 | 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, |
| 365 | 0x0C:4GB, 0x0D:8GB, 0x0E:0MB |
| 366 | **/ |
| 367 | UINT16 SocTraceHubMemReg0Size; |
| 368 | |
| 369 | /** Offset 0x0150 - SOC Trace Hub Memory Region 1 buffer Size |
| 370 | Select size of memory region 1 buffer. Memory allocated by BIOS only applies to |
| 371 | ITH tool running on the host. For ITH tool running on the target, choose None/OS, |
| 372 | memory shall be allocated by tool. User should be cautious to choose the amount |
| 373 | of memory. If chosen size is larger than half of system memory, setup will automatically |
| 374 | rollback to default value. |
| 375 | 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, |
| 376 | 0x0C:4GB, 0x0D:8GB, 0x0E:0MB |
| 377 | **/ |
| 378 | UINT16 SocTraceHubMemReg1Size; |
| 379 | |
| 380 | /** Offset 0x0152 - Reserved |
| 381 | **/ |
| 382 | UINT8 Reserved3; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 383 | |
| 384 | /** Offset 0x0153 - PCH Trace Hub Mode |
| 385 | Enable/Disable PCH TraceHub |
| 386 | $EN_DIS |
| 387 | **/ |
| 388 | UINT8 PchTraceHubMode; |
| 389 | |
| 390 | /** Offset 0x0154 - PCH Trace Hub Memory Region 0 buffer Size |
| 391 | Select size of memory region 0 buffer. Memory allocated by BIOS only applies to |
| 392 | ITH tool running on the host. For ITH tool running on the target, choose None/OS, |
| 393 | memory shall be allocated by tool. User should be cautious to choose the amount |
| 394 | of memory. If chosen size is larger than half of system memory, setup will automatically |
| 395 | rollback to default value. |
| 396 | 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, |
| 397 | 0x0C:4GB, 0x0D:8GB, 0x0E:0MB |
| 398 | **/ |
| 399 | UINT16 PchTraceHubMemReg0Size; |
| 400 | |
| 401 | /** Offset 0x0156 - PCH Trace Hub Memory Region 1 buffer Size |
| 402 | Select size of memory region 1 buffer. Memory allocated by BIOS only applies to |
| 403 | ITH tool running on the host. For ITH tool running on the target, choose None/OS, |
| 404 | memory shall be allocated by tool. User should be cautious to choose the amount |
| 405 | of memory. If chosen size is larger than half of system memory, setup will automatically |
| 406 | rollback to default value. |
| 407 | 0x00:1MB, 0x03:8MB, 0x06:64MB, 0x07:128MB, 0x08:256MB, 0x09:512MB, 0x0A:1GB, 0x0B:2GB, |
| 408 | 0x0C:4GB, 0x0D:8GB, 0x0E:0MB |
| 409 | **/ |
| 410 | UINT16 PchTraceHubMemReg1Size; |
| 411 | |
| 412 | /** Offset 0x0158 - Reserved |
| 413 | **/ |
Srinidhi N Kaushik | 15b439e | 2022-07-29 16:06:05 -0700 | [diff] [blame] | 414 | UINT8 Reserved4[4]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 415 | |
| 416 | /** Offset 0x015C - HD Audio DMIC Link Clock Select |
| 417 | Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB |
| 418 | 0: Both, 1: ClkA, 2: ClkB |
| 419 | **/ |
| 420 | UINT8 PchHdaAudioLinkDmicClockSelect[2]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 421 | |
| 422 | /** Offset 0x015E - State of X2APIC_OPT_OUT bit in the DMAR table |
| 423 | 0=Disable/Clear, 1=Enable/Set |
| 424 | $EN_DIS |
| 425 | **/ |
| 426 | UINT8 X2ApicOptOut; |
| 427 | |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 428 | /** Offset 0x015F - State of DMA_CONTROL_GUARANTEE bit in the DMAR table |
| 429 | 0=Disable/Clear, 1=Enable/Set |
| 430 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 431 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 432 | UINT8 DmaControlGuarantee; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 433 | |
| 434 | /** Offset 0x0160 - Base addresses for VT-d function MMIO access |
| 435 | Base addresses for VT-d MMIO access per VT-d engine |
| 436 | **/ |
| 437 | UINT32 VtdBaseAddress[9]; |
| 438 | |
| 439 | /** Offset 0x0184 - Disable VT-d |
| 440 | 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) |
| 441 | $EN_DIS |
| 442 | **/ |
| 443 | UINT8 VtdDisable; |
| 444 | |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 445 | /** Offset 0x0185 - Vtd Programming for Igd |
| 446 | 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar |
| 447 | programming disabled) |
| 448 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 449 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 450 | UINT8 VtdIgdEnable; |
| 451 | |
| 452 | /** Offset 0x0186 - Vtd Programming for Iop |
| 453 | 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar |
| 454 | programming disabled) |
| 455 | $EN_DIS |
| 456 | **/ |
| 457 | UINT8 VtdIopEnable; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 458 | |
| 459 | /** Offset 0x0187 - Internal Graphics Pre-allocated Memory |
| 460 | Size of memory preallocated for internal graphics. |
| 461 | 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, |
| 462 | 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, |
| 463 | 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB |
| 464 | **/ |
| 465 | UINT8 IgdDvmt50PreAlloc; |
| 466 | |
| 467 | /** Offset 0x0188 - Internal Graphics |
| 468 | Enable/disable internal graphics. |
| 469 | $EN_DIS |
| 470 | **/ |
| 471 | UINT8 InternalGfx; |
| 472 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 473 | /** Offset 0x0189 - Reserved |
| 474 | **/ |
| 475 | UINT8 Reserved5; |
| 476 | |
| 477 | /** Offset 0x018A - Board Type |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 478 | MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile |
| 479 | Halo, 7=UP Server |
| 480 | 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server |
| 481 | **/ |
| 482 | UINT8 UserBd; |
| 483 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 484 | /** Offset 0x018B - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 485 | **/ |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 486 | UINT8 Reserved6; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 487 | |
| 488 | /** Offset 0x018C - DDR Frequency Limit |
| 489 | Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, |
| 490 | 2133, 2400, 2667, 2933 and 0 for Auto. |
| 491 | 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto |
| 492 | **/ |
| 493 | UINT16 DdrFreqLimit; |
| 494 | |
| 495 | /** Offset 0x018E - SAGV |
| 496 | System Agent dynamic frequency support. |
| 497 | 0:Disabled, 1:Enabled |
| 498 | **/ |
| 499 | UINT8 SaGv; |
| 500 | |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 501 | /** Offset 0x018F - SAGV WP Mask |
| 502 | System Agent dynamic frequency workpoints that memory will be training at the enabled |
| 503 | frequencies. |
| 504 | 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 505 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 506 | UINT8 SaGvWpMask; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 507 | |
| 508 | /** Offset 0x0190 - Memory Test on Warm Boot |
| 509 | Run Base Memory Test on Warm Boot |
| 510 | 0:Disable, 1:Enable |
| 511 | **/ |
| 512 | UINT8 MemTestOnWarmBoot; |
| 513 | |
| 514 | /** Offset 0x0191 - DDR Speed Control |
| 515 | DDR Frequency and Gear control for all SAGV points. |
| 516 | 0:Auto, 1:Manual |
| 517 | **/ |
| 518 | UINT8 DdrSpeedControl; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 519 | |
| 520 | /** Offset 0x0192 - Controller 0 Channel 0 DIMM Control |
| 521 | Enable / Disable DIMMs on Controller 0 Channel 0 |
| 522 | $EN_DIS |
| 523 | **/ |
| 524 | UINT8 DisableMc0Ch0; |
| 525 | |
| 526 | /** Offset 0x0193 - Controller 0 Channel 1 DIMM Control |
| 527 | Enable / Disable DIMMs on Controller 0 Channel 1 |
| 528 | $EN_DIS |
| 529 | **/ |
| 530 | UINT8 DisableMc0Ch1; |
| 531 | |
| 532 | /** Offset 0x0194 - Controller 0 Channel 2 DIMM Control |
| 533 | Enable / Disable DIMMs on Controller 0 Channel 2 |
| 534 | $EN_DIS |
| 535 | **/ |
| 536 | UINT8 DisableMc0Ch2; |
| 537 | |
| 538 | /** Offset 0x0195 - Controller 0 Channel 3 DIMM Control |
| 539 | Enable / Disable DIMMs on Controller 0 Channel 3 |
| 540 | $EN_DIS |
| 541 | **/ |
| 542 | UINT8 DisableMc0Ch3; |
| 543 | |
| 544 | /** Offset 0x0196 - Controller 1 Channel 0 DIMM Control |
| 545 | Enable / Disable DIMMs on Controller 1 Channel 0 |
| 546 | $EN_DIS |
| 547 | **/ |
| 548 | UINT8 DisableMc1Ch0; |
| 549 | |
| 550 | /** Offset 0x0197 - Controller 1 Channel 1 DIMM Control |
| 551 | Enable / Disable DIMMs on Controller 1 Channel 1 |
| 552 | $EN_DIS |
| 553 | **/ |
| 554 | UINT8 DisableMc1Ch1; |
| 555 | |
| 556 | /** Offset 0x0198 - Controller 1 Channel 2 DIMM Control |
| 557 | Enable / Disable DIMMs on Controller 1 Channel 2 |
| 558 | $EN_DIS |
| 559 | **/ |
| 560 | UINT8 DisableMc1Ch2; |
| 561 | |
| 562 | /** Offset 0x0199 - Controller 1 Channel 3 DIMM Control |
| 563 | Enable / Disable DIMMs on Controller 1 Channel 3 |
| 564 | $EN_DIS |
| 565 | **/ |
| 566 | UINT8 DisableMc1Ch3; |
| 567 | |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 568 | /** Offset 0x019A - Scrambler Support |
| 569 | This option enables data scrambling in memory. |
| 570 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 571 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 572 | UINT8 ScramblerSupport; |
| 573 | |
| 574 | /** Offset 0x019B - SPD Profile Selected |
| 575 | Select DIMM timing profile. Options are 0:Default SPD Profile, 1:Custom Profile, |
| 576 | 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP Profile 3, 5:XMP User Profile 4, 6:XMP |
| 577 | User Profile 5 |
| 578 | 0:Default SPD Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP |
| 579 | Profile 3, 5:XMP User Profile 4, 6:XMP User Profile 5 |
| 580 | **/ |
| 581 | UINT8 SpdProfileSelected; |
| 582 | |
| 583 | /** Offset 0x019C - Reserved |
| 584 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 585 | UINT8 Reserved7[102]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 586 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 587 | /** Offset 0x0202 - Memory Reference Clock |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 588 | 100MHz, 133MHz. |
| 589 | 0:133MHz, 1:100MHz |
| 590 | **/ |
| 591 | UINT8 RefClk; |
| 592 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 593 | /** Offset 0x0203 - Reserved |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 594 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 595 | UINT8 Reserved8[9]; |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 596 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 597 | /** Offset 0x020C - Memory Vdd Voltage |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 598 | DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM |
| 599 | chips) in millivolts. <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc. |
| 600 | 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 |
| 601 | Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts |
| 602 | **/ |
| 603 | UINT16 VddVoltage; |
| 604 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 605 | /** Offset 0x020E - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 606 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 607 | UINT8 Reserved9[4]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 608 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 609 | /** Offset 0x0212 - Memory Ratio |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 610 | Automatic or the frequency will equal ratio times reference clock. Set to Auto to |
| 611 | recalculate memory timings listed below. |
| 612 | 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 |
| 613 | **/ |
| 614 | UINT16 Ratio; |
| 615 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 616 | /** Offset 0x0214 - tCL |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 617 | CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 618 | == 1 (Custom Profile). |
| 619 | **/ |
| 620 | UINT8 tCL; |
| 621 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 622 | /** Offset 0x0215 - tCWL |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 623 | Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 624 | == 1 (Custom Profile). |
| 625 | **/ |
| 626 | UINT8 tCWL; |
| 627 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 628 | /** Offset 0x0216 - tFAW |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 629 | Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 630 | == 1 (Custom Profile). |
| 631 | **/ |
| 632 | UINT16 tFAW; |
| 633 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 634 | /** Offset 0x0218 - tRAS |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 635 | RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 636 | == 1 (Custom Profile). |
| 637 | **/ |
| 638 | UINT16 tRAS; |
| 639 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 640 | /** Offset 0x021A - tRCD/tRP |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 641 | RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used |
| 642 | if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). |
| 643 | **/ |
| 644 | UINT8 tRCDtRP; |
| 645 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 646 | /** Offset 0x021B - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 647 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 648 | UINT8 Reserved10; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 649 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 650 | /** Offset 0x021C - tREFI |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 651 | Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 652 | == 1 (Custom Profile). |
| 653 | **/ |
| 654 | UINT16 tREFI; |
| 655 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 656 | /** Offset 0x021E - tRFC |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 657 | Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 658 | == 1 (Custom Profile). |
| 659 | **/ |
| 660 | UINT16 tRFC; |
| 661 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 662 | /** Offset 0x0220 - tRRD |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 663 | Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 664 | == 1 (Custom Profile). |
| 665 | **/ |
| 666 | UINT8 tRRD; |
| 667 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 668 | /** Offset 0x0221 - tRTP |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 669 | Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used |
| 670 | if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). |
| 671 | **/ |
| 672 | UINT8 tRTP; |
| 673 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 674 | /** Offset 0x0222 - tWR |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 675 | Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, |
| 676 | 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). |
| 677 | 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, |
| 678 | 34:34, 40:40 |
| 679 | **/ |
| 680 | UINT8 tWR; |
| 681 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 682 | /** Offset 0x0223 - tWTR |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 683 | Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 684 | == 1 (Custom Profile). |
| 685 | **/ |
| 686 | UINT8 tWTR; |
| 687 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 688 | /** Offset 0x0224 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 689 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 690 | UINT8 Reserved11[12]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 691 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 692 | /** Offset 0x0230 - NMode |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 693 | System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N |
| 694 | **/ |
| 695 | UINT8 NModeSupport; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 696 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 697 | /** Offset 0x0231 - Enable Intel HD Audio (Azalia) |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 698 | 0: Disable, 1: Enable (Default) Azalia controller |
| 699 | $EN_DIS |
| 700 | **/ |
| 701 | UINT8 PchHdaEnable; |
| 702 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 703 | /** Offset 0x0232 - Enable PCH ISH Controller |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 704 | 0: Disable, 1: Enable (Default) ISH Controller |
| 705 | $EN_DIS |
| 706 | **/ |
| 707 | UINT8 PchIshEnable; |
| 708 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 709 | /** Offset 0x0233 - Reserved |
| 710 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 711 | UINT8 Reserved12[7]; |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 712 | |
| 713 | /** Offset 0x023A - SAGV Gear Ratio |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 714 | Gear Selection for SAGV points. 0 - Auto, 2-Gear 2, 4-Gear 4 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 715 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 716 | UINT8 SaGvGear[4]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 717 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 718 | /** Offset 0x023E - SAGV Frequency |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 719 | SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. |
| 720 | **/ |
| 721 | UINT16 SaGvFreq[4]; |
| 722 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 723 | /** Offset 0x0246 - SAGV Disabled Gear Ratio |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 724 | Gear Selection for SAGV Disabled. 0 - Auto, 2-Gear 2, 2-Gear 4 |
| 725 | **/ |
| 726 | UINT8 GearRatio; |
| 727 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 728 | /** Offset 0x0247 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 729 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 730 | UINT8 Reserved13[69]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 731 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 732 | /** Offset 0x028C - MMIO size adjustment for AUTO mode |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 733 | Positive number means increasing MMIO size, Negative value means decreasing MMIO |
| 734 | size: 0 (Default)=no change to AUTO mode MMIO size |
| 735 | **/ |
| 736 | UINT16 MmioSizeAdjustment; |
| 737 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 738 | /** Offset 0x028E - Selection of the primary display device |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 739 | 0=iGFX, 3(Default)=AUTO, 4=Hybrid Graphics |
| 740 | 0:iGFX, 3:AUTO, 4:Hybrid Graphics |
| 741 | **/ |
| 742 | UINT8 PrimaryDisplay; |
| 743 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 744 | /** Offset 0x028F - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 745 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 746 | UINT8 Reserved14; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 747 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 748 | /** Offset 0x0290 - Temporary MMIO address for GMADR |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 749 | Obsolete field now and it has been extended to 64 bit address, used LMemBar |
| 750 | **/ |
| 751 | UINT32 GmAdr; |
| 752 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 753 | /** Offset 0x0294 - Temporary MMIO address for GTTMMADR |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 754 | The reference code will use this as Temporary MMIO address space to access GTTMMADR |
| 755 | Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr |
| 756 | to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO |
| 757 | + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) |
| 758 | **/ |
| 759 | UINT32 GttMmAdr; |
| 760 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 761 | /** Offset 0x0298 - Enable/Disable MRC TXT dependency |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 762 | When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): |
| 763 | MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization |
| 764 | $EN_DIS |
| 765 | **/ |
| 766 | UINT8 TxtImplemented; |
| 767 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 768 | /** Offset 0x0299 - Enable/Disable SA OcSupport |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 769 | Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport |
| 770 | $EN_DIS |
| 771 | **/ |
| 772 | UINT8 SaOcSupport; |
| 773 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 774 | /** Offset 0x029A - GT slice Voltage Mode |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 775 | 0(Default): Adaptive, 1: Override |
| 776 | 0: Adaptive, 1: Override |
| 777 | **/ |
| 778 | UINT8 GtVoltageMode; |
| 779 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 780 | /** Offset 0x029B - Maximum GTs turbo ratio override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 781 | 0(Default)=Minimal/Auto, 60=Maximum |
| 782 | **/ |
| 783 | UINT8 GtMaxOcRatio; |
| 784 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 785 | /** Offset 0x029C - The voltage offset applied to GT slice |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 786 | 0(Default)=Minimal, 1000=Maximum |
| 787 | **/ |
| 788 | UINT16 GtVoltageOffset; |
| 789 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 790 | /** Offset 0x029E - The GT slice voltage override which is applied to the entire range of GT frequencies |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 791 | 0(Default)=Minimal, 2000=Maximum |
| 792 | **/ |
| 793 | UINT16 GtVoltageOverride; |
| 794 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 795 | /** Offset 0x02A0 - adaptive voltage applied during turbo frequencies |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 796 | 0(Default)=Minimal, 2000=Maximum |
| 797 | **/ |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 798 | UINT16 GtAdaptiveVoltage; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 799 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 800 | /** Offset 0x02A2 - voltage offset applied to the SA |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 801 | 0(Default)=Minimal, 1000=Maximum |
| 802 | **/ |
| 803 | UINT16 SaVoltageOffset; |
| 804 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 805 | /** Offset 0x02A4 - PCIe root port Function number for Hybrid Graphics dGPU |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 806 | Root port Index number to indicate which PCIe root port has dGPU |
| 807 | **/ |
| 808 | UINT8 RootPortIndex; |
| 809 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 810 | /** Offset 0x02A5 - Realtime Memory Timing |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 811 | 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform |
| 812 | realtime memory timing changes after MRC_DONE. |
| 813 | 0: Disabled, 1: Enabled |
| 814 | **/ |
| 815 | UINT8 RealtimeMemoryTiming; |
| 816 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 817 | /** Offset 0x02A6 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 818 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 819 | UINT8 Reserved15; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 820 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 821 | /** Offset 0x02A7 - Enable/Disable SA IPU |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 822 | Enable(Default): Enable SA IPU, Disable: Disable SA IPU |
| 823 | $EN_DIS |
| 824 | **/ |
| 825 | UINT8 SaIpuEnable; |
| 826 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 827 | /** Offset 0x02A8 - IMGU CLKOUT Configuration |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 828 | The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>. |
| 829 | $EN_DIS |
| 830 | **/ |
| 831 | UINT8 ImguClkOutEn[6]; |
| 832 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 833 | /** Offset 0x02AE - Program GPIOs for LFP on DDI port-A device |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 834 | 0=Disabled,1(Default)=eDP, 2=MIPI DSI |
| 835 | 0:Disabled, 1:eDP, 2:MIPI DSI |
| 836 | **/ |
| 837 | UINT8 DdiPortAConfig; |
| 838 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 839 | /** Offset 0x02AF - Program GPIOs for LFP on DDI port-B device |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 840 | 0(Default)=Disabled,1=eDP, 2=MIPI DSI |
| 841 | 0:Disabled, 1:eDP, 2:MIPI DSI |
| 842 | **/ |
| 843 | UINT8 DdiPortBConfig; |
| 844 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 845 | /** Offset 0x02B0 - Enable or disable HPD of DDI port A |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 846 | 0(Default)=Disable, 1=Enable |
| 847 | $EN_DIS |
| 848 | **/ |
| 849 | UINT8 DdiPortAHpd; |
| 850 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 851 | /** Offset 0x02B1 - Enable or disable HPD of DDI port B |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 852 | 0=Disable, 1(Default)=Enable |
| 853 | $EN_DIS |
| 854 | **/ |
| 855 | UINT8 DdiPortBHpd; |
| 856 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 857 | /** Offset 0x02B2 - Enable or disable HPD of DDI port C |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 858 | 0(Default)=Disable, 1=Enable |
| 859 | $EN_DIS |
| 860 | **/ |
| 861 | UINT8 DdiPortCHpd; |
| 862 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 863 | /** Offset 0x02B3 - Enable or disable HPD of DDI port 1 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 864 | 0=Disable, 1(Default)=Enable |
| 865 | $EN_DIS |
| 866 | **/ |
| 867 | UINT8 DdiPort1Hpd; |
| 868 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 869 | /** Offset 0x02B4 - Enable or disable HPD of DDI port 2 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 870 | 0(Default)=Disable, 1=Enable |
| 871 | $EN_DIS |
| 872 | **/ |
| 873 | UINT8 DdiPort2Hpd; |
| 874 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 875 | /** Offset 0x02B5 - Enable or disable HPD of DDI port 3 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 876 | 0(Default)=Disable, 1=Enable |
| 877 | $EN_DIS |
| 878 | **/ |
| 879 | UINT8 DdiPort3Hpd; |
| 880 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 881 | /** Offset 0x02B6 - Enable or disable HPD of DDI port 4 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 882 | 0(Default)=Disable, 1=Enable |
| 883 | $EN_DIS |
| 884 | **/ |
| 885 | UINT8 DdiPort4Hpd; |
| 886 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 887 | /** Offset 0x02B7 - Enable or disable DDC of DDI port A |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 888 | 0(Default)=Disable, 1=Enable |
| 889 | $EN_DIS |
| 890 | **/ |
| 891 | UINT8 DdiPortADdc; |
| 892 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 893 | /** Offset 0x02B8 - Enable or disable DDC of DDI port B |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 894 | 0=Disable, 1(Default)=Enable |
| 895 | $EN_DIS |
| 896 | **/ |
| 897 | UINT8 DdiPortBDdc; |
| 898 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 899 | /** Offset 0x02B9 - Enable or disable DDC of DDI port C |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 900 | 0(Default)=Disable, 1=Enable |
| 901 | $EN_DIS |
| 902 | **/ |
| 903 | UINT8 DdiPortCDdc; |
| 904 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 905 | /** Offset 0x02BA - Enable DDC setting of DDI Port 1 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 906 | 0(Default)=Disable, 1=Enable |
| 907 | $EN_DIS |
| 908 | **/ |
| 909 | UINT8 DdiPort1Ddc; |
| 910 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 911 | /** Offset 0x02BB - Enable DDC setting of DDI Port 2 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 912 | 0(Default)=Disable, 1=Enable |
| 913 | $EN_DIS |
| 914 | **/ |
| 915 | UINT8 DdiPort2Ddc; |
| 916 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 917 | /** Offset 0x02BC - Enable DDC setting of DDI Port 3 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 918 | 0(Default)=Disable, 1=Enable |
| 919 | $EN_DIS |
| 920 | **/ |
| 921 | UINT8 DdiPort3Ddc; |
| 922 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 923 | /** Offset 0x02BD - Enable DDC setting of DDI Port 4 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 924 | 0(Default)=Disable, 1=Enable |
| 925 | $EN_DIS |
| 926 | **/ |
| 927 | UINT8 DdiPort4Ddc; |
| 928 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 929 | /** Offset 0x02BE - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 930 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 931 | UINT8 Reserved16[18]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 932 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 933 | /** Offset 0x02D0 - Per-core HT Disable |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 934 | Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, |
| 935 | 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value |
| 936 | of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have |
| 937 | HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1. |
| 938 | **/ |
| 939 | UINT16 PerCoreHtDisable; |
| 940 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 941 | /** Offset 0x02D2 - Reserved |
Subrata Banik | bf71c72 | 2022-10-17 14:57:41 +0530 | [diff] [blame] | 942 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 943 | UINT8 Reserved17[6]; |
Subrata Banik | bf71c72 | 2022-10-17 14:57:41 +0530 | [diff] [blame] | 944 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 945 | /** Offset 0x02D8 - Thermal Velocity Boost Ratio clipping |
Kulkarni, Srinivas | 6f37788 | 2022-12-09 13:57:39 +0530 | [diff] [blame] | 946 | 0: Disabled, 1(Default): Enabled. This service controls Core frequency reduction |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 947 | caused by high package temperatures for processors that implement the Intel Thermal |
| 948 | Velocity Boost (TVB) feature |
| 949 | $EN_DIS |
| 950 | **/ |
| 951 | UINT8 TvbRatioClipping; |
| 952 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 953 | /** Offset 0x02D9 - Thermal Velocity Boost voltage optimization |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 954 | 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations |
| 955 | for processors that implement the Intel Thermal Velocity Boost (TVB) feature. |
| 956 | $EN_DIS |
| 957 | **/ |
| 958 | UINT8 TvbVoltageOptimization; |
| 959 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 960 | /** Offset 0x02DA - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 961 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 962 | UINT8 Reserved18[45]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 963 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 964 | /** Offset 0x0307 - DMI Max Link Speed |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 965 | Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 |
| 966 | Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed |
| 967 | 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 |
| 968 | **/ |
| 969 | UINT8 DmiMaxLinkSpeed; |
| 970 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 971 | /** Offset 0x0308 - PCH DMI Equalization Phase 2 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 972 | DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): |
| 973 | AUTO - Use the current default method |
| 974 | 0:Disable phase2, 1:Enable phase2, 2:Auto |
| 975 | **/ |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 976 | UINT8 PchDmiGen3EqPh2Enable; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 977 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 978 | /** Offset 0x0309 - PCH DMI Gen3 Equalization Phase3 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 979 | DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, |
| 980 | HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software |
| 981 | Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static |
| 982 | EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just |
| 983 | Phase1), Disabled(0x4): Bypass Equalization Phase 3 |
| 984 | 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 |
| 985 | **/ |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 986 | UINT8 PchDmiGen3EqPh3Method; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 987 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 988 | /** Offset 0x030A - Enable/Disable DMI GEN3 Static EQ Phase1 programming |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 989 | Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static |
| 990 | Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming |
| 991 | $EN_DIS |
| 992 | **/ |
| 993 | UINT8 DmiGen3ProgramStaticEq; |
| 994 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 995 | /** Offset 0x030B - PCH DMI Gen3 Root port preset values per lane |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 996 | Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane |
| 997 | **/ |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 998 | UINT8 PchDmiGen3RootPortPreset[8]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 999 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1000 | /** Offset 0x0313 - PCH DMI Gen3 End port preset values per lane |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1001 | Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1002 | **/ |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 1003 | UINT8 PchDmiGen3EndPointPreset[8]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1004 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1005 | /** Offset 0x031B - PCH DMI Gen3 End port Hint values per lane |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1006 | Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane |
| 1007 | **/ |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 1008 | UINT8 PchDmiGen3EndPointHint[8]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1009 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1010 | /** Offset 0x0323 - DMI ASPM Configuration:{Combo |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1011 | Set ASPM Configuration |
| 1012 | 0:Disabled, 1:L0s, 2:L1, 3:L1L0s |
| 1013 | **/ |
| 1014 | UINT8 DmiAspm; |
| 1015 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1016 | /** Offset 0x0324 - Reserved |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 1017 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1018 | UINT8 Reserved19; |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 1019 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1020 | /** Offset 0x0325 - Enable/Disable DMI GEN3 Hardware Eq |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1021 | Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0): Disable Hardware Eq, Enabled(0x1)(Default): |
| 1022 | Enable EQ Phase1 Static Presets Programming |
| 1023 | $EN_DIS |
| 1024 | **/ |
| 1025 | UINT8 DmiHweq; |
| 1026 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1027 | /** Offset 0x0326 - Enable/Disable DMI GEN3 Phase 23 Bypass |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1028 | DMIGEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): |
| 1029 | Enable Phase 23 Bypass |
| 1030 | $EN_DIS |
| 1031 | **/ |
| 1032 | UINT8 Gen3EqPhase23Bypass; |
| 1033 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1034 | /** Offset 0x0327 - Enable/Disable DMI GEN3 Phase 3 Bypass |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1035 | DMIGEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): |
| 1036 | Enable Phase 3 Bypass |
| 1037 | $EN_DIS |
| 1038 | **/ |
| 1039 | UINT8 Gen3EqPhase3Bypass; |
| 1040 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1041 | /** Offset 0x0328 - Enable/Disable DMI Gen3 EQ Local Transmitter Coefficient Override Enable |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1042 | Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0): Disable Local |
| 1043 | Transmitter Coefficient Override, Enabled(0x1)(Default): Enable Local Transmitter |
| 1044 | Coefficient Override |
| 1045 | $EN_DIS |
| 1046 | **/ |
| 1047 | UINT8 Gen3LtcoEnable; |
| 1048 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1049 | /** Offset 0x0329 - Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1050 | Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): |
| 1051 | Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote |
| 1052 | Transmitter Coefficient/Preset Override |
| 1053 | $EN_DIS |
| 1054 | **/ |
| 1055 | UINT8 Gen3RtcoRtpoEnable; |
| 1056 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1057 | /** Offset 0x032A - DMI Gen3 Transmitter Pre-Cursor Coefficient |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1058 | Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, |
| 1059 | 2 is default for each lane |
| 1060 | **/ |
| 1061 | UINT8 DmiGen3Ltcpre[8]; |
| 1062 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1063 | /** Offset 0x0332 - DMI Gen3 Transmitter Post-Cursor Coefficient |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1064 | Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default |
| 1065 | for each lane |
| 1066 | **/ |
| 1067 | UINT8 DmiGen3Ltcpo[8]; |
| 1068 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1069 | /** Offset 0x033A - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1070 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1071 | UINT8 Reserved20[34]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1072 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1073 | /** Offset 0x035C - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1074 | Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable, |
| 1075 | Manual(0x1): Enable DmiGen3DsPresetEnable |
| 1076 | $EN_DIS |
| 1077 | **/ |
| 1078 | UINT8 DmiGen3DsPresetEnable; |
| 1079 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1080 | /** Offset 0x035D - DMI Gen3 Root port preset Rx values per lane |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1081 | Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default |
| 1082 | for each lane |
| 1083 | **/ |
| 1084 | UINT8 DmiGen3DsPortRxPreset[8]; |
| 1085 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1086 | /** Offset 0x0365 - DMI Gen3 Root port preset Tx values per lane |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1087 | Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default |
| 1088 | for each lane |
| 1089 | **/ |
| 1090 | UINT8 DmiGen3DsPortTxPreset[8]; |
| 1091 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1092 | /** Offset 0x036D - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1093 | Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable, |
| 1094 | Manual(0x1): Enable DmiGen3UsPresetEnable |
| 1095 | $EN_DIS |
| 1096 | **/ |
| 1097 | UINT8 DmiGen3UsPresetEnable; |
| 1098 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1099 | /** Offset 0x036E - DMI Gen3 Root port preset Rx values per lane |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1100 | Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default |
| 1101 | for each lane |
| 1102 | **/ |
| 1103 | UINT8 DmiGen3UsPortRxPreset[8]; |
| 1104 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1105 | /** Offset 0x0376 - DMI Gen3 Root port preset Tx values per lane |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1106 | Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default |
| 1107 | for each lane |
| 1108 | **/ |
| 1109 | UINT8 DmiGen3UsPortTxPreset[8]; |
| 1110 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1111 | /** Offset 0x037E - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1112 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1113 | UINT8 Reserved21[54]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1114 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1115 | /** Offset 0x03B4 - DMI ASPM L1 exit Latency |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1116 | Range: 0-7, 4 is default L1 exit Latency |
| 1117 | **/ |
| 1118 | UINT8 DmiAspmL1ExitLatency; |
| 1119 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1120 | /** Offset 0x03B5 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1121 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1122 | UINT8 Reserved22[63]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1123 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1124 | /** Offset 0x03F4 - BIST on Reset |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1125 | Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable. |
| 1126 | $EN_DIS |
| 1127 | **/ |
| 1128 | UINT8 BistOnReset; |
| 1129 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1130 | /** Offset 0x03F5 - Skip Stop PBET Timer Enable/Disable |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1131 | Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable |
| 1132 | $EN_DIS |
| 1133 | **/ |
| 1134 | UINT8 SkipStopPbet; |
| 1135 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1136 | /** Offset 0x03F6 - Over clocking support |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1137 | Over clocking support; <b>0: Disable</b>; 1: Enable |
| 1138 | $EN_DIS |
| 1139 | **/ |
| 1140 | UINT8 OcSupport; |
| 1141 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1142 | /** Offset 0x03F7 - Over clocking Lock |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1143 | Lock Overclocking. 0: Disable; <b>1: Enable</b> |
| 1144 | $EN_DIS |
| 1145 | **/ |
| 1146 | UINT8 OcLock; |
| 1147 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1148 | /** Offset 0x03F8 - Maximum Core Turbo Ratio Override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1149 | Maximum core turbo ratio override allows to increase CPU core frequency beyond the |
| 1150 | fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 if CoreRatioExtensionMode |
| 1151 | is disabled. 0-120 if CoreRatioExtensionMode is enabled. |
| 1152 | **/ |
| 1153 | UINT8 CoreMaxOcRatio; |
| 1154 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1155 | /** Offset 0x03F9 - Core voltage mode |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1156 | Core voltage mode; <b>0: Adaptive</b>; 1: Override. |
| 1157 | $EN_DIS |
| 1158 | **/ |
| 1159 | UINT8 CoreVoltageMode; |
| 1160 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1161 | /** Offset 0x03FA - Maximum clr turbo ratio override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1162 | Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the |
| 1163 | fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 |
| 1164 | **/ |
| 1165 | UINT8 RingMaxOcRatio; |
| 1166 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1167 | /** Offset 0x03FB - Hyper Threading Enable/Disable |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1168 | Enable or Disable Hyper-Threading Technology. 0: Disable; <b>1: Enable</b> |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1169 | $EN_DIS |
| 1170 | **/ |
| 1171 | UINT8 HyperThreading; |
| 1172 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1173 | /** Offset 0x03FC - Enable or Disable CPU Ratio Override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1174 | Enable/Disable CPU Flex Ratio Programming; <b>0: Disable</b>; 1: Enable. |
| 1175 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1176 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1177 | UINT8 CpuRatioOverride; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1178 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1179 | /** Offset 0x03FD - CPU ratio value |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1180 | This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio |
| 1181 | set by Hardware (HFM). Valid Range 0 to 63. |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1182 | **/ |
| 1183 | UINT8 CpuRatio; |
| 1184 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1185 | /** Offset 0x03FE - Reserved |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1186 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1187 | UINT8 Reserved23; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1188 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1189 | /** Offset 0x03FF - Number of active big cores |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1190 | Number of P-cores to enable in each processor package. Note: Number of P-Cores and |
| 1191 | E-Cores are looked at together. When both are {0,0 |
| 1192 | 0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores |
| 1193 | **/ |
| 1194 | UINT8 ActiveCoreCount; |
| 1195 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1196 | /** Offset 0x0400 - Processor Early Power On Configuration FCLK setting |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1197 | FCLK frequency can take values of 400MHz, 800MHz and 1GHz. <b>0: 800 MHz (ULT/ULX)</b>. |
| 1198 | <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1199 | 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved |
| 1200 | **/ |
| 1201 | UINT8 FClkFrequency; |
| 1202 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1203 | /** Offset 0x0401 - Enable or Disable VMX |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1204 | Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities |
| 1205 | provided by Vanderpool Technology. 0: Disable; <b>1: Enable</b>. |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1206 | $EN_DIS |
| 1207 | **/ |
| 1208 | UINT8 VmxEnable; |
| 1209 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1210 | /** Offset 0x0402 - AVX2 Ratio Offset |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1211 | 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio |
| 1212 | vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1213 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1214 | UINT8 Avx2RatioOffset; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1215 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1216 | /** Offset 0x0403 - AVX3 Ratio Offset |
Subrata Banik | d0de6c2 | 2023-08-30 17:38:50 +0000 | [diff] [blame] | 1217 | DEPRECATED. 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease |
| 1218 | AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1219 | **/ |
| 1220 | UINT8 Avx3RatioOffset; |
| 1221 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1222 | /** Offset 0x0404 - BCLK Adaptive Voltage Enable |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1223 | When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0: |
| 1224 | Disable;<b> 1: Enable |
| 1225 | $EN_DIS |
| 1226 | **/ |
| 1227 | UINT8 BclkAdaptiveVoltage; |
| 1228 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1229 | /** Offset 0x0405 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1230 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1231 | UINT8 Reserved24; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1232 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1233 | /** Offset 0x0406 - core voltage override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1234 | The core voltage override which is applied to the entire range of cpu core frequencies. |
| 1235 | Valid Range 0 to 2000 |
| 1236 | **/ |
| 1237 | UINT16 CoreVoltageOverride; |
| 1238 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1239 | /** Offset 0x0408 - Core Turbo Adaptive Voltage |
| 1240 | Adaptive voltage applied to the cpu core when the cpu is operating in turbo mode. |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1241 | Valid Range 0 to 2000 |
| 1242 | **/ |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1243 | UINT16 CoreAdaptiveVoltage; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1244 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1245 | /** Offset 0x040A - Core Turbo voltage Offset |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1246 | The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 |
| 1247 | **/ |
| 1248 | UINT16 CoreVoltageOffset; |
| 1249 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1250 | /** Offset 0x040C - Core PLL voltage offset |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1251 | Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 |
| 1252 | **/ |
| 1253 | UINT8 CorePllVoltageOffset; |
| 1254 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1255 | /** Offset 0x040D - Ring Downbin |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1256 | Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always |
| 1257 | lower than the core ratio.0: Disable; <b>1: Enable.</b> |
| 1258 | $EN_DIS |
| 1259 | **/ |
| 1260 | UINT8 RingDownBin; |
| 1261 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1262 | /** Offset 0x040E - Ring voltage mode |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1263 | Ring voltage mode; <b>0: Adaptive</b>; 1: Override. |
| 1264 | $EN_DIS |
| 1265 | **/ |
| 1266 | UINT8 RingVoltageMode; |
| 1267 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1268 | /** Offset 0x040F - TjMax Offset |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1269 | TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support |
| 1270 | TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 |
| 1271 | **/ |
| 1272 | UINT8 TjMaxOffset; |
| 1273 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1274 | /** Offset 0x0410 - Ring voltage override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1275 | The ring voltage override which is applied to the entire range of cpu ring frequencies. |
| 1276 | Valid Range 0 to 2000 |
| 1277 | **/ |
| 1278 | UINT16 RingVoltageOverride; |
| 1279 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1280 | /** Offset 0x0412 - Ring Turbo Adaptive Voltage |
| 1281 | Adaptive voltage applied to the cpu ring when the cpu is operating in turbo mode. |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1282 | Valid Range 0 to 2000 |
| 1283 | **/ |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1284 | UINT16 RingAdaptiveVoltage; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1285 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1286 | /** Offset 0x0414 - Ring Turbo voltage Offset |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1287 | The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 |
| 1288 | **/ |
| 1289 | UINT16 RingVoltageOffset; |
| 1290 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1291 | /** Offset 0x0416 - Enable or Disable TME |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1292 | Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks. |
| 1293 | <b>0: Disable</b>; 1: Enable. |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1294 | $EN_DIS |
| 1295 | **/ |
| 1296 | UINT8 TmeEnable; |
| 1297 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1298 | /** Offset 0x0417 - Enable CPU CrashLog |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1299 | Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>. |
| 1300 | $EN_DIS |
| 1301 | **/ |
| 1302 | UINT8 CpuCrashLogEnable; |
| 1303 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1304 | /** Offset 0x0418 - CPU Run Control |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1305 | Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2: |
| 1306 | No Change</b> |
| 1307 | 0:Disabled, 1:Enabled, 2:No Change |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1308 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1309 | UINT8 DebugInterfaceEnable; |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1310 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1311 | /** Offset 0x0419 - CPU Run Control Lock |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1312 | Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>. |
| 1313 | $EN_DIS |
| 1314 | **/ |
| 1315 | UINT8 DebugInterfaceLockEnable; |
| 1316 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1317 | /** Offset 0x041A - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1318 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1319 | UINT8 Reserved25[67]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1320 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1321 | /** Offset 0x045D - Core VF Point Offset Mode |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1322 | Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes. |
| 1323 | In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, |
| 1324 | setting a selected VF point; <b>0: Legacy</b>; 1: Selection. |
| 1325 | 0:Legacy, 1:Selection |
| 1326 | **/ |
| 1327 | UINT8 CoreVfPointOffsetMode; |
| 1328 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1329 | /** Offset 0x045E - Core VF Point Offset |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1330 | Array used to specifies the Core Voltage Offset applied to the each selected VF |
| 1331 | Point. This voltage is specified in millivolts. |
| 1332 | **/ |
| 1333 | UINT16 CoreVfPointOffset[15]; |
| 1334 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1335 | /** Offset 0x047C - Core VF Point Offset Prefix |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1336 | Sets the CoreVfPointOffset value as positive or negative for corresponding core |
| 1337 | VF Point; <b>0: Positive </b>; 1: Negative. |
| 1338 | 0:Positive, 1:Negative |
| 1339 | **/ |
| 1340 | UINT8 CoreVfPointOffsetPrefix[15]; |
| 1341 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1342 | /** Offset 0x048B - Core VF Point Ratio |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1343 | Array for the each selected Core VF Point to display the ration. |
| 1344 | **/ |
| 1345 | UINT8 CoreVfPointRatio[15]; |
| 1346 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1347 | /** Offset 0x049A - Core VF Point Count |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1348 | Number of supported Core Voltage & Frequency Point Offset |
| 1349 | **/ |
| 1350 | UINT8 CoreVfPointCount; |
| 1351 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1352 | /** Offset 0x049B - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1353 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1354 | UINT8 Reserved26[25]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1355 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1356 | /** Offset 0x04B4 - Per Core Max Ratio override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1357 | Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new |
| 1358 | favored core ratio to each Core. <b>0: Disable</b>, 1: enable |
| 1359 | $EN_DIS |
| 1360 | **/ |
| 1361 | UINT8 PerCoreRatioOverride; |
| 1362 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1363 | /** Offset 0x04B5 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1364 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1365 | UINT8 Reserved27[41]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1366 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1367 | /** Offset 0x04DE - Per Core Current Max Ratio |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1368 | Array for the Per Core Max Ratio |
| 1369 | **/ |
| 1370 | UINT8 PerCoreRatio[8]; |
| 1371 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1372 | /** Offset 0x04E6 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1373 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1374 | UINT8 Reserved28[69]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1375 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1376 | /** Offset 0x052B - Pvd Ratio Threshold for SOC/CPU die |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1377 | Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio |
| 1378 | (P0 to Pn) to select the multiplier so that the output is within the DCO frequency |
| 1379 | range. As per the die selected, this threshold is applied to SA and MC/CMI PLL |
| 1380 | for SOC die and SA, Ring and Atom PLL for CPU die. Range 0-63. When the threshold |
| 1381 | is 0, static PVD ratio is selected based on the PVD Mode for SOC. <b>0: Default</b>. |
| 1382 | **/ |
| 1383 | UINT8 PvdRatioThreshold[2]; |
| 1384 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1385 | /** Offset 0x052D - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1386 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1387 | UINT8 Reserved29[68]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1388 | |
Kilari Raasi | b120758 | 2023-03-20 12:19:23 +0530 | [diff] [blame] | 1389 | /** Offset 0x0571 - GPIO Override |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1390 | Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings |
| 1391 | before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO |
Subrata Banik | 6ed4315 | 2022-11-22 16:36:37 +0530 | [diff] [blame] | 1392 | configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for use |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1393 | **/ |
| 1394 | UINT8 GpioOverride; |
| 1395 | |
Kilari Raasi | b120758 | 2023-03-20 12:19:23 +0530 | [diff] [blame] | 1396 | /** Offset 0x0572 - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1397 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1398 | UINT8 Reserved30[10]; |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1399 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1400 | /** Offset 0x057C - CPU BCLK OC Frequency |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1401 | CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is |
| 1402 | 40Mhz-1000Mhz. |
| 1403 | **/ |
| 1404 | UINT32 CpuBclkOcFrequency; |
| 1405 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1406 | /** Offset 0x0580 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1407 | **/ |
Subrata Banik | 04abc86 | 2023-05-22 15:36:46 +0530 | [diff] [blame] | 1408 | UINT8 Reserved31[4]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1409 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1410 | /** Offset 0x0584 - Enable CPU CrashLog GPRs dump |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1411 | Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only |
| 1412 | disable Smm GPRs dump |
| 1413 | 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled |
| 1414 | **/ |
| 1415 | UINT8 CrashLogGprs; |
| 1416 | |
Kilari Raasi | 9f5b2f7 | 2023-03-02 13:48:02 +0530 | [diff] [blame] | 1417 | /** Offset 0x0585 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1418 | **/ |
Kilari Raasi | 01f4f5d | 2023-08-16 16:34:40 +0530 | [diff] [blame] | 1419 | UINT8 Reserved32[145]; |
| 1420 | |
| 1421 | /** Offset 0x0616 - Platform Power Pmax |
| 1422 | PSYS PMax power, defined in 1/8 Watt increments. <b>0 - Auto</b> Specified in 1/8 |
| 1423 | Watt increments. Range 0-1024 Watts(0-8191). Value of 800 = 100W |
| 1424 | **/ |
| 1425 | UINT16 PsysPmax; |
| 1426 | |
| 1427 | /** Offset 0x0618 - Reserved |
| 1428 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1429 | UINT8 Reserved33[12]; |
| 1430 | |
| 1431 | /** Offset 0x0624 - AcLoadline |
| 1432 | AC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 |
| 1433 | mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for |
| 1434 | GT, [2] for SA, [3] through [5] are Reserved. |
| 1435 | **/ |
| 1436 | UINT16 AcLoadline[6]; |
| 1437 | |
| 1438 | /** Offset 0x0630 - DcLoadline |
| 1439 | DC Loadline defined in 1/100 mOhms. A value of 100 = 1.00 mOhm, and 1255 = 12.55 |
| 1440 | mOhm. Range is 0-6249 (0-62.49 mOhms). 0 = AUTO/HW default. [0] for IA, [1] for |
| 1441 | GT, [2] for SA, [3] through [5] are Reserved. |
| 1442 | **/ |
| 1443 | UINT16 DcLoadline[6]; |
| 1444 | |
Jeremy Compostella | e68650a | 2023-10-18 12:39:10 -0700 | [diff] [blame^] | 1445 | /** Offset 0x063C - Power State 1 Threshold current |
| 1446 | PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range |
| 1447 | 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, |
| 1448 | [3] through [5] are Reserved. |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1449 | **/ |
Jeremy Compostella | e68650a | 2023-10-18 12:39:10 -0700 | [diff] [blame^] | 1450 | UINT16 Psi1Threshold[6]; |
| 1451 | |
| 1452 | /** Offset 0x0648 - Power State 2 Threshold current |
| 1453 | PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range |
| 1454 | 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, |
| 1455 | [3] through [5] are Reserved. |
| 1456 | **/ |
| 1457 | UINT16 Psi2Threshold[6]; |
| 1458 | |
| 1459 | /** Offset 0x0654 - Power State 3 Threshold current |
| 1460 | PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range |
| 1461 | 0-512, which translates to 0-128A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, |
| 1462 | [3] through [5] are Reserved. |
| 1463 | **/ |
| 1464 | UINT16 Psi3Threshold[6]; |
| 1465 | |
| 1466 | /** Offset 0x0660 - Reserved |
| 1467 | **/ |
| 1468 | UINT8 Reserved34[54]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1469 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1470 | /** Offset 0x0696 - Thermal Design Current enable/disable |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1471 | Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA, |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1472 | [1] for GT, [2] for SA, [3] through [5] are Reserved. |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1473 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1474 | UINT8 TdcEnable[6]; |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1475 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1476 | /** Offset 0x069C - Thermal Design Current time window |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1477 | TDC Time Window, value of IA either in milliseconds or seconds, value of GT/SA is |
| 1478 | in milliseconds. 1ms is default. Range of IA from 1ms to 448s, Range of GT/SA is |
| 1479 | 1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition. |
| 1480 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1481 | UINT32 TdcTimeWindow[6]; |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1482 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1483 | /** Offset 0x06B4 - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1484 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1485 | UINT8 Reserved35[166]; |
Subrata Banik | b6f45ef | 2023-06-12 16:22:37 +0530 | [diff] [blame] | 1486 | |
| 1487 | /** Offset 0x075A - VR Fast Vmode ICC Limit support |
| 1488 | Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds |
| 1489 | to feature disabled (no reactive protection). This value represents the current |
| 1490 | threshold where the VR would initiate reactive protection if Fast Vmode is enabled. |
| 1491 | The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for |
| 1492 | GT, [2] for SA, [3] through [5] are Reserved. |
| 1493 | **/ |
| 1494 | UINT16 IccLimit[6]; |
| 1495 | |
| 1496 | /** Offset 0x0766 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. |
Dinesh Gehlot | b60cf3d | 2023-08-17 11:04:32 +0530 | [diff] [blame] | 1497 | Enable/Disable VR FastVmode; 0: Disable; <b>1: Enable</b>. For all VR by domain |
Subrata Banik | b6f45ef | 2023-06-12 16:22:37 +0530 | [diff] [blame] | 1498 | 0: Disable, 1: Enable |
| 1499 | **/ |
| 1500 | UINT8 EnableFastVmode[6]; |
| 1501 | |
| 1502 | /** Offset 0x076C - Enable CEP |
Dinesh Gehlot | b60cf3d | 2023-08-17 11:04:32 +0530 | [diff] [blame] | 1503 | Enable/Disable CEP (Current Excursion Protection) Support. 0: Disable; <b>1: Enable</b>. |
| 1504 | [0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved. |
Subrata Banik | b6f45ef | 2023-06-12 16:22:37 +0530 | [diff] [blame] | 1505 | $EN_DIS |
| 1506 | **/ |
| 1507 | UINT8 CepEnable[6]; |
| 1508 | |
| 1509 | /** Offset 0x0772 - Reserved |
| 1510 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1511 | UINT8 Reserved36[146]; |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1512 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1513 | /** Offset 0x0804 - BiosGuard |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1514 | Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable |
| 1515 | $EN_DIS |
| 1516 | **/ |
| 1517 | UINT8 BiosGuard; |
| 1518 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1519 | /** Offset 0x0805 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1520 | **/ |
| 1521 | UINT8 BiosGuardToolsInterface; |
| 1522 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1523 | /** Offset 0x0806 - Txt |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1524 | Enables utilization of additional hardware capabilities provided by Intel (R) Trusted |
| 1525 | Execution Technology. Changes require a full power cycle to take effect. <b>0: |
| 1526 | Disable</b>, 1: Enable |
| 1527 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1528 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1529 | UINT8 Txt; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1530 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1531 | /** Offset 0x0807 - Reserved |
Srinidhi N Kaushik | 15b439e | 2022-07-29 16:06:05 -0700 | [diff] [blame] | 1532 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1533 | UINT8 Reserved37; |
Srinidhi N Kaushik | 15b439e | 2022-07-29 16:06:05 -0700 | [diff] [blame] | 1534 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1535 | /** Offset 0x0808 - PrmrrSize |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1536 | Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable |
| 1537 | **/ |
| 1538 | UINT32 PrmrrSize; |
| 1539 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1540 | /** Offset 0x080C - SinitMemorySize |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1541 | Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable |
| 1542 | **/ |
| 1543 | UINT32 SinitMemorySize; |
| 1544 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1545 | /** Offset 0x0810 - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1546 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1547 | UINT8 Reserved38[8]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1548 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1549 | /** Offset 0x0818 - TxtDprMemoryBase |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1550 | Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable |
| 1551 | **/ |
| 1552 | UINT64 TxtDprMemoryBase; |
| 1553 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1554 | /** Offset 0x0820 - TxtHeapMemorySize |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1555 | Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable |
| 1556 | **/ |
| 1557 | UINT32 TxtHeapMemorySize; |
| 1558 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1559 | /** Offset 0x0824 - TxtDprMemorySize |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1560 | Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize |
| 1561 | , 1: enable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1562 | **/ |
| 1563 | UINT32 TxtDprMemorySize; |
| 1564 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1565 | /** Offset 0x0828 - BiosAcmBase |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1566 | Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1567 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1568 | UINT32 BiosAcmBase; |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 1569 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1570 | /** Offset 0x082C - BiosAcmSize |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1571 | Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable |
| 1572 | **/ |
| 1573 | UINT32 BiosAcmSize; |
| 1574 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1575 | /** Offset 0x0830 - ApStartupBase |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1576 | Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable |
| 1577 | **/ |
| 1578 | UINT32 ApStartupBase; |
| 1579 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1580 | /** Offset 0x0834 - TgaSize |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1581 | Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable |
| 1582 | **/ |
| 1583 | UINT32 TgaSize; |
| 1584 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1585 | /** Offset 0x0838 - TxtLcpPdBase |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1586 | Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable |
| 1587 | **/ |
| 1588 | UINT64 TxtLcpPdBase; |
| 1589 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1590 | /** Offset 0x0840 - TxtLcpPdSize |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1591 | Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable |
| 1592 | **/ |
| 1593 | UINT64 TxtLcpPdSize; |
| 1594 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1595 | /** Offset 0x0848 - IsTPMPresence |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1596 | IsTPMPresence default values |
| 1597 | **/ |
| 1598 | UINT8 IsTPMPresence; |
| 1599 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1600 | /** Offset 0x0849 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1601 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1602 | UINT8 Reserved39[32]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1603 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1604 | /** Offset 0x0869 - Enable PCH HSIO PCIE Rx Set Ctle |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1605 | Enable PCH PCIe Gen 3 Set CTLE Value. |
| 1606 | **/ |
| 1607 | UINT8 PchPcieHsioRxSetCtleEnable[28]; |
| 1608 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1609 | /** Offset 0x0885 - PCH HSIO PCIE Rx Set Ctle Value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1610 | PCH PCIe Gen 3 Set CTLE Value. |
| 1611 | **/ |
| 1612 | UINT8 PchPcieHsioRxSetCtle[28]; |
| 1613 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1614 | /** Offset 0x08A1 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1615 | 0: Disable; 1: Enable. |
| 1616 | **/ |
| 1617 | UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28]; |
| 1618 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1619 | /** Offset 0x08BD - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1620 | PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. |
| 1621 | **/ |
| 1622 | UINT8 PchPcieHsioTxGen1DownscaleAmp[28]; |
| 1623 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1624 | /** Offset 0x08D9 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1625 | 0: Disable; 1: Enable. |
| 1626 | **/ |
| 1627 | UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28]; |
| 1628 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1629 | /** Offset 0x08F5 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1630 | PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. |
| 1631 | **/ |
| 1632 | UINT8 PchPcieHsioTxGen2DownscaleAmp[28]; |
| 1633 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1634 | /** Offset 0x0911 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1635 | 0: Disable; 1: Enable. |
| 1636 | **/ |
| 1637 | UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28]; |
| 1638 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1639 | /** Offset 0x092D - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1640 | PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. |
| 1641 | **/ |
| 1642 | UINT8 PchPcieHsioTxGen3DownscaleAmp[28]; |
| 1643 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1644 | /** Offset 0x0949 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1645 | 0: Disable; 1: Enable. |
| 1646 | **/ |
| 1647 | UINT8 PchPcieHsioTxGen1DeEmphEnable[28]; |
| 1648 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1649 | /** Offset 0x0965 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1650 | PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. |
| 1651 | **/ |
| 1652 | UINT8 PchPcieHsioTxGen1DeEmph[28]; |
| 1653 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1654 | /** Offset 0x0981 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1655 | 0: Disable; 1: Enable. |
| 1656 | **/ |
| 1657 | UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28]; |
| 1658 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1659 | /** Offset 0x099D - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1660 | PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. |
| 1661 | **/ |
| 1662 | UINT8 PchPcieHsioTxGen2DeEmph3p5[28]; |
| 1663 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1664 | /** Offset 0x09B9 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1665 | 0: Disable; 1: Enable. |
| 1666 | **/ |
| 1667 | UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28]; |
| 1668 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1669 | /** Offset 0x09D5 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1670 | PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. |
| 1671 | **/ |
| 1672 | UINT8 PchPcieHsioTxGen2DeEmph6p0[28]; |
| 1673 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1674 | /** Offset 0x09F1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1675 | 0: Disable; 1: Enable. |
| 1676 | **/ |
| 1677 | UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; |
| 1678 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1679 | /** Offset 0x09F9 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1680 | PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. |
| 1681 | **/ |
| 1682 | UINT8 PchSataHsioRxGen1EqBoostMag[8]; |
| 1683 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1684 | /** Offset 0x0A01 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1685 | 0: Disable; 1: Enable. |
| 1686 | **/ |
| 1687 | UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; |
| 1688 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1689 | /** Offset 0x0A09 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1690 | PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. |
| 1691 | **/ |
| 1692 | UINT8 PchSataHsioRxGen2EqBoostMag[8]; |
| 1693 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1694 | /** Offset 0x0A11 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1695 | 0: Disable; 1: Enable. |
| 1696 | **/ |
| 1697 | UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; |
| 1698 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1699 | /** Offset 0x0A19 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1700 | PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. |
| 1701 | **/ |
| 1702 | UINT8 PchSataHsioRxGen3EqBoostMag[8]; |
| 1703 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1704 | /** Offset 0x0A21 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1705 | 0: Disable; 1: Enable. |
| 1706 | **/ |
| 1707 | UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; |
| 1708 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1709 | /** Offset 0x0A29 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1710 | PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. |
| 1711 | **/ |
| 1712 | UINT8 PchSataHsioTxGen1DownscaleAmp[8]; |
| 1713 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1714 | /** Offset 0x0A31 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1715 | 0: Disable; 1: Enable. |
| 1716 | **/ |
| 1717 | UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; |
| 1718 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1719 | /** Offset 0x0A39 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1720 | PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. |
| 1721 | **/ |
| 1722 | UINT8 PchSataHsioTxGen2DownscaleAmp[8]; |
| 1723 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1724 | /** Offset 0x0A41 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1725 | 0: Disable; 1: Enable. |
| 1726 | **/ |
| 1727 | UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; |
| 1728 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1729 | /** Offset 0x0A49 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1730 | PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. |
| 1731 | **/ |
| 1732 | UINT8 PchSataHsioTxGen3DownscaleAmp[8]; |
| 1733 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1734 | /** Offset 0x0A51 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1735 | 0: Disable; 1: Enable. |
| 1736 | **/ |
| 1737 | UINT8 PchSataHsioTxGen1DeEmphEnable[8]; |
| 1738 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1739 | /** Offset 0x0A59 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1740 | PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. |
| 1741 | **/ |
| 1742 | UINT8 PchSataHsioTxGen1DeEmph[8]; |
| 1743 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1744 | /** Offset 0x0A61 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1745 | 0: Disable; 1: Enable. |
| 1746 | **/ |
| 1747 | UINT8 PchSataHsioTxGen2DeEmphEnable[8]; |
| 1748 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1749 | /** Offset 0x0A69 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1750 | PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. |
| 1751 | **/ |
| 1752 | UINT8 PchSataHsioTxGen2DeEmph[8]; |
| 1753 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1754 | /** Offset 0x0A71 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1755 | 0: Disable; 1: Enable. |
| 1756 | **/ |
| 1757 | UINT8 PchSataHsioTxGen3DeEmphEnable[8]; |
| 1758 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1759 | /** Offset 0x0A79 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1760 | PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. |
| 1761 | **/ |
| 1762 | UINT8 PchSataHsioTxGen3DeEmph[8]; |
| 1763 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1764 | /** Offset 0x0A81 - PCH LPC Enhance the port 8xh decoding |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1765 | Original LPC only decodes one byte of port 80h. |
| 1766 | $EN_DIS |
| 1767 | **/ |
| 1768 | UINT8 PchLpcEnhancePort8xhDecoding; |
| 1769 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1770 | /** Offset 0x0A82 - PCH Port80 Route |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1771 | Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. |
| 1772 | $EN_DIS |
| 1773 | **/ |
| 1774 | UINT8 PchPort80Route; |
| 1775 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1776 | /** Offset 0x0A83 - Enable SMBus ARP support |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1777 | Enable SMBus ARP support. |
| 1778 | $EN_DIS |
| 1779 | **/ |
| 1780 | UINT8 SmbusArpEnable; |
| 1781 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1782 | /** Offset 0x0A84 - Number of RsvdSmbusAddressTable. |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1783 | The number of elements in the RsvdSmbusAddressTable. |
| 1784 | **/ |
| 1785 | UINT8 PchNumRsvdSmbusAddresses; |
| 1786 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1787 | /** Offset 0x0A85 - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1788 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1789 | UINT8 Reserved40; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1790 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1791 | /** Offset 0x0A86 - SMBUS Base Address |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1792 | SMBUS Base Address (IO space). |
| 1793 | **/ |
| 1794 | UINT16 PchSmbusIoBase; |
| 1795 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1796 | /** Offset 0x0A88 - Enable SMBus Alert Pin |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1797 | Enable SMBus Alert Pin. |
| 1798 | $EN_DIS |
| 1799 | **/ |
| 1800 | UINT8 PchSmbAlertEnable; |
| 1801 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1802 | /** Offset 0x0A89 - Usage type for SOC/IOE ClkSrc |
| 1803 | 0-23: PCIe rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1804 | **/ |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1805 | UINT8 PcieClkSrcUsage[16]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1806 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1807 | /** Offset 0x0A99 - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1808 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1809 | UINT8 Reserved41[16]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1810 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1811 | /** Offset 0x0AA9 - SOC/IOE ClkReq-to-ClkSrc mapping |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1812 | Number of ClkReq signal assigned to ClkSrc |
| 1813 | **/ |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1814 | UINT8 PcieClkSrcClkReq[16]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1815 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1816 | /** Offset 0x0AB9 - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1817 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1818 | UINT8 Reserved42[55]; |
Kilari Raasi | 6a7703f | 2023-05-30 12:36:36 +0530 | [diff] [blame] | 1819 | |
| 1820 | /** Offset 0x0AF0 - Enable PCH PCIE RP Mask |
| 1821 | Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, |
| 1822 | bit0 for port1, bit1 for port2, and so on. |
| 1823 | **/ |
| 1824 | UINT32 PchPcieRpEnableMask; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1825 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1826 | /** Offset 0x0AF4 - Enable SOC/IOE PCIE RP Mask |
Subrata Banik | 6ed4315 | 2022-11-22 16:36:37 +0530 | [diff] [blame] | 1827 | Enable/disable SOC/IOE PCIE Root Ports. 0: disable, 1: enable. One bit for each |
| 1828 | port, bit0 for port1, bit1 for port2, and so on. |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1829 | **/ |
Subrata Banik | 6ed4315 | 2022-11-22 16:36:37 +0530 | [diff] [blame] | 1830 | UINT16 PcieRpEnableMask; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1831 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1832 | /** Offset 0x0AF6 - VC Type |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1833 | Virtual Channel Type Select: 0: VC0, 1: VC1. |
| 1834 | 0: VC0, 1: VC1 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1835 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1836 | UINT8 PchHdaVcType; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1837 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1838 | /** Offset 0x0AF7 - Universal Audio Architecture compliance for DSP enabled system |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1839 | 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox |
| 1840 | driver or SST driver supported). |
| 1841 | $EN_DIS |
| 1842 | **/ |
| 1843 | UINT8 PchHdaDspUaaCompliance; |
| 1844 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1845 | /** Offset 0x0AF8 - Enable HD Audio Link |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1846 | Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. |
| 1847 | $EN_DIS |
| 1848 | **/ |
| 1849 | UINT8 PchHdaAudioLinkHdaEnable; |
| 1850 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1851 | /** Offset 0x0AF9 - Enable HDA SDI lanes |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1852 | Enable/disable HDA SDI lanes. |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1853 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1854 | UINT8 PchHdaSdiEnable[2]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1855 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1856 | /** Offset 0x0AFB - HDA Power/Clock Gating (PGD/CGD) |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1857 | Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: |
| 1858 | FORCE_ENABLE, 2: FORCE_DISABLE. |
| 1859 | 0: POR, 1: Force Enable, 2: Force Disable |
| 1860 | **/ |
| 1861 | UINT8 PchHdaTestPowerClockGating; |
| 1862 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1863 | /** Offset 0x0AFC - Enable HD Audio DMIC_N Link |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1864 | Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. |
| 1865 | **/ |
| 1866 | UINT8 PchHdaAudioLinkDmicEnable[2]; |
| 1867 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1868 | /** Offset 0x0AFE - Reserved |
Subrata Banik | 6ed4315 | 2022-11-22 16:36:37 +0530 | [diff] [blame] | 1869 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1870 | UINT8 Reserved43[2]; |
Subrata Banik | 6ed4315 | 2022-11-22 16:36:37 +0530 | [diff] [blame] | 1871 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1872 | /** Offset 0x0B00 - DMIC<N> ClkA Pin Muxing (N - DMIC number) |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1873 | Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* |
| 1874 | **/ |
| 1875 | UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; |
| 1876 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1877 | /** Offset 0x0B08 - DMIC<N> ClkB Pin Muxing |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1878 | Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* |
| 1879 | **/ |
| 1880 | UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; |
| 1881 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1882 | /** Offset 0x0B10 - Enable HD Audio DSP |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1883 | Enable/disable HD Audio DSP feature. |
| 1884 | $EN_DIS |
| 1885 | **/ |
| 1886 | UINT8 PchHdaDspEnable; |
| 1887 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1888 | /** Offset 0x0B11 - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1889 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1890 | UINT8 Reserved44[3]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1891 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1892 | /** Offset 0x0B14 - DMIC<N> Data Pin Muxing |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1893 | Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* |
| 1894 | **/ |
| 1895 | UINT32 PchHdaAudioLinkDmicDataPinMux[2]; |
| 1896 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1897 | /** Offset 0x0B1C - Enable HD Audio SSP0 Link |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1898 | Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 |
| 1899 | **/ |
| 1900 | UINT8 PchHdaAudioLinkSspEnable[6]; |
| 1901 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1902 | /** Offset 0x0B22 - Enable HD Audio SoundWire#N Link |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1903 | Enable/disable HD Audio SNDW#N link. Muxed with HDA. |
| 1904 | **/ |
| 1905 | UINT8 PchHdaAudioLinkSndwEnable[4]; |
| 1906 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1907 | /** Offset 0x0B26 - iDisp-Link Frequency |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1908 | iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. |
| 1909 | 4: 96MHz, 3: 48MHz |
| 1910 | **/ |
| 1911 | UINT8 PchHdaIDispLinkFrequency; |
| 1912 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1913 | /** Offset 0x0B27 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1914 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1915 | UINT8 Reserved45; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1916 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1917 | /** Offset 0x0B28 - iDisp-Link T-mode |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1918 | iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T |
| 1919 | 0: 2T, 2: 4T, 3: 8T, 4: 16T |
| 1920 | **/ |
| 1921 | UINT8 PchHdaIDispLinkTmode; |
| 1922 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1923 | /** Offset 0x0B29 - iDisplay Audio Codec disconnection |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1924 | 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. |
| 1925 | $EN_DIS |
| 1926 | **/ |
| 1927 | UINT8 PchHdaIDispCodecDisconnect; |
| 1928 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1929 | /** Offset 0x0B2A - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1930 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1931 | UINT8 Reserved46[6]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1932 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1933 | /** Offset 0x0B30 - CNVi DDR RFI Mitigation |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1934 | Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE |
| 1935 | $EN_DIS |
| 1936 | **/ |
| 1937 | UINT8 CnviDdrRfim; |
| 1938 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1939 | /** Offset 0x0B31 - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1940 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1941 | UINT8 Reserved47[11]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1942 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1943 | /** Offset 0x0B3C - Debug Interfaces |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1944 | Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, |
| 1945 | BIT2 - Not used. |
| 1946 | **/ |
| 1947 | UINT8 PcdDebugInterfaceFlags; |
| 1948 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1949 | /** Offset 0x0B3D - Serial Io Uart Debug Controller Number |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1950 | Select SerialIo Uart Controller for debug. |
| 1951 | 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 |
| 1952 | **/ |
| 1953 | UINT8 SerialIoUartDebugControllerNumber; |
| 1954 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1955 | /** Offset 0x0B3E - Serial Io Uart Debug Auto Flow |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1956 | Enables UART hardware flow control, CTS and RTS lines. |
| 1957 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1958 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1959 | UINT8 SerialIoUartDebugAutoFlow; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 1960 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1961 | /** Offset 0x0B3F - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1962 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1963 | UINT8 Reserved48; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1964 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1965 | /** Offset 0x0B40 - Serial Io Uart Debug BaudRate |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1966 | Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, |
| 1967 | 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 |
| 1968 | **/ |
| 1969 | UINT32 SerialIoUartDebugBaudRate; |
| 1970 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1971 | /** Offset 0x0B44 - Serial Io Uart Debug Parity |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1972 | Set default Parity. |
| 1973 | 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity |
| 1974 | **/ |
| 1975 | UINT8 SerialIoUartDebugParity; |
| 1976 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1977 | /** Offset 0x0B45 - Serial Io Uart Debug Stop Bits |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1978 | Set default stop bits. |
| 1979 | 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits |
| 1980 | **/ |
| 1981 | UINT8 SerialIoUartDebugStopBits; |
| 1982 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1983 | /** Offset 0x0B46 - Serial Io Uart Debug Data Bits |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1984 | Set default word length. 0: Default, 5,6,7,8 |
| 1985 | 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS |
| 1986 | **/ |
| 1987 | UINT8 SerialIoUartDebugDataBits; |
| 1988 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1989 | /** Offset 0x0B47 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1990 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 1991 | UINT8 Reserved49; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1992 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1993 | /** Offset 0x0B48 - Serial Io Uart Debug Mmio Base |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 1994 | Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode |
| 1995 | = SerialIoUartPci. |
| 1996 | **/ |
| 1997 | UINT32 SerialIoUartDebugMmioBase; |
| 1998 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 1999 | /** Offset 0x0B4C - ISA Serial Base selection |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2000 | Select ISA Serial Base address. Default is 0x3F8. |
| 2001 | 0:0x3F8, 1:0x2F8 |
| 2002 | **/ |
| 2003 | UINT8 PcdIsaSerialUartBase; |
| 2004 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2005 | /** Offset 0x0B4D - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2006 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2007 | UINT8 Reserved50; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2008 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2009 | /** Offset 0x0B4E - Ring PLL voltage offset |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2010 | Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 |
| 2011 | **/ |
| 2012 | UINT8 RingPllVoltageOffset; |
| 2013 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2014 | /** Offset 0x0B4F - System Agent PLL voltage offset |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2015 | Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 |
| 2016 | **/ |
| 2017 | UINT8 SaPllVoltageOffset; |
| 2018 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2019 | /** Offset 0x0B50 - Reserved |
Srinidhi N Kaushik | 3083f35 | 2022-09-07 14:15:54 -0700 | [diff] [blame] | 2020 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2021 | UINT8 Reserved51; |
Srinidhi N Kaushik | 3083f35 | 2022-09-07 14:15:54 -0700 | [diff] [blame] | 2022 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2023 | /** Offset 0x0B51 - Memory Controller PLL voltage offset |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2024 | Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 |
| 2025 | **/ |
| 2026 | UINT8 McPllVoltageOffset; |
| 2027 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2028 | /** Offset 0x0B52 - TCSS Thunderbolt PCIE Root Port 0 Enable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2029 | Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled |
| 2030 | $EN_DIS |
| 2031 | **/ |
| 2032 | UINT8 TcssItbtPcie0En; |
| 2033 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2034 | /** Offset 0x0B53 - TCSS Thunderbolt PCIE Root Port 1 Enable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2035 | Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled |
| 2036 | $EN_DIS |
| 2037 | **/ |
| 2038 | UINT8 TcssItbtPcie1En; |
| 2039 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2040 | /** Offset 0x0B54 - TCSS Thunderbolt PCIE Root Port 2 Enable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2041 | Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled |
| 2042 | $EN_DIS |
| 2043 | **/ |
| 2044 | UINT8 TcssItbtPcie2En; |
| 2045 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2046 | /** Offset 0x0B55 - TCSS Thunderbolt PCIE Root Port 3 Enable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2047 | Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled |
| 2048 | $EN_DIS |
| 2049 | **/ |
| 2050 | UINT8 TcssItbtPcie3En; |
| 2051 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2052 | /** Offset 0x0B56 - TCSS USB HOST (xHCI) Enable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2053 | Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below |
| 2054 | $EN_DIS |
| 2055 | **/ |
| 2056 | UINT8 TcssXhciEn; |
| 2057 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2058 | /** Offset 0x0B57 - TCSS USB DEVICE (xDCI) Enable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2059 | Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled |
| 2060 | $EN_DIS |
| 2061 | **/ |
| 2062 | UINT8 TcssXdciEn; |
| 2063 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2064 | /** Offset 0x0B58 - TCSS DMA0 Enable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2065 | Set TCSS DMA0. 0:Disabled 1:Enabled |
| 2066 | $EN_DIS |
| 2067 | **/ |
| 2068 | UINT8 TcssDma0En; |
| 2069 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2070 | /** Offset 0x0B59 - TCSS DMA1 Enable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2071 | Set TCSS DMA1. 0:Disabled 1:Enabled |
| 2072 | $EN_DIS |
| 2073 | **/ |
| 2074 | UINT8 TcssDma1En; |
| 2075 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2076 | /** Offset 0x0B5A - PcdSerialDebugBaudRate |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2077 | Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. |
| 2078 | 3:9600, 4:19200, 6:56700, 7:115200 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2079 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2080 | UINT8 PcdSerialDebugBaudRate; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2081 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2082 | /** Offset 0x0B5B - HobBufferSize |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2083 | Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB |
| 2084 | total HOB size). |
| 2085 | 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value |
| 2086 | **/ |
| 2087 | UINT8 HobBufferSize; |
| 2088 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2089 | /** Offset 0x0B5C - Early Command Training |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2090 | Enables/Disable Early Command Training |
| 2091 | $EN_DIS |
| 2092 | **/ |
| 2093 | UINT8 ECT; |
| 2094 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2095 | /** Offset 0x0B5D - SenseAmp Offset Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2096 | Enables/Disable SenseAmp Offset Training |
| 2097 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2098 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2099 | UINT8 SOT; |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 2100 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2101 | /** Offset 0x0B5E - Early ReadMPR Timing Centering 2D |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2102 | Enables/Disable Early ReadMPR Timing Centering 2D |
| 2103 | $EN_DIS |
| 2104 | **/ |
| 2105 | UINT8 ERDMPRTC2D; |
| 2106 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2107 | /** Offset 0x0B5F - Read MPR Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2108 | Enables/Disable Read MPR Training |
| 2109 | $EN_DIS |
| 2110 | **/ |
| 2111 | UINT8 RDMPRT; |
| 2112 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2113 | /** Offset 0x0B60 - Receive Enable Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2114 | Enables/Disable Receive Enable Training |
| 2115 | $EN_DIS |
| 2116 | **/ |
| 2117 | UINT8 RCVET; |
| 2118 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2119 | /** Offset 0x0B61 - Jedec Write Leveling |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2120 | Enables/Disable Jedec Write Leveling |
| 2121 | $EN_DIS |
| 2122 | **/ |
| 2123 | UINT8 JWRL; |
| 2124 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2125 | /** Offset 0x0B62 - Early Write Time Centering 2D |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2126 | Enables/Disable Early Write Time Centering 2D |
| 2127 | $EN_DIS |
| 2128 | **/ |
| 2129 | UINT8 EWRTC2D; |
| 2130 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2131 | /** Offset 0x0B63 - Early Read Time Centering 2D |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2132 | Enables/Disable Early Read Time Centering 2D |
| 2133 | $EN_DIS |
| 2134 | **/ |
| 2135 | UINT8 ERDTC2D; |
| 2136 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2137 | /** Offset 0x0B64 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2138 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2139 | UINT8 Reserved52; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2140 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2141 | /** Offset 0x0B65 - Write Timing Centering 1D |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2142 | Enables/Disable Write Timing Centering 1D |
| 2143 | $EN_DIS |
| 2144 | **/ |
| 2145 | UINT8 WRTC1D; |
| 2146 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2147 | /** Offset 0x0B66 - Write Voltage Centering 1D |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2148 | Enables/Disable Write Voltage Centering 1D |
| 2149 | $EN_DIS |
| 2150 | **/ |
| 2151 | UINT8 WRVC1D; |
| 2152 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2153 | /** Offset 0x0B67 - Read Timing Centering 1D |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2154 | Enables/Disable Read Timing Centering 1D |
| 2155 | $EN_DIS |
| 2156 | **/ |
| 2157 | UINT8 RDTC1D; |
| 2158 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2159 | /** Offset 0x0B68 - Read Voltage Centering 1D |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2160 | Enable/Disable Read Voltage Centering 1D |
| 2161 | $EN_DIS |
| 2162 | **/ |
| 2163 | UINT8 RDVC1D; |
| 2164 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2165 | /** Offset 0x0B69 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2166 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2167 | UINT8 Reserved53[10]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2168 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2169 | /** Offset 0x0B73 - Read Equalization Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2170 | Enables/Disable Read Equalization Training |
| 2171 | $EN_DIS |
| 2172 | **/ |
| 2173 | UINT8 RDEQT; |
| 2174 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2175 | /** Offset 0x0B74 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2176 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2177 | UINT8 Reserved54[2]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2178 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2179 | /** Offset 0x0B76 - Write Timing Centering 2D |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2180 | Enables/Disable Write Timing Centering 2D |
| 2181 | $EN_DIS |
| 2182 | **/ |
| 2183 | UINT8 WRTC2D; |
| 2184 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2185 | /** Offset 0x0B77 - Read Timing Centering 2D |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2186 | Enables/Disable Read Timing Centering 2D |
| 2187 | $EN_DIS |
| 2188 | **/ |
| 2189 | UINT8 RDTC2D; |
| 2190 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2191 | /** Offset 0x0B78 - Write Voltage Centering 2D |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2192 | Enables/Disable Write Voltage Centering 2D |
| 2193 | $EN_DIS |
| 2194 | **/ |
| 2195 | UINT8 WRVC2D; |
| 2196 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2197 | /** Offset 0x0B79 - Read Voltage Centering 2D |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2198 | Enables/Disable Read Voltage Centering 2D |
| 2199 | $EN_DIS |
| 2200 | **/ |
| 2201 | UINT8 RDVC2D; |
| 2202 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2203 | /** Offset 0x0B7A - Reserved |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 2204 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2205 | UINT8 Reserved55; |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 2206 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2207 | /** Offset 0x0B7B - Command Voltage Centering |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2208 | Enables/Disable Command Voltage Centering |
| 2209 | $EN_DIS |
| 2210 | **/ |
| 2211 | UINT8 CMDVC; |
| 2212 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2213 | /** Offset 0x0B7C - Late Command Training |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2214 | Enables/Disable Late Command Training |
| 2215 | $EN_DIS |
| 2216 | **/ |
| 2217 | UINT8 LCT; |
| 2218 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2219 | /** Offset 0x0B7D - Turn Around Timing Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2220 | Enables/Disable Turn Around Timing Training |
| 2221 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2222 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2223 | UINT8 TAT; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2224 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2225 | /** Offset 0x0B7E - Rank Margin Tool |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2226 | Enable/disable Rank Margin Tool |
| 2227 | $EN_DIS |
| 2228 | **/ |
| 2229 | UINT8 RMT; |
| 2230 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2231 | /** Offset 0x0B7F - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2232 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2233 | UINT8 Reserved56; |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 2234 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2235 | /** Offset 0x0B80 - DIMM SPD Alias Test |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2236 | Enables/Disable DIMM SPD Alias Test |
| 2237 | $EN_DIS |
| 2238 | **/ |
| 2239 | UINT8 ALIASCHK; |
| 2240 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2241 | /** Offset 0x0B81 - Retrain Margin Check |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2242 | Enables/Disable Retrain Margin Check |
| 2243 | $EN_DIS |
| 2244 | **/ |
| 2245 | UINT8 RMC; |
| 2246 | |
Kilari Raasi | 9c28ab1 | 2023-06-19 16:26:21 +0530 | [diff] [blame] | 2247 | /** Offset 0x0B82 - Row Hammering Prevention |
| 2248 | Enables/Disable Row Hammering Prevention |
| 2249 | $EN_DIS |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2250 | **/ |
Kilari Raasi | 9c28ab1 | 2023-06-19 16:26:21 +0530 | [diff] [blame] | 2251 | UINT8 ROWHAMMER; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2252 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2253 | /** Offset 0x0B83 - Dimm ODT Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2254 | Enables/Disable Dimm ODT Training |
| 2255 | $EN_DIS |
| 2256 | **/ |
| 2257 | UINT8 DIMMODTT; |
| 2258 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2259 | /** Offset 0x0B84 - DIMM RON Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2260 | Enables/Disable DIMM RON Training |
| 2261 | $EN_DIS |
| 2262 | **/ |
| 2263 | UINT8 DIMMRONT; |
| 2264 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2265 | /** Offset 0x0B85 - TxDqTCO Comp Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2266 | Enable/Disable TxDqTCO Comp Training |
| 2267 | $EN_DIS |
| 2268 | **/ |
| 2269 | UINT8 TXTCO; |
| 2270 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2271 | /** Offset 0x0B86 - ClkTCO Comp Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2272 | Enable/Disable ClkTCO Comp Training |
| 2273 | $EN_DIS |
| 2274 | **/ |
| 2275 | UINT8 CLKTCO; |
| 2276 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2277 | /** Offset 0x0B87 - CMD Slew Rate Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2278 | Enable/Disable CMD Slew Rate Training |
| 2279 | $EN_DIS |
| 2280 | **/ |
| 2281 | UINT8 CMDSR; |
| 2282 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2283 | /** Offset 0x0B88 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2284 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2285 | UINT8 Reserved57[2]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2286 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2287 | /** Offset 0x0B8A - DIMM CA ODT Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2288 | Enable/Disable DIMM CA ODT Training |
| 2289 | $EN_DIS |
| 2290 | **/ |
| 2291 | UINT8 DIMMODTCA; |
| 2292 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2293 | /** Offset 0x0B8B - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2294 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2295 | UINT8 Reserved58[3]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2296 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2297 | /** Offset 0x0B8E - Read Vref Decap Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2298 | Enable/Disable Read Vref Decap Training |
| 2299 | $EN_DIS |
| 2300 | **/ |
| 2301 | UINT8 RDVREFDC; |
| 2302 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2303 | /** Offset 0x0B8F - Vddq Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2304 | Enable/Disable Vddq Training |
| 2305 | $EN_DIS |
| 2306 | **/ |
| 2307 | UINT8 VDDQT; |
| 2308 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2309 | /** Offset 0x0B90 - Rank Margin Tool Per Bit |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2310 | Enable/Disable Rank Margin Tool Per Bit |
| 2311 | $EN_DIS |
| 2312 | **/ |
| 2313 | UINT8 RMTBIT; |
| 2314 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2315 | /** Offset 0x0B91 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2316 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2317 | UINT8 Reserved59[4]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2318 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2319 | /** Offset 0x0B95 - Duty Cycle Correction Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2320 | Enable/Disable Duty Cycle Correction Training |
| 2321 | $EN_DIS |
| 2322 | **/ |
| 2323 | UINT8 DCC; |
| 2324 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2325 | /** Offset 0x0B96 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2326 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2327 | UINT8 Reserved60[17]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2328 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2329 | /** Offset 0x0BA7 - ECC Support |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2330 | Enables/Disable ECC Support |
| 2331 | $EN_DIS |
| 2332 | **/ |
| 2333 | UINT8 EccSupport; |
| 2334 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2335 | /** Offset 0x0BA8 - Ibecc |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2336 | In-Band ECC Support |
| 2337 | $EN_DIS |
| 2338 | **/ |
| 2339 | UINT8 Ibecc; |
| 2340 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2341 | /** Offset 0x0BA9 - IbeccParity |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2342 | In-Band ECC Parity Control |
| 2343 | $EN_DIS |
| 2344 | **/ |
| 2345 | UINT8 IbeccParity; |
| 2346 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2347 | /** Offset 0x0BAA - IbeccOperationMode |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2348 | In-Band ECC Operation Mode |
| 2349 | 0:Protect base on address range, 1: Non-protected, 2: All protected |
| 2350 | **/ |
| 2351 | UINT8 IbeccOperationMode; |
| 2352 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2353 | /** Offset 0x0BAB - IbeccProtectedRegionEnable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2354 | In-Band ECC Protected Region Enable |
| 2355 | $EN_DIS |
| 2356 | **/ |
| 2357 | UINT8 IbeccProtectedRegionEnable[8]; |
| 2358 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2359 | /** Offset 0x0BB3 - Reserved |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 2360 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2361 | UINT8 Reserved61; |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 2362 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2363 | /** Offset 0x0BB4 - IbeccProtectedRegionBases |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2364 | IBECC Protected Region Bases per IBECC instance |
| 2365 | **/ |
| 2366 | UINT16 IbeccProtectedRegionBase[8]; |
| 2367 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2368 | /** Offset 0x0BC4 - IbeccProtectedRegionMasks |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2369 | IBECC Protected Region Masks |
| 2370 | **/ |
| 2371 | UINT16 IbeccProtectedRegionMask[8]; |
| 2372 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2373 | /** Offset 0x0BD4 - IbeccProtectedRegionOverallBases |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2374 | IBECC Protected Region Bases based on enabled IBECC instance |
| 2375 | **/ |
| 2376 | UINT16 IbeccProtectedRegionOverallBase[8]; |
| 2377 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2378 | /** Offset 0x0BE4 - Memory Remap |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2379 | Enables/Disable Memory Remap |
| 2380 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2381 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2382 | UINT8 RemapEnable; |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 2383 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2384 | /** Offset 0x0BE5 - Rank Interleave support |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2385 | Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at |
| 2386 | the same time. |
| 2387 | $EN_DIS |
| 2388 | **/ |
| 2389 | UINT8 RankInterleave; |
| 2390 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2391 | /** Offset 0x0BE6 - Enhanced Interleave support |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2392 | Enables/Disable Enhanced Interleave support |
| 2393 | $EN_DIS |
| 2394 | **/ |
| 2395 | UINT8 EnhancedInterleave; |
| 2396 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2397 | /** Offset 0x0BE7 - Ch Hash Support |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2398 | Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode |
| 2399 | $EN_DIS |
| 2400 | **/ |
| 2401 | UINT8 ChHashEnable; |
| 2402 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2403 | /** Offset 0x0BE8 - Extern Therm Status |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2404 | Enables/Disable Extern Therm Status |
| 2405 | $EN_DIS |
| 2406 | **/ |
| 2407 | UINT8 EnableExtts; |
| 2408 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2409 | /** Offset 0x0BE9 - DDR PowerDown and idle counter |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2410 | Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) |
| 2411 | $EN_DIS |
| 2412 | **/ |
| 2413 | UINT8 EnablePwrDn; |
| 2414 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2415 | /** Offset 0x0BEA - DDR PowerDown and idle counter |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2416 | Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) |
| 2417 | $EN_DIS |
| 2418 | **/ |
| 2419 | UINT8 EnablePwrDnLpddr; |
| 2420 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2421 | /** Offset 0x0BEB - SelfRefresh Enable |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2422 | Enables/Disable SelfRefresh Enable |
| 2423 | $EN_DIS |
| 2424 | **/ |
| 2425 | UINT8 SrefCfgEna; |
| 2426 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2427 | /** Offset 0x0BEC - Throttler CKEMin Defeature |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2428 | Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) |
| 2429 | $EN_DIS |
| 2430 | **/ |
| 2431 | UINT8 ThrtCkeMinDefeatLpddr; |
| 2432 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2433 | /** Offset 0x0BED - Throttler CKEMin Defeature |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2434 | Enables/Disable Throttler CKEMin Defeature |
| 2435 | $EN_DIS |
| 2436 | **/ |
| 2437 | UINT8 ThrtCkeMinDefeat; |
| 2438 | |
Kilari Raasi | 9c28ab1 | 2023-06-19 16:26:21 +0530 | [diff] [blame] | 2439 | /** Offset 0x0BEE - Row Hammer Select |
| 2440 | Row Hammer Select |
| 2441 | 0:Disable, 1:RFM, 2:pTRR |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2442 | **/ |
Kilari Raasi | 9c28ab1 | 2023-06-19 16:26:21 +0530 | [diff] [blame] | 2443 | UINT8 RhSelect; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2444 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2445 | /** Offset 0x0BEF - Exit On Failure (MRC) |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2446 | Enables/Disable Exit On Failure (MRC) |
| 2447 | $EN_DIS |
| 2448 | **/ |
| 2449 | UINT8 ExitOnFailure; |
| 2450 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2451 | /** Offset 0x0BF0 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2452 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2453 | UINT8 Reserved62[4]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2454 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2455 | /** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2456 | ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP |
| 2457 | $EN_DIS |
| 2458 | **/ |
| 2459 | UINT8 Ddr4DdpSharedZq; |
| 2460 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2461 | /** Offset 0x0BF5 - Ch Hash Interleaved Bit |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2462 | Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave |
| 2463 | the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 |
| 2464 | 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 |
| 2465 | **/ |
| 2466 | UINT8 ChHashInterleaveBit; |
| 2467 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2468 | /** Offset 0x0BF6 - Ch Hash Mask |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2469 | Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to |
| 2470 | BITS [19:6] Default is 0x30CC |
| 2471 | **/ |
| 2472 | UINT16 ChHashMask; |
| 2473 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2474 | /** Offset 0x0BF8 - Base reference clock value |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2475 | Base reference clock value, in Hertz(Default is 125Hz) |
| 2476 | 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz |
| 2477 | **/ |
| 2478 | UINT32 BClkFrequency; |
| 2479 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2480 | /** Offset 0x0BFC - EPG DIMM Idd3N |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2481 | Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on |
| 2482 | a per DIMM basis. Default is 26 |
| 2483 | **/ |
| 2484 | UINT16 Idd3n; |
| 2485 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2486 | /** Offset 0x0BFE - EPG DIMM Idd3P |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2487 | Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated |
| 2488 | on a per DIMM basis. Default is 11 |
| 2489 | **/ |
| 2490 | UINT16 Idd3p; |
| 2491 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2492 | /** Offset 0x0C00 - CMD Normalization |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2493 | Enable/Disable CMD Normalization |
| 2494 | $EN_DIS |
| 2495 | **/ |
| 2496 | UINT8 CMDNORM; |
| 2497 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2498 | /** Offset 0x0C01 - Early DQ Write Drive Strength and Equalization Training |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2499 | Enable/Disable Early DQ Write Drive Strength and Equalization Training |
| 2500 | $EN_DIS |
| 2501 | **/ |
| 2502 | UINT8 EWRDSEQ; |
| 2503 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2504 | /** Offset 0x0C02 - Idle Energy Mc0Ch0Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2505 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2506 | **/ |
| 2507 | UINT8 IdleEnergyMc0Ch0Dimm0; |
| 2508 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2509 | /** Offset 0x0C03 - Idle Energy Mc0Ch0Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2510 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2511 | **/ |
| 2512 | UINT8 IdleEnergyMc0Ch0Dimm1; |
| 2513 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2514 | /** Offset 0x0C04 - Idle Energy Mc0Ch1Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2515 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2516 | **/ |
| 2517 | UINT8 IdleEnergyMc0Ch1Dimm0; |
| 2518 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2519 | /** Offset 0x0C05 - Idle Energy Mc0Ch1Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2520 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2521 | **/ |
| 2522 | UINT8 IdleEnergyMc0Ch1Dimm1; |
| 2523 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2524 | /** Offset 0x0C06 - Idle Energy Mc1Ch0Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2525 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2526 | **/ |
| 2527 | UINT8 IdleEnergyMc1Ch0Dimm0; |
| 2528 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2529 | /** Offset 0x0C07 - Idle Energy Mc1Ch0Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2530 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2531 | **/ |
| 2532 | UINT8 IdleEnergyMc1Ch0Dimm1; |
| 2533 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2534 | /** Offset 0x0C08 - Idle Energy Mc1Ch1Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2535 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2536 | **/ |
| 2537 | UINT8 IdleEnergyMc1Ch1Dimm0; |
| 2538 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2539 | /** Offset 0x0C09 - Idle Energy Mc1Ch1Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2540 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2541 | **/ |
| 2542 | UINT8 IdleEnergyMc1Ch1Dimm1; |
| 2543 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2544 | /** Offset 0x0C0A - PowerDown Energy Mc0Ch0Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2545 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2546 | **/ |
| 2547 | UINT8 PdEnergyMc0Ch0Dimm0; |
| 2548 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2549 | /** Offset 0x0C0B - PowerDown Energy Mc0Ch0Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2550 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2551 | **/ |
| 2552 | UINT8 PdEnergyMc0Ch0Dimm1; |
| 2553 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2554 | /** Offset 0x0C0C - PowerDown Energy Mc0Ch1Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2555 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2556 | **/ |
| 2557 | UINT8 PdEnergyMc0Ch1Dimm0; |
| 2558 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2559 | /** Offset 0x0C0D - PowerDown Energy Mc0Ch1Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2560 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2561 | **/ |
| 2562 | UINT8 PdEnergyMc0Ch1Dimm1; |
| 2563 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2564 | /** Offset 0x0C0E - PowerDown Energy Mc1Ch0Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2565 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2566 | **/ |
| 2567 | UINT8 PdEnergyMc1Ch0Dimm0; |
| 2568 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2569 | /** Offset 0x0C0F - PowerDown Energy Mc1Ch0Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2570 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2571 | **/ |
| 2572 | UINT8 PdEnergyMc1Ch0Dimm1; |
| 2573 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2574 | /** Offset 0x0C10 - PowerDown Energy Mc1Ch1Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2575 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2576 | **/ |
| 2577 | UINT8 PdEnergyMc1Ch1Dimm0; |
| 2578 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2579 | /** Offset 0x0C11 - PowerDown Energy Mc1Ch1Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2580 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2581 | **/ |
| 2582 | UINT8 PdEnergyMc1Ch1Dimm1; |
| 2583 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2584 | /** Offset 0x0C12 - Activate Energy Mc0Ch0Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2585 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2586 | **/ |
| 2587 | UINT8 ActEnergyMc0Ch0Dimm0; |
| 2588 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2589 | /** Offset 0x0C13 - Activate Energy Mc0Ch0Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2590 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2591 | **/ |
| 2592 | UINT8 ActEnergyMc0Ch0Dimm1; |
| 2593 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2594 | /** Offset 0x0C14 - Activate Energy Mc0Ch1Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2595 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2596 | **/ |
| 2597 | UINT8 ActEnergyMc0Ch1Dimm0; |
| 2598 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2599 | /** Offset 0x0C15 - Activate Energy Mc0Ch1Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2600 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2601 | **/ |
| 2602 | UINT8 ActEnergyMc0Ch1Dimm1; |
| 2603 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2604 | /** Offset 0x0C16 - Activate Energy Mc1Ch0Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2605 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2606 | **/ |
| 2607 | UINT8 ActEnergyMc1Ch0Dimm0; |
| 2608 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2609 | /** Offset 0x0C17 - Activate Energy Mc1Ch0Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2610 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2611 | **/ |
| 2612 | UINT8 ActEnergyMc1Ch0Dimm1; |
| 2613 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2614 | /** Offset 0x0C18 - Activate Energy Mc1Ch1Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2615 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2616 | **/ |
| 2617 | UINT8 ActEnergyMc1Ch1Dimm0; |
| 2618 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2619 | /** Offset 0x0C19 - Activate Energy Mc1Ch1Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2620 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2621 | **/ |
| 2622 | UINT8 ActEnergyMc1Ch1Dimm1; |
| 2623 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2624 | /** Offset 0x0C1A - Read Energy Mc0Ch0Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2625 | Read Energy Contribution, range[255;0],(212= Def) |
| 2626 | **/ |
| 2627 | UINT8 RdEnergyMc0Ch0Dimm0; |
| 2628 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2629 | /** Offset 0x0C1B - Read Energy Mc0Ch0Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2630 | Read Energy Contribution, range[255;0],(212= Def) |
| 2631 | **/ |
| 2632 | UINT8 RdEnergyMc0Ch0Dimm1; |
| 2633 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2634 | /** Offset 0x0C1C - Read Energy Mc0Ch1Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2635 | Read Energy Contribution, range[255;0],(212= Def) |
| 2636 | **/ |
| 2637 | UINT8 RdEnergyMc0Ch1Dimm0; |
| 2638 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2639 | /** Offset 0x0C1D - Read Energy Mc0Ch1Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2640 | Read Energy Contribution, range[255;0],(212= Def) |
| 2641 | **/ |
| 2642 | UINT8 RdEnergyMc0Ch1Dimm1; |
| 2643 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2644 | /** Offset 0x0C1E - Read Energy Mc1Ch0Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2645 | Read Energy Contribution, range[255;0],(212= Def) |
| 2646 | **/ |
| 2647 | UINT8 RdEnergyMc1Ch0Dimm0; |
| 2648 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2649 | /** Offset 0x0C1F - Read Energy Mc1Ch0Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2650 | Read Energy Contribution, range[255;0],(212= Def) |
| 2651 | **/ |
| 2652 | UINT8 RdEnergyMc1Ch0Dimm1; |
| 2653 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2654 | /** Offset 0x0C20 - Read Energy Mc1Ch1Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2655 | Read Energy Contribution, range[255;0],(212= Def) |
| 2656 | **/ |
| 2657 | UINT8 RdEnergyMc1Ch1Dimm0; |
| 2658 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2659 | /** Offset 0x0C21 - Read Energy Mc1Ch1Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2660 | Read Energy Contribution, range[255;0],(212= Def) |
| 2661 | **/ |
| 2662 | UINT8 RdEnergyMc1Ch1Dimm1; |
| 2663 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2664 | /** Offset 0x0C22 - Write Energy Mc0Ch0Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2665 | Write Energy Contribution, range[255;0],(221= Def) |
| 2666 | **/ |
| 2667 | UINT8 WrEnergyMc0Ch0Dimm0; |
| 2668 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2669 | /** Offset 0x0C23 - Write Energy Mc0Ch0Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2670 | Write Energy Contribution, range[255;0],(221= Def) |
| 2671 | **/ |
| 2672 | UINT8 WrEnergyMc0Ch0Dimm1; |
| 2673 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2674 | /** Offset 0x0C24 - Write Energy Mc0Ch1Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2675 | Write Energy Contribution, range[255;0],(221= Def) |
| 2676 | **/ |
| 2677 | UINT8 WrEnergyMc0Ch1Dimm0; |
| 2678 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2679 | /** Offset 0x0C25 - Write Energy Mc0Ch1Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2680 | Write Energy Contribution, range[255;0],(221= Def) |
| 2681 | **/ |
| 2682 | UINT8 WrEnergyMc0Ch1Dimm1; |
| 2683 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2684 | /** Offset 0x0C26 - Write Energy Mc1Ch0Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2685 | Write Energy Contribution, range[255;0],(221= Def) |
| 2686 | **/ |
| 2687 | UINT8 WrEnergyMc1Ch0Dimm0; |
| 2688 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2689 | /** Offset 0x0C27 - Write Energy Mc1Ch0Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2690 | Write Energy Contribution, range[255;0],(221= Def) |
| 2691 | **/ |
| 2692 | UINT8 WrEnergyMc1Ch0Dimm1; |
| 2693 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2694 | /** Offset 0x0C28 - Write Energy Mc1Ch1Dimm0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2695 | Write Energy Contribution, range[255;0],(221= Def) |
| 2696 | **/ |
| 2697 | UINT8 WrEnergyMc1Ch1Dimm0; |
| 2698 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2699 | /** Offset 0x0C29 - Write Energy Mc1Ch1Dimm1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2700 | Write Energy Contribution, range[255;0],(221= Def) |
| 2701 | **/ |
| 2702 | UINT8 WrEnergyMc1Ch1Dimm1; |
| 2703 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2704 | /** Offset 0x0C2A - Throttler CKEMin Timer |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2705 | Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). |
| 2706 | Dfault is 0x00 |
| 2707 | **/ |
| 2708 | UINT8 ThrtCkeMinTmr; |
| 2709 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2710 | /** Offset 0x0C2B - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2711 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2712 | UINT8 Reserved63[2]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2713 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2714 | /** Offset 0x0C2D - Rapl Power Floor Ch0 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2715 | Power budget ,range[255;0],(0= 5.3W Def) |
| 2716 | **/ |
| 2717 | UINT8 RaplPwrFlCh0; |
| 2718 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2719 | /** Offset 0x0C2E - Rapl Power Floor Ch1 |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2720 | Power budget ,range[255;0],(0= 5.3W Def) |
| 2721 | **/ |
| 2722 | UINT8 RaplPwrFlCh1; |
| 2723 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2724 | /** Offset 0x0C2F - Command Rate Support |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2725 | CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs |
| 2726 | 0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS |
| 2727 | **/ |
| 2728 | UINT8 EnCmdRate; |
| 2729 | |
Kilari Raasi | 9c28ab1 | 2023-06-19 16:26:21 +0530 | [diff] [blame] | 2730 | /** Offset 0x0C30 - MC_REFRESH_RATE |
| 2731 | Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh |
| 2732 | 0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2733 | **/ |
Kilari Raasi | 9c28ab1 | 2023-06-19 16:26:21 +0530 | [diff] [blame] | 2734 | UINT8 McRefreshRate; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2735 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2736 | /** Offset 0x0C31 - Energy Performance Gain |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2737 | Enable/disable Energy Performance Gain. <b>0: Disable</b>; 1: Enable |
| 2738 | $EN_DIS |
| 2739 | **/ |
| 2740 | UINT8 EpgEnable; |
| 2741 | |
Kilari Raasi | 9c28ab1 | 2023-06-19 16:26:21 +0530 | [diff] [blame] | 2742 | /** Offset 0x0C32 - RH pTRR LFSR0 Mask |
| 2743 | Row Hammer pTRR LFSR0 Mask, 1/2^(value) |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2744 | **/ |
Kilari Raasi | 9c28ab1 | 2023-06-19 16:26:21 +0530 | [diff] [blame] | 2745 | UINT8 Lfsr0Mask; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2746 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2747 | /** Offset 0x0C33 - User Manual Threshold |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2748 | Disabled: Predefined threshold will be used.\n |
| 2749 | Enabled: User Input will be used. |
| 2750 | $EN_DIS |
| 2751 | **/ |
| 2752 | UINT8 UserThresholdEnable; |
| 2753 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2754 | /** Offset 0x0C34 - User Manual Budget |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2755 | Disabled: Configuration of memories will defined the Budget value.\n |
| 2756 | Enabled: User Input will be used. |
| 2757 | $EN_DIS |
| 2758 | **/ |
| 2759 | UINT8 UserBudgetEnable; |
| 2760 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2761 | /** Offset 0x0C35 - Reserved |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 2762 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2763 | UINT8 Reserved64; |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 2764 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2765 | /** Offset 0x0C36 - Power Down Mode |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2766 | This option controls command bus tristating during idle periods |
| 2767 | 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto |
| 2768 | **/ |
| 2769 | UINT8 PowerDownMode; |
| 2770 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2771 | /** Offset 0x0C37 - Pwr Down Idle Timer |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2772 | The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means |
| 2773 | AUTO: 64 for ULX/ULT, 128 for DT/Halo |
| 2774 | **/ |
| 2775 | UINT8 PwdwnIdleCounter; |
| 2776 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2777 | /** Offset 0x0C38 - Page Close Idle Timeout |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2778 | This option controls Page Close Idle Timeout |
| 2779 | 0:Enabled, 1:Disabled |
| 2780 | **/ |
| 2781 | UINT8 DisPgCloseIdleTimeout; |
| 2782 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2783 | /** Offset 0x0C39 - Bitmask of ranks that have CA bus terminated |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2784 | Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, |
| 2785 | Rank0 is terminating and Rank1 is non-terminating</b> |
| 2786 | **/ |
| 2787 | UINT8 CmdRanksTerminated; |
| 2788 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2789 | /** Offset 0x0C3A - PcdSerialDebugLevel |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2790 | Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, |
| 2791 | Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, |
| 2792 | Info & Verbose. |
| 2793 | 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load |
| 2794 | Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose |
| 2795 | **/ |
| 2796 | UINT8 PcdSerialDebugLevel; |
| 2797 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2798 | /** Offset 0x0C3B - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2799 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2800 | UINT8 Reserved65[8]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2801 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2802 | /** Offset 0x0C43 - Ask MRC to clear memory content |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2803 | Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory. |
| 2804 | $EN_DIS |
| 2805 | **/ |
| 2806 | UINT8 CleanMemory; |
| 2807 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2808 | /** Offset 0x0C44 - TCSS USB Port Enable |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2809 | Bitmap for per port enabling |
| 2810 | **/ |
| 2811 | UINT8 UsbTcPortEnPreMem; |
| 2812 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2813 | /** Offset 0x0C45 - Reserved |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2814 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2815 | UINT8 Reserved66; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2816 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2817 | /** Offset 0x0C46 - Post Code Output Port |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2818 | This option configures Post Code Output Port |
| 2819 | **/ |
| 2820 | UINT16 PostCodeOutputPort; |
| 2821 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2822 | /** Offset 0x0C48 - RMTLoopCount |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2823 | Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO |
| 2824 | **/ |
| 2825 | UINT8 RMTLoopCount; |
| 2826 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2827 | /** Offset 0x0C49 - Enable/Disable SA CRID |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2828 | Enable: SA CRID, Disable (Default): SA CRID |
| 2829 | $EN_DIS |
| 2830 | **/ |
| 2831 | UINT8 CridEnable; |
| 2832 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2833 | /** Offset 0x0C4A - Reserved |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 2834 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2835 | UINT8 Reserved67[2]; |
Kilari Raasi | eac71c0 | 2023-01-30 16:02:34 +0530 | [diff] [blame] | 2836 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2837 | /** Offset 0x0C4C - BCLK RFI Frequency |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2838 | Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No |
| 2839 | RFI Tuning</b>. Range is 98Mhz-100Mhz. |
| 2840 | **/ |
| 2841 | UINT32 BclkRfiFreq[4]; |
| 2842 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2843 | /** Offset 0x0C5C - Size of PCIe IMR. |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2844 | Size of PCIe IMR in megabytes |
| 2845 | **/ |
| 2846 | UINT16 PcieImrSize; |
| 2847 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2848 | /** Offset 0x0C5E - Enable PCIe IMR |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2849 | 0: Disable(AUTO), 1: Enable |
| 2850 | $EN_DIS |
| 2851 | **/ |
| 2852 | UINT8 PcieImrEnabled; |
| 2853 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2854 | /** Offset 0x0C5F - Enable PCIe IMR |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2855 | 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select |
| 2856 | the Root port location from PCH PCIe or SA PCIe |
| 2857 | $EN_DIS |
| 2858 | **/ |
| 2859 | UINT8 PcieImrRpLocation; |
| 2860 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2861 | /** Offset 0x0C60 - Root port number for IMR. |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2862 | Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port |
| 2863 | from 0 to 23 and if it is SA PCIe then select root port from 0 to 3 |
| 2864 | **/ |
| 2865 | UINT8 PcieImrRpSelection; |
| 2866 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2867 | /** Offset 0x0C61 - SerialDebugMrcLevel |
Subrata Banik | 8206741 | 2022-07-01 09:12:08 +0000 | [diff] [blame] | 2868 | MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, |
| 2869 | Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, |
| 2870 | Info & Verbose. |
| 2871 | 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load |
| 2872 | Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2873 | **/ |
Subrata Banik | 8206741 | 2022-07-01 09:12:08 +0000 | [diff] [blame] | 2874 | UINT8 SerialDebugMrcLevel; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2875 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2876 | /** Offset 0x0C62 - Reserved |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 2877 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2878 | UINT8 Reserved68[11]; |
Kilari Raasi | 9c28ab1 | 2023-06-19 16:26:21 +0530 | [diff] [blame] | 2879 | |
| 2880 | /** Offset 0x0C6D - RH pTRR LFSR1 Mask |
| 2881 | Row Hammer pTRR LFSR1 Mask, 1/2^(value) |
| 2882 | **/ |
| 2883 | UINT8 Lfsr1Mask; |
| 2884 | |
| 2885 | /** Offset 0x0C6E - Reserved |
| 2886 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2887 | UINT8 Reserved69; |
Srinidhi N Kaushik | b2d9d57 | 2022-06-01 15:11:36 -0700 | [diff] [blame] | 2888 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2889 | /** Offset 0x0C6F - Command Pins Mapping |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2890 | BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller |
| 2891 | 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. |
| 2892 | **/ |
| 2893 | UINT8 Lp5CccConfig; |
| 2894 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2895 | /** Offset 0x0C70 - Command Pins Mirrored |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2896 | BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller |
| 2897 | 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. |
| 2898 | **/ |
| 2899 | UINT8 CmdMirror; |
| 2900 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2901 | /** Offset 0x0C71 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2902 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2903 | UINT8 Reserved70[3]; |
| 2904 | |
| 2905 | /** Offset 0x0C74 - LowerBasicMemTestSize |
| 2906 | Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable |
| 2907 | $EN_DIS |
| 2908 | **/ |
| 2909 | UINT8 LowerBasicMemTestSize; |
| 2910 | |
| 2911 | /** Offset 0x0C75 - Reserved |
| 2912 | **/ |
| 2913 | UINT8 Reserved71[20]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2914 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2915 | /** Offset 0x0C89 - Skip external display device scanning |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2916 | Enable: Do not scan for external display device, Disable (Default): Scan external |
| 2917 | display devices |
| 2918 | $EN_DIS |
| 2919 | **/ |
| 2920 | UINT8 SkipExtGfxScan; |
| 2921 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2922 | /** Offset 0x0C8A - Generate BIOS Data ACPI Table |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2923 | Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it |
| 2924 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2925 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2926 | UINT8 BdatEnable; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2927 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2928 | /** Offset 0x0C8B - Lock PCU Thermal Management registers |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2929 | Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 |
| 2930 | $EN_DIS |
| 2931 | **/ |
| 2932 | UINT8 LockPTMregs; |
| 2933 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2934 | /** Offset 0x0C8C - Panel Power Enable |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2935 | Control for enabling/disabling VDD force bit (Required only for early enabling of |
| 2936 | eDP panel). 0=Disable, 1(Default)=Enable |
| 2937 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2938 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2939 | UINT8 PanelPowerEnable; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2940 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2941 | /** Offset 0x0C8D - BdatTestType |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2942 | Indicates the type of Memory Training data to populate into the BDAT ACPI table. |
| 2943 | 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D |
| 2944 | **/ |
| 2945 | UINT8 BdatTestType; |
| 2946 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2947 | /** Offset 0x0C8E - Reserved |
Srinidhi N Kaushik | 15b439e | 2022-07-29 16:06:05 -0700 | [diff] [blame] | 2948 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2949 | UINT8 Reserved72[2]; |
Srinidhi N Kaushik | 15b439e | 2022-07-29 16:06:05 -0700 | [diff] [blame] | 2950 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2951 | /** Offset 0x0C90 - PMR Size |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2952 | Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot |
| 2953 | **/ |
| 2954 | UINT32 DmaBufferSize; |
| 2955 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2956 | /** Offset 0x0C94 - The policy for VTd driver behavior |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2957 | BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS |
| 2958 | **/ |
| 2959 | UINT8 PreBootDmaMask; |
| 2960 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2961 | /** Offset 0x0C95 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2962 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2963 | UINT8 Reserved73[143]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2964 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2965 | /** Offset 0x0D24 - TotalFlashSize |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2966 | Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable |
| 2967 | **/ |
| 2968 | UINT16 TotalFlashSize; |
| 2969 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2970 | /** Offset 0x0D26 - BiosSize |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2971 | The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != |
| 2972 | 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected |
| 2973 | Range) so that a BIOS Update Script can be stored in the DPR. |
| 2974 | **/ |
| 2975 | UINT16 BiosSize; |
| 2976 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2977 | /** Offset 0x0D28 - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2978 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2979 | UINT8 Reserved74[28]; |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2980 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2981 | /** Offset 0x0D44 - Smbus dynamic power gating |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2982 | Disable or Enable Smbus dynamic power gating. |
| 2983 | $EN_DIS |
| 2984 | **/ |
| 2985 | UINT8 SmbusDynamicPowerGating; |
| 2986 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2987 | /** Offset 0x0D45 - Disable and Lock Watch Dog Register |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 2988 | Set 1 to clear WDT status, then disable and lock WDT registers. |
| 2989 | $EN_DIS |
| 2990 | **/ |
| 2991 | UINT8 WdtDisableAndLock; |
| 2992 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2993 | /** Offset 0x0D46 - Reserved |
Kilari Raasi | b120758 | 2023-03-20 12:19:23 +0530 | [diff] [blame] | 2994 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 2995 | UINT8 Reserved75[2]; |
Kilari Raasi | b120758 | 2023-03-20 12:19:23 +0530 | [diff] [blame] | 2996 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 2997 | /** Offset 0x0D48 - SMBUS SPD Write Disable |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 2998 | Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write |
| 2999 | Disable bit. For security recommendations, SPD write disable bit must be set. |
| 3000 | $EN_DIS |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 3001 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3002 | UINT8 SmbusSpdWriteDisable; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 3003 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3004 | /** Offset 0x0D49 - Reserved |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 3005 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 3006 | UINT8 Reserved76[34]; |
vjadeja-intel | 0ddeaed | 2022-11-03 14:48:46 +0530 | [diff] [blame] | 3007 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3008 | /** Offset 0x0D6B - HECI Timeouts |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3009 | 0: Disable, 1: Enable (Default) timeout check for HECI |
| 3010 | $EN_DIS |
| 3011 | **/ |
| 3012 | UINT8 HeciTimeouts; |
| 3013 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3014 | /** Offset 0x0D6C - Force ME DID Init Status |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3015 | Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set |
| 3016 | ME DID init stat value |
| 3017 | $EN_DIS |
| 3018 | **/ |
| 3019 | UINT8 DidInitStat; |
| 3020 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3021 | /** Offset 0x0D6D - CPU Replaced Polling Disable |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3022 | Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop |
| 3023 | $EN_DIS |
| 3024 | **/ |
| 3025 | UINT8 DisableCpuReplacedPolling; |
| 3026 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3027 | /** Offset 0x0D6E - Check HECI message before send |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3028 | Test, 0: disable, 1: enable, Enable/Disable message check. |
| 3029 | $EN_DIS |
| 3030 | **/ |
| 3031 | UINT8 DisableMessageCheck; |
| 3032 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3033 | /** Offset 0x0D6F - Skip MBP HOB |
| 3034 | Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob. |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3035 | $EN_DIS |
| 3036 | **/ |
| 3037 | UINT8 SkipMbpHob; |
| 3038 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3039 | /** Offset 0x0D70 - HECI2 Interface Communication |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3040 | Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. |
| 3041 | $EN_DIS |
| 3042 | **/ |
| 3043 | UINT8 HeciCommunication2; |
| 3044 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3045 | /** Offset 0x0D71 - Enable KT device |
Kilari Raasi | b120758 | 2023-03-20 12:19:23 +0530 | [diff] [blame] | 3046 | Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device. |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3047 | $EN_DIS |
| 3048 | **/ |
| 3049 | UINT8 KtDeviceEnable; |
| 3050 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3051 | /** Offset 0x0D72 - Skip CPU replacement check |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 3052 | Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check |
| 3053 | $EN_DIS |
| 3054 | **/ |
| 3055 | UINT8 SkipCpuReplacementCheck; |
| 3056 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3057 | /** Offset 0x0D73 - Reserved |
| 3058 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 3059 | UINT8 Reserved77[100]; |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3060 | |
| 3061 | /** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3062 | AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in |
| 3063 | 1/100 units, where a value of 125 would apply a 1.25 scale factor. |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 3064 | **/ |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3065 | UINT8 Avx2VoltageScaleFactor; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 3066 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3067 | /** Offset 0x0DD8 - Avx512 Voltage Guardband Scaling Factor |
Subrata Banik | d0de6c2 | 2023-08-30 17:38:50 +0000 | [diff] [blame] | 3068 | DEPRECATED. AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range |
| 3069 | is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3070 | **/ |
| 3071 | UINT8 Avx512VoltageScaleFactor; |
| 3072 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3073 | /** Offset 0x0DD9 - Serial Io Uart Debug Mode |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 3074 | Select SerialIo Uart Controller mode |
| 3075 | 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, |
| 3076 | 4:SerialIoUartSkipInit |
| 3077 | **/ |
| 3078 | UINT8 SerialIoUartDebugMode; |
| 3079 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3080 | /** Offset 0x0DDA - Reserved |
Kilari Raasi | b120758 | 2023-03-20 12:19:23 +0530 | [diff] [blame] | 3081 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 3082 | UINT8 Reserved78[2]; |
Kilari Raasi | b120758 | 2023-03-20 12:19:23 +0530 | [diff] [blame] | 3083 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3084 | /** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3085 | Select RX pin muxing for SerialIo UART used for debug |
| 3086 | **/ |
| 3087 | UINT32 SerialIoUartDebugRxPinMux; |
| 3088 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3089 | /** Offset 0x0DE0 - SerialIoUartDebugTxPinMux - FSPM |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3090 | Select TX pin muxing for SerialIo UART used for debug |
| 3091 | **/ |
| 3092 | UINT32 SerialIoUartDebugTxPinMux; |
| 3093 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3094 | /** Offset 0x0DE4 - SerialIoUartDebugRtsPinMux - FSPM |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3095 | Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* |
| 3096 | for possible values. |
| 3097 | **/ |
| 3098 | UINT32 SerialIoUartDebugRtsPinMux; |
| 3099 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3100 | /** Offset 0x0DE8 - SerialIoUartDebugCtsPinMux - FSPM |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3101 | Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* |
| 3102 | for possible values. |
| 3103 | **/ |
| 3104 | UINT32 SerialIoUartDebugCtsPinMux; |
| 3105 | |
Kilari Raasi | b07209f | 2023-04-27 14:44:40 +0530 | [diff] [blame] | 3106 | /** Offset 0x0DEC - Reserved |
Kapil Porwal | a42ad28 | 2022-07-07 18:28:30 +0000 | [diff] [blame] | 3107 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 3108 | UINT8 Reserved79[164]; |
Kilari Raasi | 9c28ab1 | 2023-06-19 16:26:21 +0530 | [diff] [blame] | 3109 | |
| 3110 | /** Offset 0x0E90 - TME Exclude Base Address |
| 3111 | TME Exclude Base Address. |
| 3112 | **/ |
| 3113 | UINT64 TmeExcludeBase; |
| 3114 | |
| 3115 | /** Offset 0x0E98 - TME Exclude Size Value |
| 3116 | TME Exclude Size Value. |
| 3117 | **/ |
| 3118 | UINT64 TmeExcludeSize; |
| 3119 | |
| 3120 | /** Offset 0x0EA0 - Generate New TME Key |
| 3121 | Enable: Generate New TME Key, Disable(Default): TME key determine by type of reset |
| 3122 | $EN_DIS |
| 3123 | **/ |
| 3124 | UINT8 GenerateNewTmeKey; |
| 3125 | |
| 3126 | /** Offset 0x0EA1 - Reserved |
| 3127 | **/ |
Subrata Banik | 17d619c | 2023-09-22 12:26:11 +0530 | [diff] [blame] | 3128 | UINT8 Reserved80[7]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 3129 | } FSP_M_CONFIG; |
| 3130 | |
| 3131 | /** Fsp M UPD Configuration |
| 3132 | **/ |
| 3133 | typedef struct { |
| 3134 | |
| 3135 | /** Offset 0x0000 |
| 3136 | **/ |
| 3137 | FSP_UPD_HEADER FspUpdHeader; |
| 3138 | |
| 3139 | /** Offset 0x0020 |
| 3140 | **/ |
| 3141 | FSPM_ARCH_UPD FspmArchUpd; |
| 3142 | |
| 3143 | /** Offset 0x0040 |
| 3144 | **/ |
| 3145 | FSP_M_CONFIG FspmConfig; |
| 3146 | |
Kilari Raasi | 6a7703f | 2023-05-30 12:36:36 +0530 | [diff] [blame] | 3147 | /** Offset 0x0EA8 |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 3148 | **/ |
Subrata Banik | 6ed4315 | 2022-11-22 16:36:37 +0530 | [diff] [blame] | 3149 | UINT8 Rsvd500[6]; |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 3150 | |
Kilari Raasi | 6a7703f | 2023-05-30 12:36:36 +0530 | [diff] [blame] | 3151 | /** Offset 0x0EAE |
Srinidhi N Kaushik | 0876103 | 2022-06-02 00:10:28 -0700 | [diff] [blame] | 3152 | **/ |
| 3153 | UINT16 UpdTerminator; |
| 3154 | } FSPM_UPD; |
| 3155 | |
| 3156 | #pragma pack() |
| 3157 | |
| 3158 | #endif |