| commit | 8206741a062115119a3c005af27c059853a0eafe | [log] [tgz] |
|---|---|---|
| author | Subrata Banik <subratabanik@google.com> | Fri Jul 01 09:12:08 2022 +0000 |
| committer | Subrata Banik <subratabanik@google.com> | Sun Jul 03 04:57:33 2022 +0000 |
| tree | ad38ffa2e5024e20857881ef0a00e8478d57175b | |
| parent | abc59fb6fc8f46d987980ae596e72d475e8c602c [diff] |
vc/intel/fsp2_0: Add UPDs into the FSP partial header version 2222 This patch adds below UPDs into the existing FSP partial header v2222.1 FSP-M UPD: DisableMc0Ch0 DisableMc0Ch1 DisableMc0Ch2 DisableMc0Ch3 DisableMc1Ch0 DisableMc1Ch1 DisableMc1Ch2 DisableMc1Ch3 DdrFreqLimit GpioOverride SerialIoUartDebugMode SerialDebugMrcLevel SmbusDynamicPowerGating WdtDisableAndLock SaIpuEnable SkipCpuReplacementCheck TcssDma0En TcssDma1En VtdBaseAddress CpuCrashLogDevice CpuCrashLogEnable LCT TdcEnable TdcTimeWindow Lp5CccConfig RMTBIT RmtPerTask RMTLoopCount MrcFastBoot EnCmdRate SaGvGear TAT PchHdaVcType BdatTestType RdEnergyMc0Ch0Dimm1 RdEnergyMc0Ch0Dimm0 CorePllVoltageOffset RdEnergyMc1Ch1Dimm1 RdEnergyMc1Ch1Dimm0 DciEn PchPort80Route ActEnergyMc0Ch1Dimm1 ActEnergyMc0Ch1Dimm0 HeciCommunication2 PcdSerialDebugBaudRate HeciTimeouts ThrtCkeMinDefeatLpddr PchPcieHsioRxSetCtle BdatEnable DisableCpuReplacedPolling PchSataHsioRxGen1EqBoostMagEnable CoreVoltageOffset PchPcieHsioTxGen1DownscaleAmp PchHdaDspUaaCompliance VddVoltage WRVC1D PreBootDmaMask tWR RingVoltageAdaptive PchSataHsioTxGen3DeEmphEnable PchPcieHsioRxSetCtleEnable RingPllVoltageOffset OcSupport WrEnergyMc0Ch0Dimm1 PdEnergyMc1Ch1Dimm1 PdEnergyMc1Ch1Dimm0 DmiGen3ProgramStaticEq SmramMask tRAS PerCoreHtDisable IdleEnergyMc1Ch0Dimm0 IdleEnergyMc1Ch0Dimm1 Gen3LtcoEnable tWTR RCVET DmiGen3UsPresetEnable tCWL PwdwnIdleCounter WRTC1D CLKTCO PrimaryDisplay DisableMessageCheck tFAW PchSataHsioTxGen2DeEmphEnable SerialIoUartDebugRtsPinMux GtExtraTurboVoltage TXTCO PchSataHsioTxGen3DownscaleAmp CpuRatioOverride PostCodeOutputPort DmiHweq CoreVfPointCount NModeSupport Ddr4DdpSharedZq RdEnergyMc1Ch0Dimm0 RdEnergyMc1Ch0Dimm1 PchSataHsioTxGen2DownscaleAmp DebugInterfaceEnable WrEnergyMc0Ch1Dimm0 WrEnergyMc0Ch1Dimm1 SaPllVoltageOffset DmiGen3EndPointPreset PchSataHsioRxGen2EqBoostMag VDDQT PvdRatioThreshold CoreVfPointOffsetMode DmiGen3DsPortRxPreset BclkRfiFreq SmbusArpEnable PowerDownMode DebugInterfaceLockEnable RingVoltageOffset EnableExtts SerialIoUartDebugCtsPinMux PchPcieHsioTxGen2DownscaleAmpEnable Avx2VoltageScaleFactor GearRatio GtVoltageOverride EccSupport RingMaxOcRatio TrainTrace EnablePwrDn IsTPMPresence OcLock DmaBufferSize SOT CoreVfPointRatio PchPcieHsioTxGen2DownscaleAmp TjMaxOffset CoreMaxOcRatio RingDownBin PchSataHsioRxGen1EqBoostMag BiosAcmSize tRFC PchPcieHsioTxGen1DownscaleAmpEnable PdEnergyMc0Ch1Dimm0 PdEnergyMc0Ch1Dimm1 RDMPRT TxtLcpPdBase CMDVC SerialIoUartDebugBaudRate PchTraceHubMemReg1Size CoreVoltageOverride McPllVoltageOffset PdEnergyMc1Ch0Dimm0 PdEnergyMc1Ch0Dimm1 GttMmAdr PchPcieHsioTxGen1DeEmphEnable ApStartupBase CoreVoltageAdaptive GtVoltageMode PcieImrRpSelection TxtLcpPdSize PchPcieHsioTxGen2DeEmph3p5 ThrtCkeMinTmr RealtimeMemoryTiming UserBudgetEnable PchPcieHsioTxGen3DownscaleAmpEnable GmAdr PchSataHsioTxGen1DeEmphEnable CrashLogGprs tRTP RMC PchSataHsioTxGen3DownscaleAmpEnable RDODTT RDVREFDC PerCoreRatio IdleEnergyMc0Ch1Dimm1 tRCDtRP DidInitStat SerialIoUartDebugRxPinMux SerialIoUartDebugMmioBase BiosSize MmioSizeAdjustment PchTraceHubMode DmiGen3Ltcpre CoreVoltageMode DmiGen3UsPortTxPreset Gen3EqPhase3Bypass BclkSource KtDeviceEnable DciUsb3TypecUfpDbg CoreVfPointOffset Gen3RtcoRtpoEnable TotalFlashSize BclkAdaptiveVoltage TvbRatioClipping EnablePwrDnLpddr WRTC2D RankInterleave PchSataHsioRxGen3EqBoostMag IdleEnergyMc0Ch0Dimm1 IdleEnergyMc0Ch0Dimm0 Ratio JWRL Avx3RatioOffset Avx2RatioOffset RDVC1D DCC PchSataHsioTxGen2DeEmph ExitOnFailure IdleEnergyMc1Ch1Dimm1 IdleEnergyMc1Ch1Dimm0 RingVoltageOverride SpdProfileSelected ScramblerSupport SaGvFreq WRVC2D DmiGen3EqPh3Method CMDSR RdEnergyMc0Ch1Dimm0 RdEnergyMc0Ch1Dimm1 UserThresholdEnable ThrtCkeMinDefeat DmiGen3EqPh2Enable tRRD ChHashEnable BistOnReset ChHashInterleaveBit RemapEnable RDVC2D DIMMRONT WrEnergyMc0Ch0Dimm0 DmiAspm PchPcieHsioTxGen2DeEmph6p0Enable PchSataHsioTxGen1DeEmph RDEQT TxtDprMemoryBase WrEnergyMc1Ch0Dimm1 WrEnergyMc1Ch0Dimm0 DmiGen3EndPointHint CleanMemory PchSmbAlertEnable SaOcSupport PchSataHsioTxGen3DeEmph TxtImplemented CoreVfPointOffsetPrefix PchHdaTestPowerClockGating DmaControlGuarantee DIMMODTT ERDMPRTC2D RootPortIndex SkipStopPbet VtdIopEnable DmiGen3DsPortTxPreset ActiveCoreCount PchLpcEnhancePort8xhDecoding GtVoltageOffset DisPgCloseIdleTimeout ActEnergyMc1Ch0Dimm1 ActEnergyMc1Ch0Dimm0 Idd3n Idd3p PchSataHsioTxGen1DownscaleAmpEnable BClkFrequency ActEnergyMc0Ch0Dimm0 ActEnergyMc0Ch0Dimm1 DdrFreqLimit Gen3EqPhase23Bypass WrEnergyMc1Ch1Dimm0 DmiGen3DsPresetEnable PcieImrSize EWRTC2D IbeccOperationMode VtdBaseAddress TvbVoltageOptimization DciDbcMode HobBufferSize PchHdaSdiEnable PcieImrEnabled IdleEnergyMc0Ch1Dimm0 SerialIoUartDebugAutoFlow tCL PdEnergyMc0Ch0Dimm1 PdEnergyMc0Ch0Dimm0 RDTC2D ERDTC2D SerialIoUartDebugParity PchPcieHsioTxGen2DeEmph3p5Enable PchPcieHsioTxGen1DeEmph DmiGen3Ltcpo PchSmbusIoBase RaplPwrFlCh1 RaplPwrFlCh0 EnhancedInterleave PchPcieHsioTxGen2DeEmph6p0 MemTestOnWarmBoot Ibecc PanelPowerEnable BiosAcmBase DmiGen3UsPortRxPreset DmiAspmL1ExitLatency CmdMirror PchSataHsioTxGen2DownscaleAmpEnable tREFI CpuBclkOcFrequency CridEnable EpgEnable SmbusSpdWriteDisable DdrSpeedControl PchSataHsioRxGen2EqBoostMagEnable GtMaxOcRatio DmiMaxLinkSpeed PchSataHsioRxGen3EqBoostMagEnable PcieImrRpLocation CmdRanksTerminated SkipMbpHob SerialIoUartDebugTxPinMux PchSataHsioTxGen1DownscaleAmp PchPcieHsioTxGen3DownscaleAmp PerCoreRatioOverride PchHdaAudioLinkDmicClockSelect SerialIoUartDebugDataBits SrefCfgEna Avx512VoltageScaleFactor MmioSize SaVoltageOffset SaIpuEnable ActEnergyMc1Ch1Dimm0 ActEnergyMc1Ch1Dimm1 ProbelessTrace VtdIgdEnable ALIASCHK PchTraceHubMemReg0Size DIMMODTCA TgaSize EWRDSEQ SerialIoUartDebugStopBits RDTC1D CMDNORM RingVoltageMode EnableAbove4GBMmio WrEnergyMc1Ch1Dimm1 Txt PcieMultipleSegmentEnabled CnviDdrRfim FSP-S UPD: CpuMpPpi LidStatus ITbtConnectTopologyTimeoutInMs D3HotEnable D3ColdEnable PchLockDownGlobalSmi PchLockDownBiosInterface PchUnlockGpioPads RtcMemoryLock SkipPamLock EndOfPostMessage CpuUsb3OverCurrentPin PcieRpHotPlug SerialIoUartAutoFlow TccActivationOffset VmdEnable Enable8254ClockGating Enable8254ClockGatingOnS3 HybridStorageMode PcieRpHotPlug Hwp Cx PsOnEnable EnergyEfficientTurbo PchPmDisableEnergyReport UfsEnable FspEventHandler GnaEnable VbtSize PcieComplianceTestMode CStatePreWake SerialIoUartDataBits SataPortsExternal CstateLatencyControl0TimeUnit SataP0Tinact PmcV1p05PhyExtFetControlEn ApIdleManner SataPortsSpinUp DisableProcHotOut ITbtPcieTunnelingForUsb4 SerialIoUartDmaEnable SaPcieItbtRpNonSnoopLatencyOverrideMode SaPcieItbtRpSnoopLatencyOverrideMode MlcSpatialPrefetcher PchXhciOcLock PmcPowerButtonDebounce TccOffsetClamp LogoPixelWidth AvxDisable Custom1PowerLimit1 Custom1PowerLimit2 PmcCpuC10GatePinEnable PchPmSlpStrchSusUp IshI2cSdaPadTermination Custom2PowerLimit1Time RtcBiosInterfaceLock WatchDogTimerBios SataP1TDisp PchPciePort8xhDecodePortIndex PcieRpImrSelection TcCstateLimit PchS0ixAutoDemotion PchFivrExtV1p05RailEnabledStates PcieRpSlotPowerLimitScale IshUartCtsPinMuxing PcieRpSnoopLatencyOverrideMode TTCrossThrottling PsysPowerLimit1 SataRstInterrupt IshSpiClkPadTermination PcieEnablePeerMemoryWrite SataP1T2M ChipsetInitBinPtr LogoPixelHeight PsysPowerLimit1Time HwpInterruptControl DevIntConfigPtr IshUartRtsPadTermination PsysPowerLimit1Power EnergyEfficientTurbo Custom3TurboActivationRatio PcieDpc TurboMode PchFivrExtVnnRailSupportedVoltageStates ITbtDmaLtr IshSpiClkPinMuxing PchSbAccessUnlock PcieRpSystemErrorOnCorrectableError PcieRpSlotPowerLimitValue SendEcCmd SataSpeedLimit SataRstPcieEnable PchUsb3HsioCtrlAdaptOffsetCfg SataP0T2M PchHdaVerbTableEntryNum DmiTS1TW DmiTS2TW PcieRpImrEnabled GpioIrqRoute SataPortsSolidStateDrive RaceToHalt PcieRpNonSnoopLatencyOverrideMultiplier PcieRpUnsupportedRequestReport AesEnable PchFivrExtVnnRailSxVoltage SataP1Tinact PkgCStateUnDemotion SataPortsZpOdd PchSerialIoI2cPadsTermination PchFivrExtV1p05RailSupportedVoltageStates PchUsbLtrLowIdleTimeOverride IshSpiMosiPinMuxing PchProtectedRangeLimit SaPcieItbtRpNonSnoopLatencyOverrideValue SataP1T3M PchPmWoWlanEnable IshUartRtsPinMuxing SataLedEnable VmdGlobalMapping PcieRpEnableCpm IshGpGpioPadTermination PchDmiCwbEnable ForcMebxSyncUp FspEventHandler PchFivrExtVnnRailIccMax PchPmMeWakeSts DisableD0I3SettingForHeci PcieRpNonSnoopLatencyOverrideMode PmgCstCfgCtrlLock PchUsbLtrHighIdleTimeOverride Usb3HsioTxRate2UniqTran SiNumberOfSsidTableEntry IshSpiMisoPadTermination IshUartRxPadTermination PcieRpSlotImplemented PchUsbOverCurrentEnable EndOfPostMessage SaPcieItbtRpSnoopLatencyOverrideValue EnableHwpAutoEppGrouping SerialIoUartDbg2 ConfigTdpLock EsataSpeedLimit PchTsnEnable PowerLimit3DutyCycle TTSuggestedSetting PchEnableDbcObs IehMode VmdPort PchFivrExtVnnRailCtrlRampTmr PchPmSlpAMinAssert CstateLatencyControl5TimeUnit ProcessorTraceEnable ChipsetInitBinLen PchTemperatureHotLevel Usb3HsioTxRate3UniqTranEnable NumberOfEntries Custom2ConfigTdpControl PowerLimit3Lock SiCustomizedSsid PchUsb3HsioFilterSelP DisableVrThermalAlert PchIoApicEntry24_119 SmbiosType4MaxSpeedOverride PowerLimit3Time C1StateUnDemotion PchDmiAspmCtrl PchUsb3HsioFilterSelN PchTTEnable PcieRpNoFatalErrorReport Custom1ConfigTdpControl PmcC10DynamicThresholdAdjustment PchFivrVccinAuxRetToLowCurModeVolTranTime BiProcHot VmdPortFunc PchUsb3HsioFilterSelNEnable PchHdaVerbTablePtr TurboPowerLimitLock PcieRpSystemErrorOnNonFatalError PmcUsb2PhySusPgEnable PcieRpSystemErrorOnFatalError PchProtectedRangeBase VccSt PchFivrExtVnnRailSxEnabledStates EnableHwpAutoPerCorePstate CstateLatencyControl1TimeUnit SaPcieItbtRpSnoopLatencyOverrideMultiplier PchPmSlpS4MinAssert PcieRpTransmitterHalfSwing Usb3HsioTxRate3UniqTran RenderStandby ProcessorTraceOutputScheme SkipFspGop PchHdaPme EcCmdProvisionEav BgpdtHash Usb3HsioTxRate0UniqTran UsbOverride PkgCStateDemotion EnableAllThermalFunctions PchPmWolEnableOverride IshSpiCsPinMuxing PchIshSpiCsEnable IshUartCtsPadTermination PmcV1p05IsExtFetControlEn MaxRingRatioLimit PchIshPdtUnlock IshUartTxPinMuxing PchFivrExtV1p05RailIccMax BiosGuardAttr LogoPtr CpuBistData ShowSpiController PchPmWolOvrWkSts SataP0T1M CstCfgCtrIoMwaitRedirection TcoIrqEnable PchHdaLinkFrequency ITbtForcePowerOnTimeoutInMs SerialIoSpiCsEnable VmdMemBar2Base TStates SiSkipSsidProgramming TccOffsetTimeWindowForRatl AmtSolEnabled PchUsb3HsioCtrlAdaptOffsetCfgEnable PchFivrExtVnnRailIccMaximum PchEspiLgmrEnable SkipPamLock IshGpGpioPinMuxing PchUsb3HsioFilterSelPEnable PchFivrExtVnnRailVoltage SataPortsDevSlpResetConfig ProcHotLock PchDmiTsawEn SerialIoSpiCsPolarity PkgCStateLimit EnableRsr PmcDbgMsgEn PchPmPwrCycDur NumOfDevIntConfig SerialIoSpiDefaultCsOutput PchPmPciePllSsc PxRcConfig CstateLatencyControl4TimeUnit PcieRpPmSci ConfigTdpBios PmcPdEnable PchT1Level PmcModPhySusPgEnable DisableTurboGt EnableTcoTimer IshSpiMisoPinMuxing IshI2cSclPinMuxing PcieRpCorrectableErrorReport C1StateAutoDemotion PchEspiLockLinkConfiguration PchFivrExtV1p05RailCtrlRampTmr SataRstPcieStoragePort PchFivrExtV1p05RailVoltage PchPmSlpSusMinAssert PchHotEnable PcieRpNonSnoopLatencyOverrideValue TcoIrqSelect PcieRpCompletionTimeout FwProgress StateRatioMax16 ConfigTdpLevel IshI2cSdaPinMuxing PcieRpPhysicalSlotNumber SerialIoUartParity TxtEnable PchLegacyIoLowLatency PchUsbLtrMediumIdleTimeOverride PchPmPmeB0S5Dis SerialIoUartPowerGating PcieRpSnoopLatencyOverrideValue PchPmSlpLanLowDc PchT2Level CstateLatencyControl2TimeUnit PchPmSlpS3MinAssert PchUsb3HsioOlfpsCfgPullUpDwnResEnable MonitorMwaitEnable Usb3HsioTxRate1UniqTran Eist IshSpiMosiPadTermination PowerLimit4Lock Custom3PowerLimit1Time PcieEnablePort8xhDecode DualTauBoost WatchDogEnabled MaxRatio Custom2TurboActivationRatio PchFivrExtVnnRailEnabledStates ApplyConfigTdp IshI2cSclPadTermination PowerLimit2Power ThermalMonitor CpuUsb3OverCurrentPin PchTTLock Custom1PowerLimit1Time PchEspiHostC10ReportEnable Usb3HsioTxRate2UniqTranEnable SataPortsInterlockSw EnablePerCorePState PsysPowerLimit2Power UfsEnable PchPmDisableNativePowerButton VmdVariablePtr Custom3PowerLimit2 PchPmDisableEnergyReport Custom3PowerLimit1 DmiTS3TW EnforceEDebugMode CstateLatencyControl3TimeUnit VmdCfgBarBase DmiSuggestedSetting SataPortsEnableDitoConfig SerialIoUartBaudRate Usb3HsioTxRate1UniqTranEnable SataPortsHotPlug MachineCheckEnable Custom1TurboActivationRatio Custom2PowerLimit1 Custom2PowerLimit2 VmdMemBar1Base SaPcieItbtRpLtrConfigLock SataP0TDispFinit PchFivrExtVnnRailSxIccMaximum PchTsnLinkSpeed SataThermalSuggestedSetting SaPcieItbtRpLtrEnable TimedMwait PchTsnMultiVcEnable PcieRpFunctionSwap PcieEqOverrideDefault SataP1T1M PsysPowerLimit2 PchLanLtrEnable SerialIoUartStopBits SciIrqSelect C1e PchFivrExtVnnRailSxIccMax PowerLimit3 PowerLimit2 PowerLimit1 MeUnconfigOnRtcClear PcieRpPcieSpeed PchUsbLtrOverrideEnable UsbPdoProgramming Custom3ConfigTdpControl SataP1TDispFinit PchFivrDynPm VmdPortDev EnableItbm MinRingRatioLimit PcieRpFatalErrorReport MctpBroadcastCycle EcCmdLock StateRatio PchPmVrAlert DmiTS0TW LogoSize PchIoApicId SaPcieItbtRpForceLtrOverride PcieRpSnoopLatencyOverrideMultiplier IshUartTxPadTermination PchCrid SataRstPcieDeviceResetDelay ProcHotResponse BltBufferSize MlcStreamerPrefetcher PcieRpLtrConfigLock SiSsidTablePtr SataP0TDisp PchUsb3HsioOlfpsCfgPullUpDwnRes BltBufferAddress PcieRpDetectTimeoutMs PpinSupport SataRstRaidDeviceId PchPmLatchEventsC10Exit IshUartRxPinMuxing PpmIrmSetting EnergyEfficientPState PchFivrExtV1p05RailIccMaximum PortResetMessageEnable PchReadProtectionEnable BiosGuardModulePtr PchWriteProtectionEnable AmtEnabled PchHdaCodecSxWakeCapability SiCustomizedSvid PcieEdpc TccOffsetLock PchPmPwrBtnOverridePeriod SaPcieItbtRpNonSnoopLatencyOverrideMultiplier WatchDogTimerOs PchTTState13Enable PowerLimit1Time PchT0Level IshSpiCsPadTermination SataP0T3M Usb3HsioTxRate0UniqTranEnable SataTestMode PmcOsIdleEnable PowerLimit4 PcieRpAcsEnabled PavpEnable UsbTcPortEn Additionally, optimize the `reserved` fields across header files. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I976a5762701711fbf000c43c5ff05f9bd93f688f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.