Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * inteltool - dump all registers on an Intel CPU + chipset based system. |
| 3 | * |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 4 | * Copyright (C) 2008-2010 by coresystems GmbH |
| 5 | * |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | */ |
| 19 | |
| 20 | #include <fcntl.h> |
| 21 | #include <unistd.h> |
| 22 | #include <stdio.h> |
| 23 | #include <stdlib.h> |
| 24 | #include <string.h> |
| 25 | #include <errno.h> |
| 26 | |
| 27 | #include "inteltool.h" |
| 28 | |
Mathias Krause | 9beb5df | 2011-06-27 14:35:00 +0200 | [diff] [blame] | 29 | #ifdef __x86_64__ |
| 30 | # define BREG "%%rbx" |
| 31 | #else |
| 32 | # define BREG "%%ebx" |
| 33 | #endif |
| 34 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 35 | int fd_msr; |
| 36 | |
| 37 | unsigned int cpuid(unsigned int op) |
| 38 | { |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 39 | uint32_t ret; |
| 40 | |
Mathias Krause | 5782fee | 2011-03-09 11:30:55 +0100 | [diff] [blame] | 41 | #if defined(__PIC__) || defined(__DARWIN__) && !defined(__LP64__) |
Stefan Reinauer | 1c60c88 | 2010-05-30 12:35:39 +0000 | [diff] [blame] | 42 | asm volatile ( |
Mathias Krause | 9beb5df | 2011-06-27 14:35:00 +0200 | [diff] [blame] | 43 | "push " BREG "\n\t" |
| 44 | "cpuid\n\t" |
| 45 | "pop " BREG "\n\t" |
Stefan Reinauer | 1c60c88 | 2010-05-30 12:35:39 +0000 | [diff] [blame] | 46 | : "=a" (ret) : "a" (op) : "%ecx", "%edx" |
| 47 | ); |
Stefan Reinauer | f182456 | 2009-04-22 23:17:44 +0000 | [diff] [blame] | 48 | #else |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 49 | asm ("cpuid" : "=a" (ret) : "a" (op) : "%ebx", "%ecx", "%edx"); |
Stefan Reinauer | f182456 | 2009-04-22 23:17:44 +0000 | [diff] [blame] | 50 | #endif |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 51 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 52 | return ret; |
| 53 | } |
| 54 | |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 55 | #ifndef __DARWIN__ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 56 | int msr_readerror = 0; |
| 57 | |
| 58 | msr_t rdmsr(int addr) |
| 59 | { |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 60 | uint32_t buf[2]; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 61 | msr_t msr = { 0xffffffff, 0xffffffff }; |
| 62 | |
| 63 | if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) { |
| 64 | perror("Could not lseek() to MSR"); |
| 65 | close(fd_msr); |
| 66 | exit(1); |
| 67 | } |
| 68 | |
| 69 | if (read(fd_msr, buf, 8) == 8) { |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 70 | msr.lo = buf[0]; |
| 71 | msr.hi = buf[1]; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 72 | return msr; |
| 73 | } |
| 74 | |
| 75 | if (errno == 5) { |
| 76 | printf(" (*)"); // Not all bits of the MSR could be read |
| 77 | msr_readerror = 1; |
| 78 | } else { |
| 79 | // A severe error. |
| 80 | perror("Could not read() MSR"); |
| 81 | close(fd_msr); |
| 82 | exit(1); |
| 83 | } |
| 84 | |
| 85 | return msr; |
| 86 | } |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 87 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 88 | |
| 89 | int print_intel_core_msrs(void) |
| 90 | { |
| 91 | unsigned int i, core, id; |
| 92 | msr_t msr; |
| 93 | |
| 94 | #define IA32_PLATFORM_ID 0x0017 |
| 95 | #define EBL_CR_POWERON 0x002a |
| 96 | #define FSB_CLK_STS 0x00cd |
| 97 | #define IA32_TIME_STAMP_COUNTER 0x0010 |
| 98 | #define IA32_APIC_BASE 0x001b |
| 99 | |
| 100 | typedef struct { |
| 101 | int number; |
| 102 | char *name; |
| 103 | } msr_entry_t; |
| 104 | |
Tobias Diedrich | 3645e61 | 2010-11-27 14:44:19 +0000 | [diff] [blame] | 105 | /* Pentium III */ |
| 106 | static const msr_entry_t model67x_global_msrs[] = { |
| 107 | { 0x0000, "IA32_P5_MC_ADDR" }, |
| 108 | { 0x0001, "IA32_P5_MC_TYPE" }, |
| 109 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 110 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 111 | { 0x001b, "IA32_APIC_BASE" }, |
| 112 | { 0x002a, "EBL_CR_POWERON" }, |
| 113 | { 0x0033, "TEST_CTL" }, |
| 114 | //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO |
| 115 | { 0x0088, "BBL_CR_D0" }, |
| 116 | { 0x0089, "BBL_CR_D1" }, |
| 117 | { 0x008a, "BBL_CR_D2" }, |
| 118 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 119 | { 0x00c1, "PERFCTR0" }, |
| 120 | { 0x00c2, "PERFCTR1" }, |
| 121 | { 0x00fe, "IA32_MTRRCAP" }, |
| 122 | { 0x0116, "BBL_CR_ADDR" }, |
| 123 | { 0x0118, "BBL_CR_DECC" }, |
| 124 | { 0x0119, "BBL_CR_CTL" }, |
| 125 | //{ 0x011a, "BBL_CR_TRIG" }, |
| 126 | { 0x011b, "BBL_CR_BUSY" }, |
| 127 | { 0x011e, "BBL_CR_CTL3" }, |
| 128 | { 0x0174, "IA32_SYSENTER_CS" }, |
| 129 | { 0x0175, "IA32_SYSENTER_ESP" }, |
| 130 | { 0x0176, "IA32_SYSENTER_EIP" }, |
| 131 | { 0x0179, "IA32_MCG_CAP" }, |
| 132 | { 0x017a, "IA32_MCG_STATUS" }, |
| 133 | { 0x017b, "IA32_MCG_CTL" }, |
| 134 | { 0x0186, "IA32_PERF_EVNTSEL0" }, |
| 135 | { 0x0187, "IA32_PERF_EVNTSEL1" }, |
| 136 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 137 | { 0x01db, "MSR_LASTBRANCHFROMIP" }, |
| 138 | { 0x01dc, "MSR_LASTBRANCHTOIP" }, |
| 139 | { 0x01dd, "MSR_LASTINTFROMIP" }, |
| 140 | { 0x01de, "MSR_LASTINTTOIP" }, |
| 141 | { 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" }, |
| 142 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 143 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 144 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 145 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 146 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 147 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 148 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 149 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 150 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 151 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 152 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 153 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 154 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 155 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 156 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 157 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 158 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 159 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 160 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 161 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 162 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 163 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 164 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 165 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 166 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 167 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 168 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 169 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 170 | { 0x0400, "IA32_MC0_CTL" }, |
| 171 | { 0x0401, "IA32_MC0_STATUS" }, |
| 172 | { 0x0402, "IA32_MC0_ADDR" }, |
| 173 | //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO |
| 174 | { 0x0404, "IA32_MC1_CTL" }, |
| 175 | { 0x0405, "IA32_MC1_STATUS" }, |
| 176 | { 0x0406, "IA32_MC1_ADDR" }, |
| 177 | //{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO |
| 178 | { 0x0408, "IA32_MC2_CTL" }, |
| 179 | { 0x0409, "IA32_MC2_STATUS" }, |
| 180 | { 0x040a, "IA32_MC2_ADDR" }, |
| 181 | //{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO |
| 182 | { 0x040c, "IA32_MC4_CTL" }, |
| 183 | { 0x040d, "IA32_MC4_STATUS" }, |
| 184 | { 0x040e, "IA32_MC4_ADDR" }, |
| 185 | //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO |
| 186 | { 0x0410, "IA32_MC3_CTL" }, |
| 187 | { 0x0411, "IA32_MC3_STATUS" }, |
| 188 | { 0x0412, "IA32_MC3_ADDR" }, |
| 189 | //{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO |
| 190 | }; |
| 191 | |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 192 | static const msr_entry_t model6bx_global_msrs[] = { |
| 193 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 194 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 195 | { 0x001b, "IA32_APIC_BASE" }, |
| 196 | { 0x002a, "EBL_CR_POWERON" }, |
| 197 | { 0x0033, "TEST_CTL" }, |
| 198 | { 0x003f, "THERM_DIODE_OFFSET" }, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 199 | //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 200 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 201 | { 0x00c1, "PERFCTR0" }, |
| 202 | { 0x00c2, "PERFCTR1" }, |
| 203 | { 0x011e, "BBL_CR_CTL3" }, |
| 204 | { 0x0179, "IA32_MCG_CAP" }, |
| 205 | { 0x017a, "IA32_MCG_STATUS" }, |
| 206 | { 0x0198, "IA32_PERF_STATUS" }, |
| 207 | { 0x0199, "IA32_PERF_CONTROL" }, |
| 208 | { 0x019a, "IA32_CLOCK_MODULATION" }, |
| 209 | { 0x01a0, "IA32_MISC_ENABLES" }, |
| 210 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 211 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 212 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 213 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 214 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 215 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 216 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 217 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 218 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 219 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 220 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 221 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 222 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 223 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 224 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 225 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 226 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 227 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 228 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 229 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 230 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 231 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 232 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 233 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 234 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 235 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 236 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 237 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 238 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 239 | { 0x0400, "IA32_MC0_CTL" }, |
| 240 | { 0x0401, "IA32_MC0_STATUS" }, |
| 241 | { 0x0402, "IA32_MC0_ADDR" }, |
| 242 | //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO |
| 243 | { 0x040c, "IA32_MC4_CTL" }, |
| 244 | { 0x040d, "IA32_MC4_STATUS" }, |
| 245 | { 0x040e, "IA32_MC4_ADDR" }, |
| 246 | //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO |
| 247 | }; |
| 248 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 249 | static const msr_entry_t model6ex_global_msrs[] = { |
| 250 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 251 | { 0x002a, "EBL_CR_POWERON" }, |
| 252 | { 0x00cd, "FSB_CLOCK_STS" }, |
| 253 | { 0x00ce, "FSB_CLOCK_VCC" }, |
| 254 | { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" }, |
| 255 | { 0x00e3, "PMG_IO_BASE_ADDR" }, |
| 256 | { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, |
| 257 | { 0x00ee, "EXT_CONFIG" }, |
| 258 | { 0x011e, "BBL_CR_CTL3" }, |
| 259 | { 0x0194, "CLOCK_FLEX_MAX" }, |
| 260 | { 0x0198, "IA32_PERF_STATUS" }, |
| 261 | { 0x01a0, "IA32_MISC_ENABLES" }, |
| 262 | { 0x01aa, "PIC_SENS_CFG" }, |
| 263 | { 0x0400, "IA32_MC0_CTL" }, |
| 264 | { 0x0401, "IA32_MC0_STATUS" }, |
| 265 | { 0x0402, "IA32_MC0_ADDR" }, |
| 266 | //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO |
| 267 | { 0x040c, "IA32_MC4_CTL" }, |
| 268 | { 0x040d, "IA32_MC4_STATUS" }, |
| 269 | { 0x040e, "IA32_MC4_ADDR" }, |
| 270 | //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO |
| 271 | }; |
| 272 | |
| 273 | static const msr_entry_t model6ex_per_core_msrs[] = { |
| 274 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 275 | { 0x001b, "IA32_APIC_BASE" }, |
| 276 | { 0x003a, "IA32_FEATURE_CONTROL" }, |
| 277 | { 0x003f, "IA32_TEMPERATURE_OFFSET" }, |
| 278 | //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO |
| 279 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 280 | { 0x00e7, "IA32_MPERF" }, |
| 281 | { 0x00e8, "IA32_APERF" }, |
| 282 | { 0x00fe, "IA32_MTRRCAP" }, |
| 283 | { 0x015f, "DTS_CAL_CTRL" }, |
| 284 | { 0x0179, "IA32_MCG_CAP" }, |
| 285 | { 0x017a, "IA32_MCG_STATUS" }, |
| 286 | { 0x0199, "IA32_PERF_CONTROL" }, |
| 287 | { 0x019a, "IA32_CLOCK_MODULATION" }, |
| 288 | { 0x019b, "IA32_THERM_INTERRUPT" }, |
| 289 | { 0x019c, "IA32_THERM_STATUS" }, |
| 290 | { 0x019d, "GV_THERM" }, |
| 291 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 292 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 293 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 294 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 295 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 296 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 297 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 298 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 299 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 300 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 301 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 302 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 303 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 304 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 305 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 306 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 307 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 308 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 309 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 310 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 311 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 312 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 313 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 314 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 315 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 316 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 317 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 318 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 319 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 320 | //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO |
| 321 | }; |
| 322 | |
| 323 | static const msr_entry_t model6fx_global_msrs[] = { |
| 324 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 325 | { 0x002a, "EBL_CR_POWERON" }, |
| 326 | { 0x003f, "IA32_TEMPERATURE_OFFSET" }, |
| 327 | { 0x00a8, "EMTTM_CR_TABLE0" }, |
| 328 | { 0x00a9, "EMTTM_CR_TABLE1" }, |
| 329 | { 0x00aa, "EMTTM_CR_TABLE2" }, |
| 330 | { 0x00ab, "EMTTM_CR_TABLE3" }, |
| 331 | { 0x00ac, "EMTTM_CR_TABLE4" }, |
| 332 | { 0x00ad, "EMTTM_CR_TABLE5" }, |
| 333 | { 0x00cd, "FSB_CLOCK_STS" }, |
| 334 | { 0x00e2, "PMG_CST_CONFIG_CONTROL" }, |
| 335 | { 0x00e3, "PMG_IO_BASE_ADDR" }, |
| 336 | { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, |
| 337 | { 0x00ee, "EXT_CONFIG" }, |
| 338 | { 0x011e, "BBL_CR_CTL3" }, |
| 339 | { 0x0194, "CLOCK_FLEX_MAX" }, |
| 340 | { 0x0198, "IA32_PERF_STATUS" }, |
| 341 | { 0x01a0, "IA32_MISC_ENABLES" }, |
| 342 | { 0x01aa, "PIC_SENS_CFG" }, |
| 343 | { 0x0400, "IA32_MC0_CTL" }, |
| 344 | { 0x0401, "IA32_MC0_STATUS" }, |
| 345 | { 0x0402, "IA32_MC0_ADDR" }, |
| 346 | //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO |
| 347 | { 0x040c, "IA32_MC4_CTL" }, |
| 348 | { 0x040d, "IA32_MC4_STATUS" }, |
| 349 | { 0x040e, "IA32_MC4_ADDR" }, |
| 350 | //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO |
| 351 | }; |
| 352 | |
| 353 | static const msr_entry_t model6fx_per_core_msrs[] = { |
| 354 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 355 | { 0x001b, "IA32_APIC_BASE" }, |
| 356 | { 0x003a, "IA32_FEATURE_CONTROL" }, |
| 357 | //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO |
| 358 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 359 | { 0x00e1, "SMM_CST_MISC_INFO" }, |
| 360 | { 0x00e7, "IA32_MPERF" }, |
| 361 | { 0x00e8, "IA32_APERF" }, |
| 362 | { 0x00fe, "IA32_MTRRCAP" }, |
| 363 | { 0x0179, "IA32_MCG_CAP" }, |
| 364 | { 0x017a, "IA32_MCG_STATUS" }, |
| 365 | { 0x0199, "IA32_PERF_CONTROL" }, |
| 366 | { 0x019a, "IA32_THERM_CTL" }, |
| 367 | { 0x019b, "IA32_THERM_INTERRUPT" }, |
| 368 | { 0x019c, "IA32_THERM_STATUS" }, |
| 369 | { 0x019d, "MSR_THERM2_CTL" }, |
| 370 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 371 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 372 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 373 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 374 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 375 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 376 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 377 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 378 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 379 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 380 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 381 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 382 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 383 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 384 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 385 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 386 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 387 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 388 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 389 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 390 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 391 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 392 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 393 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 394 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 395 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 396 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 397 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 398 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 399 | //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO |
| 400 | }; |
| 401 | |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 402 | /* Pentium 4 and XEON */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 403 | /* |
| 404 | * All MSRs per |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 405 | * |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 406 | * Intel 64 and IA-32 Architectures Software Developer's Manual |
| 407 | * Volume 3B: System Programming Guide, Part 2 |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 408 | * |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 409 | * Table B-5, B-7 |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 410 | */ |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 411 | static const msr_entry_t modelf2x_global_msrs[] = { |
| 412 | { 0x0000, "IA32_P5_MC_ADDR" }, |
| 413 | { 0x0001, "IA32_P5_MC_TYPE" }, |
| 414 | /* 0x6: Not available in model 2. */ |
| 415 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 416 | { 0x002a, "MSR_EBC_HARD_POWERON" }, |
| 417 | { 0x002b, "MSR_EBC_SOFT_POWRON" }, |
| 418 | /* 0x2c: Not available in model 2. */ |
| 419 | // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, |
| 420 | { 0x019c, "IA32_THERM_STATUS" }, |
| 421 | /* 0x19d: Not available in model 2. */ |
| 422 | { 0x01a0, "IA32_MISC_ENABLE" }, |
| 423 | /* 0x1a1: Not available in model 2. */ |
| 424 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 425 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 426 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 427 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 428 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 429 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 430 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 431 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 432 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 433 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 434 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 435 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 436 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 437 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 438 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 439 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 440 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 441 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 442 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 443 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 444 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 445 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 446 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 447 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 448 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 449 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 450 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 451 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 452 | { 0x0300, "MSR_BPU_COUNTER0" }, |
| 453 | { 0x0301, "MSR_BPU_COUNTER1" }, |
| 454 | { 0x0302, "MSR_BPU_COUNTER2" }, |
| 455 | { 0x0303, "MSR_BPU_COUNTER3" }, |
| 456 | { 0x0304, "MSR_MS_COUNTER0" }, |
| 457 | { 0x0305, "MSR_MS_COUNTER1" }, |
| 458 | { 0x0306, "MSR_MS_COUNTER2" }, |
| 459 | { 0x0307, "MSR_MS_COUNTER3" }, |
| 460 | { 0x0308, "MSR_FLAME_COUNTER0" }, |
| 461 | { 0x0309, "MSR_FLAME_COUNTER1" }, |
| 462 | { 0x030a, "MSR_FLAME_COUNTER2" }, |
| 463 | { 0x030b, "MSR_FLAME_COUNTER3" }, |
| 464 | { 0x030c, "MSR_IQ_COUNTER0" }, |
| 465 | { 0x030d, "MSR_IQ_COUNTER1" }, |
| 466 | { 0x030e, "MSR_IQ_COUNTER2" }, |
| 467 | { 0x030f, "MSR_IQ_COUNTER3" }, |
| 468 | { 0x0310, "MSR_IQ_COUNTER4" }, |
| 469 | { 0x0311, "MSR_IQ_COUNTER5" }, |
| 470 | { 0x0360, "MSR_BPU_CCCR0" }, |
| 471 | { 0x0361, "MSR_BPU_CCCR1" }, |
| 472 | { 0x0362, "MSR_BPU_CCCR2" }, |
| 473 | { 0x0363, "MSR_BPU_CCCR3" }, |
| 474 | { 0x0364, "MSR_MS_CCCR0" }, |
| 475 | { 0x0365, "MSR_MS_CCCR1" }, |
| 476 | { 0x0366, "MSR_MS_CCCR2" }, |
| 477 | { 0x0367, "MSR_MS_CCCR3" }, |
| 478 | { 0x0368, "MSR_FLAME_CCCR0" }, |
| 479 | { 0x0369, "MSR_FLAME_CCCR1" }, |
| 480 | { 0x036a, "MSR_FLAME_CCCR2" }, |
| 481 | { 0x036b, "MSR_FLAME_CCCR3" }, |
| 482 | { 0x036c, "MSR_IQ_CCCR0" }, |
| 483 | { 0x036d, "MSR_IQ_CCCR1" }, |
| 484 | { 0x036e, "MSR_IQ_CCCR2" }, |
| 485 | { 0x036f, "MSR_IQ_CCCR3" }, |
| 486 | { 0x0370, "MSR_IQ_CCCR4" }, |
| 487 | { 0x0371, "MSR_IQ_CCCR5" }, |
| 488 | { 0x03a0, "MSR_BSU_ESCR0" }, |
| 489 | { 0x03a1, "MSR_BSU_ESCR1" }, |
| 490 | { 0x03a2, "MSR_FSB_ESCR0" }, |
| 491 | { 0x03a3, "MSR_FSB_ESCR1" }, |
| 492 | { 0x03a4, "MSR_FIRM_ESCR0" }, |
| 493 | { 0x03a5, "MSR_FIRM_ESCR1" }, |
| 494 | { 0x03a6, "MSR_FLAME_ESCR0" }, |
| 495 | { 0x03a7, "MSR_FLAME_ESCR1" }, |
| 496 | { 0x03a8, "MSR_DAC_ESCR0" }, |
| 497 | { 0x03a9, "MSR_DAC_ESCR1" }, |
| 498 | { 0x03aa, "MSR_MOB_ESCR0" }, |
| 499 | { 0x03ab, "MSR_MOB_ESCR1" }, |
| 500 | { 0x03ac, "MSR_PMH_ESCR0" }, |
| 501 | { 0x03ad, "MSR_PMH_ESCR1" }, |
| 502 | { 0x03ae, "MSR_SAAT_ESCR0" }, |
| 503 | { 0x03af, "MSR_SAAT_ESCR1" }, |
| 504 | { 0x03b0, "MSR_U2L_ESCR0" }, |
| 505 | { 0x03b1, "MSR_U2L_ESCR1" }, |
| 506 | { 0x03b2, "MSR_BPU_ESCR0" }, |
| 507 | { 0x03b3, "MSR_BPU_ESCR1" }, |
| 508 | { 0x03b4, "MSR_IS_ESCR0" }, |
| 509 | { 0x03b5, "MSR_BPU_ESCR1" }, |
| 510 | { 0x03b6, "MSR_ITLB_ESCR0" }, |
| 511 | { 0x03b7, "MSR_ITLB_ESCR1" }, |
| 512 | { 0x03b8, "MSR_CRU_ESCR0" }, |
| 513 | { 0x03b9, "MSR_CRU_ESCR1" }, |
| 514 | { 0x03ba, "MSR_IQ_ESCR0" }, |
| 515 | { 0x03bb, "MSR_IQ_ESCR1" }, |
| 516 | { 0x03bc, "MSR_RAT_ESCR0" }, |
| 517 | { 0x03bd, "MSR_RAT_ESCR1" }, |
| 518 | { 0x03be, "MSR_SSU_ESCR0" }, |
| 519 | { 0x03c0, "MSR_MS_ESCR0" }, |
| 520 | { 0x03c1, "MSR_MS_ESCR1" }, |
| 521 | { 0x03c2, "MSR_TBPU_ESCR0" }, |
| 522 | { 0x03c3, "MSR_TBPU_ESCR1" }, |
| 523 | { 0x03c4, "MSR_TC_ESCR0" }, |
| 524 | { 0x03c5, "MSR_TC_ESCR1" }, |
| 525 | { 0x03c8, "MSR_IX_ESCR0" }, |
| 526 | { 0x03c9, "MSR_IX_ESCR1" }, |
| 527 | { 0x03ca, "MSR_ALF_ESCR0" }, |
| 528 | { 0x03cb, "MSR_ALF_ESCR1" }, |
| 529 | { 0x03cc, "MSR_CRU_ESCR2" }, |
| 530 | { 0x03cd, "MSR_CRU_ESCR3" }, |
| 531 | { 0x03e0, "MSR_CRU_ESCR4" }, |
| 532 | { 0x03e1, "MSR_CRU_ESCR5" }, |
| 533 | { 0x03f0, "MSR_TC_PRECISE_EVENT" }, |
| 534 | { 0x03f1, "MSR_PEBS_ENABLE" }, |
| 535 | { 0x03f2, "MSR_PEBS_MATRIX_VERT" }, |
| 536 | |
| 537 | /* |
| 538 | * All MCX_ADDR and MCX_MISC MSRs depend on a bit being |
| 539 | * set in MCX_STATUS. |
| 540 | */ |
| 541 | { 0x400, "IA32_MC0_CTL" }, |
| 542 | { 0x401, "IA32_MC0_STATUS" }, |
| 543 | { 0x402, "IA32_MC0_ADDR" }, |
| 544 | { 0x403, "IA32_MC0_MISC" }, |
| 545 | { 0x404, "IA32_MC1_CTL" }, |
| 546 | { 0x405, "IA32_MC1_STATUS" }, |
| 547 | { 0x406, "IA32_MC1_ADDR" }, |
| 548 | { 0x407, "IA32_MC1_MISC" }, |
| 549 | { 0x408, "IA32_MC2_CTL" }, |
| 550 | { 0x409, "IA32_MC2_STATUS" }, |
| 551 | { 0x40a, "IA32_MC2_ADDR" }, |
| 552 | { 0x40b, "IA32_MC2_MISC" }, |
| 553 | { 0x40c, "IA32_MC3_CTL" }, |
| 554 | { 0x40d, "IA32_MC3_STATUS" }, |
| 555 | { 0x40e, "IA32_MC3_ADDR" }, |
| 556 | { 0x40f, "IA32_MC3_MISC" }, |
| 557 | { 0x410, "IA32_MC4_CTL" }, |
| 558 | { 0x411, "IA32_MC4_STATUS" }, |
| 559 | { 0x412, "IA32_MC4_ADDR" }, |
| 560 | { 0x413, "IA32_MC4_MISC" }, |
| 561 | }; |
| 562 | |
| 563 | static const msr_entry_t modelf2x_per_core_msrs[] = { |
| 564 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 565 | { 0x001b, "IA32_APIC_BASE" }, |
| 566 | /* 0x3a: Not available in model 2. */ |
| 567 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 568 | /* 0x9b: Not available in model 2. */ |
| 569 | { 0x00fe, "IA32_MTRRCAP" }, |
| 570 | { 0x0174, "IA32_SYSENTER_CS" }, |
| 571 | { 0x0175, "IA32_SYSENTER_ESP" }, |
| 572 | { 0x0176, "IA32_SYSENTER_EIP" }, |
| 573 | { 0x0179, "IA32_MCG_CAP" }, |
| 574 | { 0x017a, "IA32_MCG_STATUS" }, |
| 575 | { 0x017b, "IA32_MCG_CTL" }, |
| 576 | { 0x0180, "MSR_MCG_RAX" }, |
| 577 | { 0x0181, "MSR_MCG_RBX" }, |
| 578 | { 0x0182, "MSR_MCG_RCX" }, |
| 579 | { 0x0183, "MSR_MCG_RDX" }, |
| 580 | { 0x0184, "MSR_MCG_RSI" }, |
| 581 | { 0x0185, "MSR_MCG_RDI" }, |
| 582 | { 0x0186, "MSR_MCG_RBP" }, |
| 583 | { 0x0187, "MSR_MCG_RSP" }, |
| 584 | { 0x0188, "MSR_MCG_RFLAGS" }, |
| 585 | { 0x0189, "MSR_MCG_RIP" }, |
| 586 | { 0x018a, "MSR_MCG_MISC" }, |
| 587 | /* 0x18b-0x18f: Reserved */ |
| 588 | { 0x0190, "MSR_MCG_R8" }, |
| 589 | { 0x0191, "MSR_MCG_R9" }, |
| 590 | { 0x0192, "MSR_MCG_R10" }, |
| 591 | { 0x0193, "MSR_MCG_R11" }, |
| 592 | { 0x0194, "MSR_MCG_R12" }, |
| 593 | { 0x0195, "MSR_MCG_R13" }, |
| 594 | { 0x0196, "MSR_MCG_R14" }, |
| 595 | { 0x0197, "MSR_MCG_R15" }, |
| 596 | /* 0x198: Not available in model 2. */ |
| 597 | /* 0x199: Not available in model 2. */ |
| 598 | { 0x019a, "IA32_CLOCK_MODULATION" }, |
| 599 | { 0x019b, "IA32_THERM_INTERRUPT" }, |
| 600 | { 0x01a0, "IA32_MISC_ENABLE" }, |
| 601 | { 0x01d7, "MSR_LER_FROM_LIP" }, |
| 602 | { 0x01d8, "MSR_LER_TO_LIP" }, |
| 603 | { 0x01d9, "MSR_DEBUGCTLA" }, |
| 604 | { 0x01da, "MSR_LASTBRANCH_TOS" }, |
| 605 | { 0x01db, "MSR_LASTBRANCH_0" }, |
| 606 | { 0x01dd, "MSR_LASTBRANCH_2" }, |
| 607 | { 0x01de, "MSR_LASTBRANCH_3" }, |
| 608 | { 0x0277, "IA32_PAT" }, |
| 609 | /* 0x480-0x48b : Not available in model 2. */ |
| 610 | { 0x0600, "IA32_DS_AREA" }, |
| 611 | /* 0x0680 - 0x06cf Branch Records Skipped */ |
| 612 | }; |
| 613 | |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 614 | static const msr_entry_t modelf4x_global_msrs[] = { |
| 615 | { 0x0000, "IA32_P5_MC_ADDR" }, |
| 616 | { 0x0001, "IA32_P5_MC_TYPE" }, |
| 617 | { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, |
| 618 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 619 | { 0x002a, "MSR_EBC_HARD_POWERON" }, |
| 620 | { 0x002b, "MSR_EBC_SOFT_POWRON" }, |
| 621 | { 0x002c, "MSR_EBC_FREQUENCY_ID" }, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 622 | // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 623 | { 0x019c, "IA32_THERM_STATUS" }, |
| 624 | { 0x019d, "MSR_THERM2_CTL" }, |
| 625 | { 0x01a0, "IA32_MISC_ENABLE" }, |
| 626 | { 0x01a1, "MSR_PLATFORM_BRV" }, |
| 627 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 628 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 629 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 630 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 631 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 632 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 633 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 634 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 635 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 636 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 637 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 638 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 639 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 640 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 641 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 642 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 643 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 644 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 645 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 646 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 647 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 648 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 649 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 650 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 651 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 652 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 653 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 654 | { 0x02ff, "IA32_MTRR_DEF_TYPE" }, |
| 655 | { 0x0300, "MSR_BPU_COUNTER0" }, |
| 656 | { 0x0301, "MSR_BPU_COUNTER1" }, |
| 657 | { 0x0302, "MSR_BPU_COUNTER2" }, |
| 658 | { 0x0303, "MSR_BPU_COUNTER3" }, |
| 659 | /* Skipped through 0x3ff for now*/ |
| 660 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 661 | /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 662 | * set in MCX_STATUS */ |
| 663 | { 0x400, "IA32_MC0_CTL" }, |
| 664 | { 0x401, "IA32_MC0_STATUS" }, |
| 665 | { 0x402, "IA32_MC0_ADDR" }, |
| 666 | { 0x403, "IA32_MC0_MISC" }, |
| 667 | { 0x404, "IA32_MC1_CTL" }, |
| 668 | { 0x405, "IA32_MC1_STATUS" }, |
| 669 | { 0x406, "IA32_MC1_ADDR" }, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 670 | { 0x407, "IA32_MC1_MISC" }, |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 671 | { 0x408, "IA32_MC2_CTL" }, |
| 672 | { 0x409, "IA32_MC2_STATUS" }, |
| 673 | { 0x40a, "IA32_MC2_ADDR" }, |
| 674 | { 0x40b, "IA32_MC2_MISC" }, |
| 675 | { 0x40c, "IA32_MC3_CTL" }, |
| 676 | { 0x40d, "IA32_MC3_STATUS" }, |
| 677 | { 0x40e, "IA32_MC3_ADDR" }, |
| 678 | { 0x40f, "IA32_MC3_MISC" }, |
| 679 | { 0x410, "IA32_MC4_CTL" }, |
| 680 | { 0x411, "IA32_MC4_STATUS" }, |
| 681 | { 0x412, "IA32_MC4_ADDR" }, |
| 682 | { 0x413, "IA32_MC4_MISC" }, |
| 683 | }; |
| 684 | |
| 685 | static const msr_entry_t modelf4x_per_core_msrs[] = { |
| 686 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 687 | { 0x001b, "IA32_APIC_BASE" }, |
| 688 | { 0x003a, "IA32_FEATURE_CONTROL" }, |
| 689 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 690 | { 0x009b, "IA32_SMM_MONITOR_CTL" }, |
| 691 | { 0x00fe, "IA32_MTRRCAP" }, |
| 692 | { 0x0174, "IA32_SYSENTER_CS" }, |
| 693 | { 0x0175, "IA32_SYSENTER_ESP" }, |
| 694 | { 0x0176, "IA32_SYSENTER_EIP" }, |
| 695 | { 0x0179, "IA32_MCG_CAP" }, |
| 696 | { 0x017a, "IA32_MCG_STATUS" }, |
| 697 | { 0x0180, "MSR_MCG_RAX" }, |
| 698 | { 0x0181, "MSR_MCG_RBX" }, |
| 699 | { 0x0182, "MSR_MCG_RCX" }, |
| 700 | { 0x0183, "MSR_MCG_RDX" }, |
| 701 | { 0x0184, "MSR_MCG_RSI" }, |
| 702 | { 0x0185, "MSR_MCG_RDI" }, |
| 703 | { 0x0186, "MSR_MCG_RBP" }, |
| 704 | { 0x0187, "MSR_MCG_RSP" }, |
| 705 | { 0x0188, "MSR_MCG_RFLAGS" }, |
| 706 | { 0x0189, "MSR_MCG_RIP" }, |
| 707 | { 0x018a, "MSR_MCG_MISC" }, |
| 708 | // 0x18b-f Reserved |
| 709 | { 0x0190, "MSR_MCG_R8" }, |
| 710 | { 0x0191, "MSR_MCG_R9" }, |
| 711 | { 0x0192, "MSR_MCG_R10" }, |
| 712 | { 0x0193, "MSR_MCG_R11" }, |
| 713 | { 0x0194, "MSR_MCG_R12" }, |
| 714 | { 0x0195, "MSR_MCG_R13" }, |
| 715 | { 0x0196, "MSR_MCG_R14" }, |
| 716 | { 0x0197, "MSR_MCG_R15" }, |
| 717 | { 0x0198, "IA32_PERF_STATUS" }, |
| 718 | { 0x0199, "IA32_PERF_CTL" }, |
| 719 | { 0x019a, "IA32_CLOCK_MODULATION" }, |
| 720 | { 0x019b, "IA32_THERM_INTERRUPT" }, |
| 721 | { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific |
| 722 | { 0x01d7, "MSR_LER_FROM_LIP" }, |
| 723 | { 0x01d8, "MSR_LER_TO_LIP" }, |
| 724 | { 0x01d9, "MSR_DEBUGCTLA" }, |
| 725 | { 0x01da, "MSR_LASTBRANCH_TOS" }, |
| 726 | { 0x0277, "IA32_PAT" }, |
| 727 | /** Virtualization |
| 728 | { 0x480, "IA32_VMX_BASIC" }, |
| 729 | through |
| 730 | { 0x48b, "IA32_VMX_PROCBASED_CTLS2" }, |
| 731 | Not implemented in my CPU |
| 732 | */ |
| 733 | { 0x0600, "IA32_DS_AREA" }, |
| 734 | /* 0x0680 - 0x06cf Branch Records Skipped */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 735 | |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 736 | }; |
| 737 | |
Olivier Langlois | 70f3987 | 2013-01-25 00:49:46 -0500 | [diff] [blame] | 738 | /* Atom N455 |
| 739 | * |
| 740 | * This should apply to the following processors: |
| 741 | * 06_1CH |
| 742 | * 06_26H |
| 743 | * 06_27H |
| 744 | * 06_35 |
| 745 | * 06_36 |
| 746 | */ |
| 747 | /* |
| 748 | * All MSRs per |
| 749 | * |
| 750 | * Intel 64 and IA-32 Architectures Software Developer's Manual |
| 751 | * Volume 3C: System Programming Guide, Part 3 |
| 752 | * Order Number 326019 |
| 753 | * January 2013 |
| 754 | * |
| 755 | * Table 35-4, 35-5 |
| 756 | * |
| 757 | * For now it has only been tested with 06_1CH. |
| 758 | */ |
| 759 | static const msr_entry_t model6_atom_global_msrs[] = { |
| 760 | { 0x0000, "IA32_P5_MC_ADDR" }, |
| 761 | { 0x0001, "IA32_P5_MC_TYPE" }, |
| 762 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 763 | { 0x0017, "IA32_PLATFORM_ID" }, |
| 764 | { 0x002a, "MSR_EBC_HARD_POWERON" }, |
| 765 | { 0x00cd, "MSR_FSB_FREQ" }, |
| 766 | { 0x00fe, "IA32_MTRRCAP" }, |
| 767 | { 0x011e, "MSR_BBL_CR_CTL3" }, |
| 768 | { 0x0198, "IA32_PERF_STATUS" }, |
| 769 | { 0x019d, "MSR_THERM2_CTL" }, |
| 770 | { 0x0200, "IA32_MTRR_PHYSBASE0" }, |
| 771 | { 0x0201, "IA32_MTRR_PHYSMASK0" }, |
| 772 | { 0x0202, "IA32_MTRR_PHYSBASE1" }, |
| 773 | { 0x0203, "IA32_MTRR_PHYSMASK1" }, |
| 774 | { 0x0204, "IA32_MTRR_PHYSBASE2" }, |
| 775 | { 0x0205, "IA32_MTRR_PHYSMASK2" }, |
| 776 | { 0x0206, "IA32_MTRR_PHYSBASE3" }, |
| 777 | { 0x0207, "IA32_MTRR_PHYSMASK3" }, |
| 778 | { 0x0208, "IA32_MTRR_PHYSBASE4" }, |
| 779 | { 0x0209, "IA32_MTRR_PHYSMASK4" }, |
| 780 | { 0x020a, "IA32_MTRR_PHYSBASE5" }, |
| 781 | { 0x020b, "IA32_MTRR_PHYSMASK5" }, |
| 782 | { 0x020c, "IA32_MTRR_PHYSBASE6" }, |
| 783 | { 0x020d, "IA32_MTRR_PHYSMASK6" }, |
| 784 | { 0x020e, "IA32_MTRR_PHYSBASE7" }, |
| 785 | { 0x020f, "IA32_MTRR_PHYSMASK7" }, |
| 786 | { 0x0250, "IA32_MTRR_FIX64K_00000" }, |
| 787 | { 0x0258, "IA32_MTRR_FIX16K_80000" }, |
| 788 | { 0x0259, "IA32_MTRR_FIX16K_A0000" }, |
| 789 | { 0x0268, "IA32_MTRR_FIX4K_C0000" }, |
| 790 | { 0x0269, "IA32_MTRR_FIX4K_C8000" }, |
| 791 | { 0x026a, "IA32_MTRR_FIX4K_D0000" }, |
| 792 | { 0x026b, "IA32_MTRR_FIX4K_D8000" }, |
| 793 | { 0x026c, "IA32_MTRR_FIX4K_E0000" }, |
| 794 | { 0x026d, "IA32_MTRR_FIX4K_E8000" }, |
| 795 | { 0x026e, "IA32_MTRR_FIX4K_F0000" }, |
| 796 | { 0x026f, "IA32_MTRR_FIX4K_F8000" }, |
| 797 | { 0x0345, "IA32_PERF_CAPABILITIES" }, |
| 798 | { 0x400, "IA32_MC0_CTL" }, |
| 799 | { 0x401, "IA32_MC0_STATUS" }, |
| 800 | { 0x402, "IA32_MC0_ADDR" }, |
| 801 | { 0x404, "IA32_MC1_CTL" }, |
| 802 | { 0x405, "IA32_MC1_STATUS" }, |
| 803 | { 0x408, "IA32_MC2_CTL" }, |
| 804 | { 0x409, "IA32_MC2_STATUS" }, |
| 805 | { 0x40a, "IA32_MC2_ADDR" }, |
| 806 | { 0x40c, "IA32_MC3_CTL" }, |
| 807 | { 0x40d, "IA32_MC3_STATUS" }, |
| 808 | { 0x40e, "IA32_MC3_ADDR" }, |
| 809 | { 0x410, "IA32_MC4_CTL" }, |
| 810 | { 0x411, "IA32_MC4_STATUS" }, |
| 811 | { 0x412, "IA32_MC4_ADDR" }, |
| 812 | /* |
| 813 | * Only 06_27C has the following MSRs |
| 814 | */ |
| 815 | /* |
| 816 | { 0x03f8, "MSR_PKG_C2_RESIDENCY" }, |
| 817 | { 0x03f9, "MSR_PKG_C4_RESIDENCY" }, |
| 818 | { 0x03fa, "MSR_PKG_C6_RESIDENCY" }, |
| 819 | */ |
| 820 | }; |
| 821 | |
| 822 | static const msr_entry_t model6_atom_per_core_msrs[] = { |
| 823 | { 0x0006, "IA32_MONITOR_FILTER_SIZE" }, |
| 824 | { 0x0010, "IA32_TIME_STAMP_COUNTER" }, |
| 825 | { 0x001b, "IA32_APIC_BASE" }, |
| 826 | { 0x003a, "IA32_FEATURE_CONTROL" }, |
| 827 | { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" }, |
| 828 | { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" }, |
| 829 | { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" }, |
| 830 | { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" }, |
| 831 | { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" }, |
| 832 | { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" }, |
| 833 | { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" }, |
| 834 | { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" }, |
| 835 | { 0x0060, "MSR_LASTBRANCH_0_TO_IP" }, |
| 836 | { 0x0061, "MSR_LASTBRANCH_1_TO_IP" }, |
| 837 | { 0x0062, "MSR_LASTBRANCH_2_TO_IP" }, |
| 838 | { 0x0063, "MSR_LASTBRANCH_3_TO_IP" }, |
| 839 | { 0x0064, "MSR_LASTBRANCH_4_TO_IP" }, |
| 840 | { 0x0065, "MSR_LASTBRANCH_5_TO_IP" }, |
| 841 | { 0x0066, "MSR_LASTBRANCH_6_TO_IP" }, |
| 842 | { 0x0067, "MSR_LASTBRANCH_7_TO_IP" }, |
| 843 | /* Write register */ |
| 844 | /* |
| 845 | { 0x0079, "IA32_BIOS_UPDT_TRIG" }, |
| 846 | */ |
| 847 | { 0x008b, "IA32_BIOS_SIGN_ID" }, |
| 848 | { 0x00c1, "IA32_PMC0" }, |
| 849 | { 0x00c2, "IA32_PMC1" }, |
| 850 | { 0x00e7, "IA32_MPERF" }, |
| 851 | { 0x00e8, "IA32_APERF" }, |
| 852 | { 0x0174, "IA32_SYSENTER_CS" }, |
| 853 | { 0x0175, "IA32_SYSENTER_ESP" }, |
| 854 | { 0x0176, "IA32_SYSENTER_EIP" }, |
| 855 | { 0x017a, "IA32_MCG_STATUS" }, |
| 856 | { 0x0186, "IA32_PERF_EVNTSEL0" }, |
| 857 | { 0x0187, "IA32_PERF_EVNTSEL1" }, |
| 858 | { 0x0199, "IA32_PERF_CONTROL" }, |
| 859 | { 0x019a, "IA32_CLOCK_MODULATION" }, |
| 860 | { 0x019b, "IA32_THERM_INTERRUPT" }, |
| 861 | { 0x019c, "IA32_THERM_STATUS" }, |
| 862 | { 0x01a0, "IA32_MISC_ENABLES" }, |
| 863 | { 0x01c9, "MSR_LASTBRANCH_TOS" }, |
| 864 | { 0x01d9, "IA32_DEBUGCTL" }, |
| 865 | { 0x01dd, "MSR_LER_FROM_LIP" }, |
| 866 | { 0x01de, "MSR_LER_TO_LIP" }, |
| 867 | { 0x0277, "IA32_PAT" }, |
| 868 | { 0x0309, "IA32_FIXED_CTR0" }, |
| 869 | { 0x030a, "IA32_FIXED_CTR1" }, |
| 870 | { 0x030b, "IA32_FIXED_CTR2" }, |
| 871 | { 0x038d, "IA32_FIXED_CTR_CTRL" }, |
| 872 | { 0x038e, "IA32_PERF_GLOBAL_STATUS" }, |
| 873 | { 0x038f, "IA32_PERF_GLOBAL_CTRL" }, |
| 874 | { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" }, |
| 875 | { 0x03f1, "MSR_PEBS_ENABLE" }, |
| 876 | { 0x0480, "IA32_VMX_BASIC" }, |
| 877 | { 0x0481, "IA32_VMX_PINBASED_CTLS" }, |
| 878 | { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, |
| 879 | { 0x0483, "IA32_VMX_EXIT_CTLS" }, |
| 880 | { 0x0484, "IA32_VMX_ENTRY_CTLS" }, |
| 881 | { 0x0485, "IA32_VMX_MISC" }, |
| 882 | { 0x0486, "IA32_VMX_CR0_FIXED0" }, |
| 883 | { 0x0487, "IA32_VMX_CR0_FIXED1" }, |
| 884 | { 0x0488, "IA32_VMX_CR4_FIXED0" }, |
| 885 | { 0x0489, "IA32_VMX_CR4_FIXED1" }, |
| 886 | { 0x048a, "IA32_VMX_VMCS_ENUM" }, |
| 887 | { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, |
| 888 | { 0x0600, "IA32_DS_AREA" }, |
| 889 | }; |
| 890 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 891 | typedef struct { |
| 892 | unsigned int model; |
| 893 | const msr_entry_t *global_msrs; |
| 894 | unsigned int num_global_msrs; |
| 895 | const msr_entry_t *per_core_msrs; |
| 896 | unsigned int num_per_core_msrs; |
| 897 | } cpu_t; |
| 898 | |
| 899 | cpu_t cpulist[] = { |
Tobias Diedrich | 3645e61 | 2010-11-27 14:44:19 +0000 | [diff] [blame] | 900 | { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 }, |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 901 | { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 }, |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 902 | { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, |
| 903 | { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 904 | { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) }, |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 905 | { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) }, |
Olivier Langlois | 70f3987 | 2013-01-25 00:49:46 -0500 | [diff] [blame] | 906 | { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 907 | }; |
| 908 | |
| 909 | cpu_t *cpu = NULL; |
| 910 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 911 | /* Get CPU family and model, not the stepping |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 912 | * (TODO: extended family/model) |
| 913 | */ |
Stefan Reinauer | 74cd5698 | 2010-06-01 10:04:28 +0000 | [diff] [blame] | 914 | id = cpuid(1) & 0xfffff0; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 915 | for (i = 0; i < ARRAY_SIZE(cpulist); i++) { |
| 916 | if(cpulist[i].model == id) { |
| 917 | cpu = &cpulist[i]; |
| 918 | break; |
| 919 | } |
| 920 | } |
| 921 | |
| 922 | if (!cpu) { |
| 923 | printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id); |
| 924 | return -1; |
| 925 | } |
| 926 | |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 927 | #ifndef __DARWIN__ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 928 | fd_msr = open("/dev/cpu/0/msr", O_RDWR); |
| 929 | if (fd_msr < 0) { |
| 930 | perror("Error while opening /dev/cpu/0/msr"); |
| 931 | printf("Did you run 'modprobe msr'?\n"); |
| 932 | return -1; |
| 933 | } |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 934 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 935 | |
| 936 | printf("\n===================== SHARED MSRs (All Cores) =====================\n"); |
| 937 | |
| 938 | for (i = 0; i < cpu->num_global_msrs; i++) { |
| 939 | msr = rdmsr(cpu->global_msrs[i].number); |
| 940 | printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", |
| 941 | cpu->global_msrs[i].number, msr.hi, msr.lo, |
| 942 | cpu->global_msrs[i].name); |
| 943 | } |
| 944 | |
| 945 | close(fd_msr); |
| 946 | |
| 947 | for (core = 0; core < 8; core++) { |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 948 | #ifndef __DARWIN__ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 949 | char msrfilename[64]; |
| 950 | memset(msrfilename, 0, 64); |
Paul Menzel | 5f3754e | 2013-04-05 00:12:21 +0200 | [diff] [blame] | 951 | sprintf(msrfilename, "/dev/cpu/%u/msr", core); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 952 | |
| 953 | fd_msr = open(msrfilename, O_RDWR); |
| 954 | |
| 955 | /* If the file is not there, we're probably through. No error, |
| 956 | * since we successfully opened /dev/cpu/0/msr before. |
| 957 | */ |
| 958 | if (fd_msr < 0) |
| 959 | break; |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 960 | #endif |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 961 | if (cpu->num_per_core_msrs) |
Paul Menzel | 5f3754e | 2013-04-05 00:12:21 +0200 | [diff] [blame] | 962 | printf("\n====================== UNIQUE MSRs (core %u) ======================\n", core); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 963 | |
| 964 | for (i = 0; i < cpu->num_per_core_msrs; i++) { |
| 965 | msr = rdmsr(cpu->per_core_msrs[i].number); |
| 966 | printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n", |
| 967 | cpu->per_core_msrs[i].number, msr.hi, msr.lo, |
| 968 | cpu->per_core_msrs[i].name); |
| 969 | } |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 970 | #ifndef __DARWIN__ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 971 | close(fd_msr); |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 972 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 973 | } |
| 974 | |
Stefan Reinauer | f7f2f25 | 2009-09-01 09:52:14 +0000 | [diff] [blame] | 975 | #ifndef __DARWIN__ |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 976 | if (msr_readerror) |
| 977 | printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 978 | #endif |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 979 | return 0; |
| 980 | } |